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? 2008 microchip technology inc. preliminary ds61143e pic32mx3xx/4xx family data sheet 64/100-pin general purpose and usb 32-bit flash microcontrollers
ds61143e-page ii preliminary ? 2008 microchip technology inc. information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. it is your responsibility to ensure that your application meets with your specifications. microchip makes no representations or warranties of any kind whether express or implied, written or oral, statutory or otherwise, related to the information, including but not limited to its condition, quality, performance, merchantability or fitness for purpose . microchip disclaims all liability arising from this information and its use. use of microchip devices in life support and/or safety applications is entirely at the buyer?s risk, and the buyer agrees to defend, indemnify and hold harmless microchip from any and all damages, claims, suits, or expenses resulting from such use. no licenses are conveyed, implicitly or otherwise, under any microchip intellectual property rights. trademarks the microchip name and logo, the microchip logo, accuron, dspic, k ee l oq , k ee l oq logo, mplab, pic, picmicro, picstart, rfpic and smartshunt are registered trademarks of microchip technology incorporated in the u.s.a. and other countries. filterlab, linear active thermistor, mxdev, mxlab, seeval, smartsensor and the embedded control solutions company are registered trademarks of microchip technology incorporated in the u.s.a. analog-for-the-digital age, appl ication maestro, codeguard, dspicdem, dspicdem.net, dspicworks, dsspeak, ecan, economonitor, fansense, in-circuit serial programming, icsp, icepic, mindi, miwi, mpasm, mplab certified logo, mplib, mplink, mtouch, pickit, picdem, picdem.net, pictail, pic 32 logo, powercal, powerinfo, powermate, powertool, real ice, rflab, select mode, total endurance, uni/o, wiperlock and zena are trademarks of microchip technology incorporated in the u.s.a. and other countries. sqtp is a service mark of microchip technology incorporated in the u.s.a. all other trademarks mentioned herein are property of their respective companies. ? 2008, microchip technology incorporated, printed in the u.s.a., all rights reserved. printed on recycled paper. note the following details of the code protection feature on microchip devices: ? microchip products meet the specification cont ained in their particular microchip data sheet. ? microchip believes that its family of products is one of the mo st secure families of its kind on the market today, when used i n the intended manner and under normal conditions. ? there are dishonest and possibly illegal methods used to breach the code protection feature. all of these methods, to our knowledge, require using the microchip produc ts in a manner outside the operating specifications contained in microchip?s data sheets. most likely, the person doing so is engaged in theft of intellectual property. ? microchip is willing to work with the customer who is concerned about the integrity of their code. ? neither microchip nor any other semiconductor manufacturer c an guarantee the security of their code. code protection does not mean that we are guaranteeing the product as ?unbreakable.? code protection is constantly evolving. we at microchip are co mmitted to continuously improvi ng the code protection features of our products. attempts to break microchip?s c ode protection feature may be a violation of the digital millennium copyright act. if such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that act. microchip received iso/ts-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona; gresham, oregon and design centers in california and india. the company?s quality system processes and procedures are for its pic ? mcus and dspic ? dscs, k ee l oq ? code hopping devices, serial eeproms, microperipherals, nonvolatile memory and analog products. in addition, microchip?s quality system for the design and manufacture of development systems is iso 9001:2000 certified.
? 2008 microchip technology inc. preliminary ds61143e-page 1 pic32mx3xx/4xx high-performance 32-bit risc cpu: ?mips32 ? m4k? 32-bit core with 5-stage pipeline ? 80 mhz maximum frequency ? 1.56 dmips/mhz (dhrystone 2.1) performance at 0 wait state flash access ? single-cycle multiply and high-performance divide unit ? mips16e? mode for up to 40% smaller code size ? user and kernel modes to enable robust embedded system ? two sets of 32 core register files (32-bit) to reduce interrupt latency ? prefetch cache module to speed execution from flash microcontroller features: ? operating voltage range of 2.3v to 3.6v ? 32k to 512k flash memory (plus an additional 12kb of boot flash) ? 8k to 32k sram memory ? pin-compatible with most pic24/dspic ? devices ? multiple power management modes ? multiple interrupt vectors with individually programmable priority ? fail-safe clock monitor mode ? configurable watchdog timer with on-chip low-power rc oscillator for reliable operation peripheral features: ? atomic set, clear and invert operation on select peripheral registers ? up to 4-channel hardware dma controller with automatic data size detection ? usb 2.0 compliant full speed device and on-the-go (otg) controller ? usb has a dedicated dma channel ? 10 mhz to 40 mhz crystal oscillator ? internal 8 mhz and 32 khz oscillators ? separate plls for cpu and usb clocks ?two i 2 c? modules ? two uart modules with: - rs-232, rs-485 and lin 1.2 support -irda ? with on-chip hardware encoder and decoder ? parallel master and slave port (pmp/psp) with 8-bit and 16-bit data and up to 16 address lines ? hardware real-time clock/calendar (rtcc) ? five 16-bit timers/counters (two 16-bit pairs com- bine to create two 32-bit timers) ? five capture inputs ? five compare/pwm outputs ? five external interrupt pins ? high-speed i/o pins capable of toggling at up to 80 mhz ? high-current sink/source (18 ma/18 ma) on all i/o pins ? configurable open-drain output on digital i/o pins debug features: ? two programming and debugging interfaces: - 2-wire interface with unintrusive access and real-time data exchange with application - 4-wire mips standard enhanced jtag interface ? unintrusive hardware-based instruction trace ? ieee std 1149.2 compatible (jtag) boundary scan analog features: ? up to 16-channel 10-bit analog-to-digital converter: - 500 ksps conversion rate - conversion available during sleep, idle ? two analog comparators ? 5.5v tolerant input pins (digital pins only) high-performance 80 mhz mips-based 32-bit flash microcontroller 64/100-pin general purpose and usb
pic32mx3xx/4xx ds61143e-page 2 preliminary ? 2008 microchip technology inc. figure 1: pic32mx package outline drawing table 2: pic32mx general purpose ? features table 3: pic32mx usb ? features tqfp 100-pin 12 x 12 mm tqfp 64-pin 10 x 10 mm general purpose device pins mhz program/ data memory (kb) timers/ capture/ compare programmable dma channels vreg trace euart/ spi/ i 2 c? 10-bit a/d (ch) comparators pmp/psp jtag pic32mx320f032h 64 40 32/8 5/5/5 0 yes no 2/2/2 16 2 yes yes pic32mx320f064h 64 80 64/16 5/5/5 0 yes no 2/2/2 16 2 yes yes pic32mx320f128h 64 80 128/16 5/5/5 0 yes no 2/2/2 16 2 yes yes pic32mx340f128h 64 80 128/32 5/5/5 4 yes no 2/2/2 16 2 yes yes pic32mx340f256h 64 80 256/32 5/5/5 4 yes no 2/2/2 16 2 yes yes pic32mx340f512h 64 80 512/32 5/5/5 4 yes no 2/2/2 16 2 yes yes pic32mx320f128l 100 80 128/16 5/5/5 0 yes no 2/2/2 16 2 yes yes pic32mx340f128l 100 80 128/32 5/5/5 4 yes no 2/2/2 16 2 yes yes pic32mx360f256l 100 80 256/32 5/5/5 4 yes yes 2/2/2 16 2 yes yes pic32mx360f512l 100 80 512/32 5/5/5 4 yes yes 2/2/2 16 2 yes yes usb device pins mhz program/data memory (kb) timers/ capture/ compare programmable dma channels dedicated usb dma channels vreg trace euart/ spi/ i 2 c? 10-bit a/d (ch) comparators pmp/psp jtag pic32mx420f032h 64 80 32/8 5/5/5 0 2 yes no 2/1/2 16 2 yes yes pic32mx440f128h 64 80 128/32 5/5/5 4 2 yes no 2/2/2 16 2 yes yes pic32mx440f256h 64 80 256/32 5/5/5 4 2 yes no 2/1/2 16 2 yes yes pic32mx440f512h 64 80 512/32 5/5/5 4 2 yes no 2/1/2 16 2 yes yes pic32mx440f128l 100 80 128/32 5/5/5 4 2 yes no 2/2/2 16 2 yes yes pic32mx460f256l 100 80 256/32 5/5/5 4 2 yes yes 2/2/2 16 2 yes yes pic32mx460f512l 100 80 512/32 5/5/5 4 2 yes yes 2/2/2 16 2 yes yes
? 2008 microchip technology inc. preliminary ds61143e-page 3 pic32mx3xx/4xx pin diagram (64-pin general purpose) 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 22 44 24 25 26 27 28 29 30 31 32 pic32mx3xxh 1 46 45 23 43 42 41 40 39 cn15/rd6 pmrd/cn14/rd5 pmwr/oc5/ic5/cn13/rd4 oc4/rd3 oc3/rd2 oc2/rd1 pmd4/re4 pmd3/re3 pmd2/re2 pmd1/re1 rf0 v cap /v ddcore sosci/cn1/rc13 oc1/rd0 ic3/pmcs2/pma15/int3/rd10 ic2/u1cts /int2/rd9 ic1/rtcc/int1/rd8 ic4/pmcs1/pma14/int4/rd11 osc2/clko/rc15 osc1/clki/rc12 v dd scl1/rg2 u1rts /bclk1/sck1/int0/rf6 u1rx/sdi1/rf2 u1tx/sdo1/rf3 sda1/rg3 sosco/t1ck/cn0/rc14 av dd u2cts /c1out/an8/rb8 pma7/c2out/an9/rb9 tms/cv refout /pma13/an10/rb10 tdo/pma12/an11/rb11 v dd pgc2/emuc2/an6/ocfa/rb6 pgd2/emud2/an7/rb7 pma8/u2tx/scl2/cn18/rf5 pma9/u2rx/sda2/cn17/rf4 pmd5/re5 pmd6/re6 pmd7/re7 pma5/sck2/cn8/rg6 v dd c1in+/an5/cn7/rb5 c1in-/an4/cn6/rb4 c2in+/an3/cn5/rb3 c2in-/an2/ss1 /cn4/rb2 pma4/sdi2/cn9/rg7 pma3/sdo2/cn10/rg8 pgc1/emuc1/an1/v ref -/cv ref -/cn3/rb1 pgd1/emud1/pma6/an0/v ref +/cv ref +/cn2/rb0 pma2/ss2 /cn11/rg9 mclr tck/pma11/an12/rb12 tdi/pma10/an13/rb13 pmalh/pma1/u2rts /bclk2/an14/rb14 pmall/pma0/an15/ocfb/cn12/rb15 pmd0/re0 rf1 cn16/rd7 v ss v ss vss envreg 63 62 61 59 60 58 57 56 54 55 53 52 51 49 50 38 37 34 36 35 33 17 19 20 21 18 av ss 64 64-pin tqfp (general purpose)
pic32mx3xx/4xx ds61143e-page 4 preliminary ? 2008 microchip technology inc. pin diagram (100-pin general purpose) 92 94 93 91 90 89 88 87 86 85 84 83 82 81 80 79 78 20 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 65 64 63 62 61 60 59 56 45 44 43 42 41 40 39 28 29 30 31 32 33 34 35 36 37 38 17 18 19 21 22 95 1 76 77 72 71 70 69 68 67 66 75 74 73 58 57 24 23 25 96 98 97 99 27 46 47 48 49 55 54 53 52 51 100 pmrd/cn14/rd5 pmwr/oc5/cn13/rd4 pmd13/cn19/rd13 pmd12/ic5/rd12 oc4/rd3 oc3/rd2 oc2/rd1 trd3/ra7 trclk/ra6 pmd2/re2 trd0/rg13 trd1/rg12 trd2/rg14 pmd1/re1 pmd0/re0 pmd8/rg0 pmd4/re4 pmd3/re3 pmd11/rf0 sosci/cn1/rc13 oc1/rd0 ic3/pmcs2/pma15/rd10 ic2/rd9 ic1/rtcc/rd8 ic4/pmcs1/pma14/rd11 int4/ra15 int3/ra14 osc2/clko/rc15 osc1/clki/rc12 v dd scl1/rg2 sck1/int0/rf6 sdi1/rf7 sdo1/rf8 sda1/rg3 u1rx/rf2 u1tx/rf3 v ss sosco/t1ck/cn0/rc14 pma6/v ref +/cv ref +/ra10 pma7/v ref -/cv ref -/ra9 av dd av ss c1out/an8/rb8 c2out/an9/rb9 cv refout /pma13/an10/rb10 pma12/an11/rb11 v dd u2cts /rf12 u2rts /bclk2/rf13 cn20/u1cts /rd14 u1rts /bclk1/cn21/rd15 v dd v ss pgc2/emuc2/an6/ocfa/rb6 pgd2/emud2/an7/rb7 pma8/u2tx/cn18/rf5 pma9/u2rx/cn17/rf4 pmd5/re5 pmd6/re6 pmd7/re7 t2ck/rc1 t3ck/rc2 t4ck/rc3 t5ck/rc4 pma5/sck2/cn8/rg6 v dd tms/ra0 int1/re8 int2/re9 c1in+/an5/cn7/rb5 c1in-/an4/cn6/rb4 c2in+/an3/cn5/rb3 c2in-/an2/ss1 /cn4/rb2 pma4/sdi2/cn9/rg7 pma3/sdo2/cn10/rg8 pgc1/emuc1/an1/cn3/rb1 pgd1/emud1/an0/cn2/rb0 v dd rg15 pma2/ss2 /cn11/rg9 mclr pma11/an12/rb12 pma10/an13/rb13 pmalh/pma1/an14/rb14 pmall/pma0/an15/ocfb/cn12/rb15 pmd9/rg1 pmd10/rf1 envreg pmd14/cn15/rd6 tdo/ra5 sda2/ra3 scl2/ra2 v ss v ss v ss v cap /v ddcore tdi/ra4 tck/ra1 100-pin tqfp (general purpose) 50 26 pmd15/cn16/rd7 pic32mx3xxl
? 2008 microchip technology inc. preliminary ds61143e-page 5 pic32mx3xx/4xx pin diagram (64-pin usb) 64-pin tqfp (usb) 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 22 44 24 25 26 27 28 29 30 31 32 pic32mx4xxh 1 46 45 23 43 42 41 40 39 cn15/rd6 pmrd/cn14/rd5 pmwr/oc5/ic5/cn13/rd4 oc4/u1tx/rd3 oc3/u1rx/rd2 oc2/u1rts /bclk1/rd1 pmd4/re4 pmd3/re3 pmd2/re2 pmd1/re1 rf0 v cap /v ddcore sosci/cn1/rc13 oc1/int0/rd0 ic3/pmcs2/pma15/int3/scl1/rd10 ic2/u1cts //int2/sda1/rd9 ic1/rtcc/int1/rd8 ic4/pmcs1/pma14/int4/rd11 osc2/clko/rc15 osc1/clki/rc12 v dd d+/rg2 vusb vbus usbid/rf3 d-/rg3 sosco/t1ck/cn0/rc14 av dd u2cts /c1out/an8/rb8 pma7/c2out/an9/rb9 tms/cv refout /pma13/an10/rb10 tdo/pma12/an11/rb11 v dd pgc2/emuc2/an6/ocfa/rb6 pgd2/emud2/an7/rb7 pma8/u2tx/scl2/cn18/rf5 pma9/u2rx/sda2/cn17/rf4 pmd5/re5 pmd6/re6 pmd7/re7 pma5/sck2/cn8/rg6 v dd vbuson/c1in+/an5/cn7/rb5 c1in-/an4/cn6/rb4 c2in+/an3/cn5/rb3 c2in-/an2/cn4/rb2 pma4/sdi2/cn9/rg7 pma3/sdo2/cn10/rg8 pgc1/emuc1/an1/v ref -/cv ref -/cn3/rb1 pgd1/emud1/pma6/an0/v ref +/cv ref +/cn2/rb0 pma2/ss2 /cn11/rg9 mclr tck/pma11/an12/rb12 tdi/pma10/an13/rb13 pmalh/pma1/u2rts /bclk2/an14/rb14 pmall/pma0/an15/ocfb/cn12/rb15 pmd0/re0 rf1 cn16/rd7 v ss v ss vss envreg 63 62 61 59 60 58 57 56 54 55 53 52 51 49 50 38 37 34 36 35 33 17 19 20 21 18 av ss 64
pic32mx3xx/4xx ds61143e-page 6 preliminary ? 2008 microchip technology inc. pin diagram (100-pin usb) 92 94 93 91 90 89 88 87 86 85 84 83 82 81 80 79 78 20 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 65 64 63 62 61 60 59 56 45 44 43 42 41 40 39 28 29 30 31 32 33 34 35 36 37 38 17 18 19 21 22 95 1 76 77 72 71 70 69 68 67 66 75 74 73 58 57 24 23 25 96 98 97 99 27 46 47 48 49 55 54 53 52 51 100 pmrd/cn14/rd5 pmwr/oc5/cn13/rd4 pmd13/cn19/rd13 pmd12/ic5/rd12 oc4/rd3 oc3/rd2 oc2/rd1 trd3/ra7 trclk/ra6 pmd2/re2 trd0/rg13 trd1/rg12 trd2/rg14 pmd1/re1 pmd0/re0 pmd8/rg0 pmd4/re4 pmd3/re3 pmd11/rf0 sosci/cn1/rc13 sdo1/oc1/int0/rd0 ic3/scki/pmcs2/pma15/rd10 ic2/ss1 /rd9 ic1/rtcc/rd8 ic4/pmcs1/pma14/rd11 sda1/int4/ra15 scl1/int3/ra14 osc2/clko/rc15 osc1/clki/rc12 v dd d+/rg2 vusb vbus u1tx/rf8 d-/rg3 u1rx/rf2 usbid/rf3 v ss sosco/t1ck/cn0/rc14 pma6/v ref +/cv ref +/ra10 pma7/v ref -/cv ref -/ra9 av dd av ss c1out/an8/rb8 c2out/an9/rb9 cv refout /pma13/an10/rb10 pma12/an11/rb11 v dd u2cts /rf12 u2rts /bclk2/rf13 cn20/u1cts /rd14 u1rts /bclk1/cn21/rd15 v dd v ss pgc2/emuc2/an6/ocfa/rb6 pgd2/emud2/an7/rb7 pma8/u2tx/cn18/rf5 pma9/u2rx/cn17/rf4 pmd5/re5 pmd6/re6 pmd7/re7 t2ck/rc1 t3ck/rc2 t4ck/rc3 sdi1/t5ck/rc4 pma5/sck2/cn8/rg6 v dd tms/ra0 int1/re8 int2/re9 vbuson/c1in+/an5/cn7/rb5 c1in-/an4/cn6/rb4 c2in+/an3/cn5/rb3 c2in-/an2/cn4/rb2 pma4/sdi2/cn9/rg7 pma3/sdo2/cn10/rg8 pgc1/emuc1/an1/cn3/rb1 pgd1/emud1/an0/cn2/rb0 v dd rg15 pma2/ss2 /cn11/rg9 mclr pma11/an12/rb12 pma10/an13/rb13 pmalh/pma1/an14/rb14 pmall/pma0/an15/ocfb/cn12/rb15 pmd9/rg1 pmd10/rf1 envreg pmd14/cn15/rd6 tdo/ra5 sda2/ra3 scl2/ra2 v ss v ss v ss v cap /v ddcore tdi/ra4 tck/ra1 100-pin tqfp (usb) 50 26 pmd15/cn16/rd7 pic32mx4xxl
? 2008 microchip technology inc. preliminary ds61143e-page 7 pic32mx3xx/4xx table of contents high-performance 80 mhz mips-based 32-bit flash microcontroller 64 /100-pin general purpose and usb ............................. ........ 1 1.0 device overview ............................................................................................................. ............................................................. 9 2.0 pic32mx mcu................................................................................................................. .......................................................... 33 3.0 instruction set ............................................................................................................. ............................................................... 47 4.0 oscillators................................................................................................................. .................................................................. 53 5.0 resets ...................................................................................................................... .................................................................. 83 6.0 memory organization ......................................................................................................... ........................................................ 93 7.0 flash program memory........................................................................................................ .................................................... 115 8.0 interrupts .................................................................................................................. ................................................................ 125 9.0 prefetch cache.............................................................................................................. ........................................................... 177 10.0 direct memory access (dma) controller ...................................................................................... ........................................... 197 11.0 usb on-the-go.............................................................................................................. ......................................................... 241 12.0 i/o ports .................................................................................................................. ................................................................. 305 13.0 timer1 ..................................................................................................................... ................................................................. 327 14.0 timers 2, 3, 4, 5 .......................................................................................................... ............................................................. 339 15.0 input capture.............................................................................................................. .............................................................. 355 16.0 output compare............................................................................................................. .......................................................... 365 17.0 serial peripheral interface (spi).......................................................................................... ..................................................... 383 18.0 inter-integrated circuit (i 2 c?) ............................................................................................................................ ..................... 409 19.0 universal asynchronous receiver transmitter (uart) ......................................................................... .................................. 425 20.0 parallel master port....................................................................................................... ........................................................... 439 21.0 real-time clock and calendar (rtcc)........................................................................................ ........................................... 467 22.0 analog-digital converter ................................................................................................... ....................................................... 489 23.0 power saving ............................................................................................................... ............................................................ 521 24.0 comparator ................................................................................................................. ............................................................. 537 25.0 comparator reference....................................................................................................... ...................................................... 549 26.0 watchdog timer ............................................................................................................. .......................................................... 555 27.0 special features ........................................................................................................... ........................................................... 565 28.0 programming and diagnostics ................................................................................................ ................................................. 577 29.0 development support........................................................................................................ ....................................................... 589 30.0 electrical characteristics ................................................................................................. ......................................................... 593 31.0 packaging information...................................................................................................... ........................................................ 631 index .......................................................................................................................... ........................................................................ 641 worldwide sales and service .................................................................................................... ........................................................ 644
pic32mx3xx/4xx ds61143e-page 8 preliminary ? 2008 microchip technology inc. to our valued customers it is our intention to provide our valued customers with the be st documentation possible to ensure successful use of your micro chip products. to this end, we will continue to improve our publications to better suit your needs. our publications will be refined and enhanced as new volumes and updates are introduced. if you have any questions or comments regardi ng this publication, please contact the marketing communications department via e-mail at docerrors@microchip.com or fax the reader response form in the back of this data sheet to (480) 792-4150. we welcome your feedback. most current data sheet to obtain the most up-to-date version of this data s heet, please register at our worldwide web site at: http://www.microchip.com you can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page . the last character of the literature number is the vers ion number, (e.g., ds30000a is version a of document ds30000). errata an errata sheet, describing minor operational differences fr om the data sheet and recommended workarounds, may exist for curren t devices. as device/documentation issues become known to us, we will publish an errata sheet. the errata will specify the revisi on of silicon and revision of document to which it applies. to determine if an errata sheet exists for a particular device, please check with one of the following: ? microchip?s worldwide web site; http://www.microchip.com ? your local microchip sales office (see last page) when contacting a sales office, please specify which device, re vision of silicon and data sheet (include literature number) you are using. customer notification system register on our web site at www.microchip.com to receive the most current information on all of our products.
? 2008 microchip technology inc. preliminary ds61143e-page 9 pic32mx3xx/4xx 1.0 device overview this document contains device specific information for the following devices: ? pic32mx320f032h ? pic32mx320f064h ? pic32mx320f128h ? pic32mx320f128l ? pic32mx340f128h ? pic32mx340f128l ? pic32mx340f256h ? pic32mx340f512h ? pic32mx360f256l ? pic32mx360f512l ? pic32mx420f032h ? pic32mx440f256h ? pic32mx440f128h ? pic32mx440f128l ? pic32mx440f512h ? pic32mx460f256l ? pic32mx460f512l this family introduces a new line of microchip devices: a 32-bit risc microcontroller family with a broad peripheral feature set and enhanced computational performance. the pic32mx3xx/4xx family offers a new migration option for those high-performance appli- cations which may be outgrowing their 16-bit platforms. 1.1 easy migration the pic32mx family of microcontrollers was designed to provide an easy migration path as the application needs change. the consistent pinout scheme used throughout the entire family aids in migrating to the next larger device. this is true when moving between devices with the same pin count, or even jumping from 64-pin to 100-pin devices. the pic32mx family is pin and peripheral compatible with microchip pic24fj128ga010 devices. 1.2 core features 1.2.1 32-bit risc architecture central to all pic32mx3xx/4xx devices is the 32-bit mips32 m4k cpu core, offering a wide range of features, including the following: ? up to 1.56 dmips/mhz ? 32-bit address and data paths ? 32-bit linear (program space) addressing ? (2) thirty-two element 32-bit core register files ? single-cycle multiply and high-performance divide unit for 32-bit integer math ? 16 and 32-bit instructions, optimized for high-level languages, such as ?c?. 1.3 power-saving technology all of the devices in the pic32mx family incorporate a range of features that can significantly reduce power consumption during operation. key features include: ? on-the-fly clock switching: the device clock can be changed under software control to any of the four clock sources during operation. ? instruction-based power-saving modes: the microcontroller can suspend all operations, or selectively shut down its core while leaving its peripherals active, with a single instruction in software. 1.4 communications the pic32mx incorporates a range of serial communi- cation peripherals to handle a range of application requirements. all devices are equipped with two inde- pendent uarts with built-in irda encoder/decoders. there are also two independent spi modules, and two independent i 2 c modules that support both master and slave modes of operation. 1.5 10-bit a/d converter the a/d converter features 500 ksps maximum sample rate. this configurable module incorporates a user- selectable scan list and auto-convert functions to allow acquisitions without processor intervention. multiple a/d trigger sources are user-selectable: timer event, external pin, manual and auto-convert. 64/100-pin general purpose and usb, 32-bit flash mi crocontrollers
pic32mx3xx/4xx ds61143e-page 10 preliminary ? 2008 microchip technology inc. 1.6 external interface a parallel master port parallel slave port enables 8/16- bit parallel data communications in master mode with up to 16 address lines; 8-bit slave modes are also supported. 1.7 real-time clock/calendar this module implements a full-featured clock and calendar with alarm functions in hardware, freeing up timer resources and program memory space for use of the core application. 1.8 oscillator options and features all of the devices in the pic32mx family offer four different oscillator options, allowing users a range of choices in developing application hardware. these include: ? a primary oscillator (posc) with two external crystal modes using crystals or ceramic resonators. ? two external clock modes with selectable peripheral bus clock output. ? a fast internal oscillator (frc) with a nominal 8 mhz output. ? on-board postscalers and/or pll to provide clock speeds ranging from 31 khz to maximum specified frequency. ? a secondary oscillator (sosc) designed to operate with an external 32.768 khz crystal. this oscillator can also be used with timer1 and the integrated rtcc. ? an internal low-power rc oscillator (lprc) having a fixed 31 khz output, which provides a low-power option for timing-insensitive applications. the oscillator block also provides a stable reference source for the user-controlled fail-safe clock monitor. this option constantly monitors the main clock source against a reference signal provided by the internal oscillator and enables the controller to switch to the internal oscillator, allowing for continued low-speed operation or a safe application shutdown.
? 2008 microchip technology inc. preliminary ds61143e-page 11 pic32mx3xx/4xx 1.9 device features, block diagrams and pinout tables table 1-1: device features, bl ock diagrams and pinout tables features pic32mx320f032h pic32mx320f064h pic32mx320f128h pic32mx340f256h pic32mx320f128l pic32mx360f256l pic32mx360f512l operating frequency dc ? 40 mhz dc ? 80 mhz program memory (bytes) 32k 64k 128k 256k 128k 256k 512k data memory (bytes) 8k 16k 16k 32k 16k 32k 32k interrupt sources/vectors 95 / 63 i/o ports ports b, c, d, e, f, g ports a, b, c, d, e, f, g total i/o pins 53 85 dma channels 0 4 0 4 timers: total number (16-bit) 5 32-bit (paired 16-bit) 2 32-bit core timer 1 input capture channels 5 output compare/pwm channels 5 input change interrupt notification 19 22 serial communications: enhanced uart 2 spi (3-wire/4-wire) 2 i 2 c? 2 parallel communications (pmp/psp) yes, 8-bit only yes, 8-bit/16-bit jtag boundary scan yes jtag debug and program yes icsp? 2-wire debug and program yes instruction trace no yes hardware break points 6 instruction, 2 data 10-bit analog-to-digital module (input channels) 16 analog comparators 2 internal ldo yes resets (and delays) por, bor, mclr , wdt, swr (software reset), cm (configuration bit mismatch) ( p w r t, o s t, p l l l o c k ) instruction support mips32 ? enhanced architecture (release 2) mips16e? code compression packages 64-pin tqfp 100-pin tqfp
pic32mx3xx/4xx ds61143e-page 12 preliminary ? 2008 microchip technology inc. table 1-2: device features for the pi c32mx3xxfxxx general purpose family features pic32mx340f128h pic32mx340f512h pic32mx340f128l operating frequency dc ? 80 mhz program memory (bytes) 128k 512k 128k data memory (bytes) 32k 32k 32k interrupt sources/vectors 95 / 63 i/o ports ports b, c, d, e, f, g ports a, b, c, d, e, f, g total i/o pins 53 85 dma channels 4 timers: total number (16-bit) 5 32-bit (paired 16-bit) 2 32-bit core timer 1 input capture channels 5 output compare/pwm channels 5 input change interrupt notification 19 22 serial communications: enhanced uart 2 spi (3-wire/4-wire) 2 i 2 c? 2 parallel communications (pmp/psp) yes, 8-bit only yes, 8-bit/16-bit jtag boundary scan yes jtag debug and program yes icsp? 2-wire debug and program yes instruction trace no hardware break points 6 instruction, 2 data 10-bit analog-to-digital module (input channels) 16 analog comparators 2 internal ldo yes resets (and delays) por, bor, mclr , wdt, swr (software reset), cm (configuration bit mismatch) ( p w r t, o s t, p l l l o c k ) instruction support mips32 ? enhanced architecture (release 2) mips16e? code compression packages 64-pin tqfp 100-pin tqfp
? 2008 microchip technology inc. preliminary ds61143e-page 13 pic32mx3xx/4xx table 1-3: device features for the pic32mx4xxfxxx usb family features pic32mx420f032h pic32mx440f128h pic32mx440f256h pic32mx440f512h pic32mx440f128l pic32mx460f256l pic32mx460f512l operating frequency dc ? 40 mhz dc ? 80 mhz program memory (bytes) 32k 128k 256k 512k 128k 256k 512k data memory (bytes) 8k 32k 32k 32k 32k 32k 32k interrupt sources / vectors 95 / 63 i/o ports ports b, c, d, e, f, g ports a, b, c, d, e, f, g to t a l i / o p i n s 5 1 8 3 dma channels 0 + 2 usb 4 + 2 usb timers: total number (16-bit) 5 32-bit (from paired 16-bit timers) 2 32-bit core timer 1 input capture channels 5 output compare/pwm channels 5 input change interrupt notification 19 22 serial communications: enhanced uart 2 spi (3-wire/4-wire) 1 2 i 2 c? 2 parallel communications (pmp/psp) yes, 8-bit only yes, 8-bit/16-bit jtag boundary scan yes jtag debug and program yes icsp 2-wire debug and program yes instruction trace no yes hardware break points: 6 instruction, 2 data 10-bit analog-to-digital module (input channels) 16 analog comparators 2 internal ldo yes resets (and delays) por, bor, mclr , wdt, swr (software reset), cm (configuration bit mismatch) ( p w r t, o s t, p l l l o c k ) instruction support mips32 enhanced architecture (release 2) mips16e? code compression packages 64-pin tqfp 100-pin tqfp
pic32mx3xx/4xx ds61143e-page 14 preliminary ? 2008 microchip technology inc. figure 1-1: pic32mx3 xx block diagram (g eneral purpose) uart1,2 comparators timer2 rtcc 10-bit adc timer3 porta (1,4) portd (1) porte (1) portf (1) portg (1) portb note 1: not all pins or features are implemented on all device pinout configurations. see table 1-4 for i/o port pin descriptions. 2: some features are not available on certain devices. 3: bor functionality is provided when the on-board voltage regulator is enabled. 4: porta is not present on 64-pin devices cn1-22 (1) jtag dmac (2) icd mips32 ? m4k? cpu core is ds ejtag int bus matrix prefetch data ram peripheral bridge 128 128-bit wide flash 32 32 32 32 32 32 peripheral bus clocked by pbclk program flash memory timer5 timer4 controller 32 32 module (2) 32 32 interrupt controller bscan portc (1) pmp (1) i2c1,2 spi1,2 (1) ic1-5 pwm oc1-5 timer1 osc1/clki osc2/clko v dd , timing generation v ss mclr power-up timer oscillator start-up timer power-on reset watchdog timer brown-out reset (3) precision reference band gap frc/lprc oscillators regulator voltage v ddcore /v cap envreg osc/sosc oscillators pll dividers sysclk pbclk peripheral bus clocked by pbclk peripheral bus clocked by sysclk
? 2008 microchip technology inc. preliminary ds61143e-page 15 pic32mx3xx/4xx figure 1-2: pic32mx4xx block diagram (usb) note 1: not all pins or features are implemented on all device pinout configurations. see table 1-5 for i/o port pin descriptions. 2: some features are not available on certain device variants. 3: bor functionality is provided when t he on-board voltage regulator is enabled. 4: porta is not present on 64 pin devices uart 1,2 comparators timer2 rtcc 10-bit adc timer3 porta (1,4) portd (1) porte (1) portf (1) portg (1) portb cn1-22 (1) jtag priority dmac (1) icd mips m4k cpu core is ds ejtag int bus matrix pre-fetch data ram peripheral bridge 128 128-bit wide flash 32 32 32 32 32 32 peripheral bus clocked by pbclk program flash memory timer5 timer4 controller 32 32 module (1) 32 32 interrupt controller bscan portc (1) pmp (1) i2c 1,2 spi 1,2 (1) ic 1,5 pwm oc 1,5 timer1 osc1/clki osc2/clko v dd , timing generation v ss mclr power-up timer oscillator start-up timer power-on reset watchdog timer brown-out reset (2) precision reference band gap frc/lprc oscillators regulator voltage (1) v ddcore /v cap envreg osc/sosc oscillators pll dividers sysclk pbclk peripheral bus clocked by pbclk peripheral bus clocked by sysclk usb pll-usb usbclk 32
pic32mx3xx/4xx ds61143e-page 16 preliminary ? 2008 microchip technology inc. table 1-4: pic32mx3xx/4xx pinout descriptions ? general purpose function pin number i/o input buffer description 64-pin 100-pin an0 16 25 i ana a/d analog inputs an1 15 24 i ana an2 14 23 i ana an3 13 22 i ana an4 12 21 i ana an5 11 20 i ana an6 17 26 i ana an7 18 27 i ana an8 21 32 i ana an9 22 33 i ana an10 23 34 i ana an11 24 35 i ana an12 27 41 i ana an13 28 42 i ana an14 29 43 i ana an15 30 44 i ana av dd 19 30 p ? positive supply for analog modules av ss 20 31 p ? ground reference for analog modules bclk1 35 48 o ? uart1 irda ? baud clock bclk2 29 39 o ? uart2 irda baud clock c1in- 12 21 i ana comparator 1 negative input c1in+ 11 20 i ana comparator 1 positive input c1out 21 32 o ? comparator 1 output c2in- 14 23 i ana comparator 2 negative input c2in+ 13 22 i ana comparator 2 positive input c2out 22 33 o ? comparator 2 output clki 39 63 i ana main clock input connection clko 40 64 o ? system clock output legend: ttl = ttl input buffer st = schmitt trigger input buffer ana = analog level input/output i 2 c? = i 2 c/smbus input buffer note: in some cases, i/o pins are multiplexed with more than one peripheral. in general, the dominant output control of a multiplexed i/o pin can be determined by the order of the peripheral output names assigned to a pin (read from left to right). multiplexed peripheral inputs have no priority.
? 2008 microchip technology inc. preliminary ds61143e-page 17 pic32mx3xx/4xx cn0 48 74 i st interrupt-on-change inputs cn1 47 73 i st cn2 16 25 i st cn3 15 24 i st cn4 14 23 i st cn5 13 22 i st cn6 12 21 i st cn7 11 20 i st cn8 4 10 i st cn9 5 11 i st cn10 6 12 i st cn11 8 14 i st cn12 30 44 i st cn13 52 81 i st cn14 53 82 i st cn15 54 83 i st cn16 55 84 i st cn17 31 49 i st cn18 32 50 i st interrupt-on-change inputs cn19 ? 80 i st cn20 ? 47 i st cn21 ? 48 i st cv ref - 15 28 i ana comparator reference voltage (low) input cv ref + 16 29 i ana comparator reference voltage (high) input cv refout 23 34 o ana comparator voltage reference output emuc1 15 24 i/o st in-circuit emulator clock input/output emud1 16 25 i/o st in-circuit emulator data input/output emuc2 17 26 i/o st in-circuit emulator clock input/output emud2 18 27 i/o st in-circuit emulator data input/output envreg 57 86 i st enable for on-chip voltage regulator ic1 42 68 i st input capture inputs ic2 43 69 i st ic3 44 70 i st ic4 45 71 i st ic5 52 79 i st int0 35 55 i st external interrupt inputs int1 42 18 i st int2 43 19 i st int3 44 66 i st int4 45 67 i st mclr 7 13 i st master clear (device reset) input. bring this line low to cause a reset. table 1-4: pic32mx3xx/4xx pinout descri ptions ? general purpose (continued) function pin number i/o input buffer description 64-pin 100-pin legend: ttl = ttl input buffer st = schmitt trigger input buffer ana = analog level input/output i 2 c? = i 2 c/smbus input buffer note: in some cases, i/o pins are multiplexed with more than one peripheral. in general, the dominant output control of a multiplexed i/o pin can be determined by the order of the per ipheral output names assigned to a pin (read from left to right). multiplexed peripheral inputs have no priority.
pic32mx3xx/4xx ds61143e-page 18 preliminary ? 2008 microchip technology inc. oc1 46 72 o ? output compare/pwm outputs oc2 49 76 o ? oc3 50 77 o ? oc4 51 78 o ? oc5 52 81 o ? ocfa 17 26 i st output compare fault a input ocfb 30 44 i st output compare fault b input osc1 39 63 i ana main oscillator input connection osc2 40 64 o ana main oscillator output connection. pgc1 15 24 i/o st in-circuit debugger and icsp? programming clock pgd1 16 25 i/o st in-circuit debugger and icsp programming data pgc2 17 26 i/o st in-circuit debugger and icsp? programming clock pgd2 18 27 i/o st in-circuit debugger and icsp programming data pmall 30 44 o? parallel master port address latch enable low-byte (multiplexed master modes) pmalh 29 43 o ? parallel master port address latch enable high-byte (multiplexed master modes) pma0 30 44 o? parallel master port address bit 0 input (buffered slave modes) and output (master modes) pma1 29 43 o ? parallel master port address bit 1 input (buffered slave modes) and output (master modes) pma2 8 14 o ? parallel master port address (demultiplexed master modes) pma3 6 12 o ? pma4 5 11 o ? pma5 4 10 o ? pma6 16 29 o ? pma7 22 28 o ? pma8 32 50 o ? pma9 31 49 o ? pma10 28 42 o ? pma11 27 41 o ? pma12 24 35 o ? pma13 23 34 o ? pma14 45 71 o ? pma15 44 70 o ? pmcs1 45 71 o ? parallel master port chip select 1 strobe pmcs2 44 70 o ? parallel master port chip select 2 strobe table 1-4: pic32mx3xx/4xx pinout desc riptions ? general purpose (continued) function pin number i/o input buffer description 64-pin 100-pin legend: ttl = ttl input buffer st = schmitt trigger input buffer ana = analog level input/output i 2 c? = i 2 c/smbus input buffer note: in some cases, i/o pins are multiplexed with more than one peripheral. in general, the dominant output control of a multiplexed i/o pin can be determined by the order of the peripheral output names assigned to a pin (read from left to right). multiplexed peripheral inputs have no priority.
? 2008 microchip technology inc. preliminary ds61143e-page 19 pic32mx3xx/4xx pmd0 60 93 i/o st/ttl parallel master port data (demultiplexed master mode) or address/data (multiplexed master modes) pmd1 61 94 i/o st/ttl pmd2 62 98 i/o st/ttl pmd3 63 99 i/o st/ttl pmd4 64 100 i/o st/ttl pmd5 1 3 i/o st/ttl pmd6 2 4 i/o st/ttl pmd7 3 5 i/o st/ttl pmd8 ? 90 i/o st/ttl pmd9 ? 89 i/o st/ttl pmd10 ? 88 i/o st/ttl pmd11 ? 87 i/o st/ttl pmd12 ? 79 i/o st/ttl pmd13 ? 80 i/o st/ttl pmd14 ? 83 i/o st/ttl pmd15 ? 84 i/o st/ttl pmenb 52 81 o ? parallel master port enable strobe (master mode 1) pmrd 53 82 o ? parallel master port read strobe (master mode 2) pmrd/pmwr 53 82 o ? parallel master port read/write strobe (master mode 1) pmwr 52 81 o ? parallel master port write strobe (master mode 2) table 1-4: pic32mx3xx/4xx pinout descri ptions ? general purpose (continued) function pin number i/o input buffer description 64-pin 100-pin legend: ttl = ttl input buffer st = schmitt trigger input buffer ana = analog level input/output i 2 c? = i 2 c/smbus input buffer note: in some cases, i/o pins are multiplexed with more than one peripheral. in general, the dominant output control of a multiplexed i/o pin can be determined by the order of the per ipheral output names assigned to a pin (read from left to right). multiplexed peripheral inputs have no priority.
pic32mx3xx/4xx ds61143e-page 20 preliminary ? 2008 microchip technology inc. ra0 ? 17 i/o st porta digital i/o notes: on 100-pin devices, jtag program/debug port is multi- plexed with port pins ra0, ra1, ra4 and ra5. at reset, these pins are controlled by the jtag port. to use these pins for general purpose i/o, the user?s application code must clear jtagen (ddpcon<3>) bit = 0 . to use these pins for jtag program/debug, the user?s application code must maintain jtagen bit = 1 . on specific 100-pin devices, the instruction trace port is multiplexed with porta pins ra6, ra7; portg pins rg12, rg13 and rg14. at power-on reset, these pins are general purpose i/o pins. to maintain these pins as general purpose i/o pins, the user?s application code must maintain troen (ddpcon<2>) bit = 0 . to use these pins as instruction trace pins, troen must be set = 1 . ra1 ? 38 i/o st ra2 ? 58 i/o st ra3 ? 59 i/o st ra4 ? 60 i/o st ra5 ? 61 i/o st ra6 ? 91 i/o st ra7 ? 92 i/o st ra9 ? 28 i/o st ra10 ? 29 i/o st ra14 ? 66 i/o st ra15 ? 67 i/o st rb0 16 25 i/o st portb digital i/o note: on 64-pin devices, jtag pr ogram/debug port is multi- plexed with port pins rb 10, rb11, rb12 and rb13. at reset, these pins are controll ed by the jtag port. to use these pins for general purpose i/o, the user?s application code must clear jtagen (ddpcon<3>) bit = 0 . to use these pins for jtag program/debug, the user?s application code must maintain jtagen bit = 1 . rb1 15 24 i/o st rb2 14 23 i/o st rb3 13 22 i/o st rb4 12 21 i/o st rb5 11 20 i/o st rb6 17 26 i/o st rb7 18 27 i/o st rb8 21 32 i/o st rb9 22 33 i/o st rb10 23 34 i/o st rb11 24 35 i/o st rb12 27 41 i/o st rb13 28 42 i/o st rb14 29 43 i/o st rb15 30 44 i/o st rc1 ? 6 i/o st portc digital i/o rc2 ? 7 i/o st rc3 ? 8 i/o st rc4 ? 9 i/o st rc12 39 63 i/o st rc13 47 73 i/o st rc14 48 74 i/o st rc15 40 64 i/o st table 1-4: pic32mx3xx/4xx pinout desc riptions ? general purpose (continued) function pin number i/o input buffer description 64-pin 100-pin legend: ttl = ttl input buffer st = schmitt trigger input buffer ana = analog level input/output i 2 c? = i 2 c/smbus input buffer note: in some cases, i/o pins are multiplexed with more than one peripheral. in general, the dominant output control of a multiplexed i/o pin can be determined by the order of the peripheral output names assigned to a pin (read from left to right). multiplexed peripheral inputs have no priority.
? 2008 microchip technology inc. preliminary ds61143e-page 21 pic32mx3xx/4xx rd0 46 72 i/o st portd digital i/o rd1 49 76 i/o st rd2 50 77 i/o st rd3 51 78 i/o st rd4 52 81 i/o st rd5 53 82 i/o st rd6 54 83 i/o st rd7 55 84 i/o st rd8 42 68 i/o st rd9 43 69 i/o st rd10 44 70 i/o st rd11 45 71 i/o st rd12 ? 79 i/o st rd13 ? 80 i/o st rd14 ? 47 i/o st rd15 ? 48 i/o st re0 60 93 i/o st porte digital i/o re1 61 94 i/o st re2 62 98 i/o st re3 63 99 i/o st re4 64 100 i/o st re5 1 3 i/o st re6 2 4 i/o st re7 3 5 i/o st re8 ? 18 i/o st re9 ? 19 i/o st rf0 58 87 i/o st portf digital i/o rf1 59 88 i/o st rf2 34 52 i/o st rf3 33 51 i/o st rf4 31 49 i/o st rf5 32 50 i/o st rf6 35 55 i/o st rf7 ? 54 i/o st rf8 ? 53 i/o st rf12 ? 40 i/o st rf13 ? 39 i/o st table 1-4: pic32mx3xx/4xx pinout descri ptions ? general purpose (continued) function pin number i/o input buffer description 64-pin 100-pin legend: ttl = ttl input buffer st = schmitt trigger input buffer ana = analog level input/output i 2 c? = i 2 c/smbus input buffer note: in some cases, i/o pins are multiplexed with more than one peripheral. in general, the dominant output control of a multiplexed i/o pin can be determined by the order of the per ipheral output names assigned to a pin (read from left to right). multiplexed peripheral inputs have no priority.
pic32mx3xx/4xx ds61143e-page 22 preliminary ? 2008 microchip technology inc. rg0 ? 90 i/o st portg digital i/o note: on specific 100-pin devices, the instruction trace port is multiplexed with porta pins ra6, ra7; portg pins rg12, rg13, and rg14. at power-on-reset, these pins are general purpose i/o pins. to maintain these pins as general purpose i/o pins, the user?s application code must maintain troen (ddpcon<2>) bit = 0 . to use these pins as instruction trace pins, troen must be set = 1 . rg1 ? 89 i/o st rg2 37 57 i/o st rg3 36 56 i/o st rg6 4 10 i/o st rg7 5 11 i/o st rg8 6 12 i/o st rg9 8 14 i/o st rg12 ? 96 i/o st rg13 ? 97 i/o st rg14 ? 95 i/o st rg15 ? 1 i/o st rtcc 42 68 o ? real-time clock alarm output sck1 35 55 o ? spi1 serial clock output sck2 4 10 i/o st spi2 serial clock output scl1 37 57 i/o i 2 c i2c1 synchronous serial clock input/output scl2 32 58 i/o i 2 c i2c2 synchronous serial clock input/output. sda1 36 56 i/o i 2 c i2c1 data input/output sda2 31 59 i/o i 2 c i2c2 data input/output sdi1 34 54 i st spi1 serial data input sdi2 5 11 i st spi2 serial data input sdo1 33 53 o ? spi1 serial data output sdo2 6 12 o ? spi2 serial data output sosci 47 73 i ana secondary oscillator/timer1 external clock input sosco 48 74 o ana secondary oscillator/timer1 external clock output ss1 14 23 i/o st slave select input/frame select output (spi1) ss2 8 14 i/o st slave select input/frame select output (spi2) t1ck 48 74 i st timer1 external clock input t2ck ? 6 i st timer2 external clock input t3ck ? 7 i st timer3 external clock input t4ck ? 8 i st timer4 external clock input t5ck ? 9 i st timer5 external clock input tck 27 38 i st jtag test clock/programming clock input tdi 28 60 i st jtag test data/programming data input tdo 24 61 o ? jtag test data output tms 23 17 i st jtag test mode select input trclk ? 91 o ? trace clock trd0 ? 97 o ? trace data bit 0 trd1 ? 96 o ? trace data bit 1 trd2 ? 95 o ? trace data bit 2 trd3 ? 92 o ? trace data bit 3 table 1-4: pic32mx3xx/4xx pinout desc riptions ? general purpose (continued) function pin number i/o input buffer description 64-pin 100-pin legend: ttl = ttl input buffer st = schmitt trigger input buffer ana = analog level input/output i 2 c? = i 2 c/smbus input buffer note: in some cases, i/o pins are multiplexed with more than one peripheral. in general, the dominant output control of a multiplexed i/o pin can be determined by the order of the peripheral output names assigned to a pin (read from left to right). multiplexed peripheral inputs have no priority.
? 2008 microchip technology inc. preliminary ds61143e-page 23 pic32mx3xx/4xx u1cts 43 47 i st uart1 clear to send input u1rts 35 48 o ? uart1 request to send output u1rx 34 52 i st uart1 receive u1tx 33 51 o ? uart1 transmit output u2cts 21 40 i st uart2 clear to send input u2rts 29 39 o ? uart2 request to send output u2rx 31 49 i st uart 2 receive input u2tx 32 50 o ? uart2 transmit output v dd 10, 26, 38 2, 16, 37, 46, 62 p ? positive supply for peripheral digital logic and i/o pins v ddcap 56 85 p ? external filter capacitor connection (regulator enabled) v ddcore 56 85 p ? positive supply for microcontroller core logic (regulator disabled) v ref - 15 28 i ana a/d reference voltage (low) input v ref + 16 29 i ana a/d reference voltage (high) input v ss 9, 25, 41 15, 36, 45, 65, 75 p ? ground reference for logic and i/o pins table 1-4: pic32mx3xx/4xx pinout descri ptions ? general purpose (continued) function pin number i/o input buffer description 64-pin 100-pin legend: ttl = ttl input buffer st = schmitt trigger input buffer ana = analog level input/output i 2 c? = i 2 c/smbus input buffer note: in some cases, i/o pins are multiplexed with more than one peripheral. in general, the dominant output control of a multiplexed i/o pin can be determined by the order of the per ipheral output names assigned to a pin (read from left to right). multiplexed peripheral inputs have no priority.
pic32mx3xx/4xx ds61143e-page 24 preliminary ? 2008 microchip technology inc. table 1-5: pic32mx3xx/4xx pi nout descriptions ? usb function pin number i/o input buffer description 64-pin 100-pin an0 16 25 i ana a/d analog inputs an1 15 24 i ana an2 14 23 i ana an3 13 22 i ana an4 12 21 i ana an5 11 20 i ana an6 17 26 i ana an7 18 27 i ana an8 21 32 i ana an9 22 33 i ana an10 23 34 i ana an11 24 35 i ana an12 27 41 i ana an13 28 42 i ana an14 29 43 i ana an15 30 44 i ana av dd 19 30 p ? positive supply for analog modules av ss 20 31 p ? ground reference for analog modules bclk1 49 48 o ? uart1 irda ? baud clock bclk2 29 39 o ? uart2 irda ? baud clock c1in- 12 21 i ana comparator 1 negative input c1in+ 11 20 i ana comparator 1 positive input c1out 21 32 o ? comparator 1 output c2in- 14 23 i ana comparator 2 negative input c2in+ 13 22 i ana comparator 2 positive input c2out 22 33 o ? comparator 2 output clki 39 63 i ana main clock input connection clko 40 64 o ? system clock output legend: ttl = ttl input buffer st = schmitt trigger input buffer ana = analog level input/output i 2 c? = i 2 c/smbus input buffer note: in some cases, i/o pins are multiplexed with more than one peripheral. in general, the dominant output control of a multiplexed i/o pin can be determined by the order of the peripheral output names assigned to a pin (read from left to right). multiplexed peripheral inputs have no priority.
? 2008 microchip technology inc. preliminary ds61143e-page 25 pic32mx3xx/4xx cn0 48 74 i st interrupt-on-change inputs cn1 47 73 i st cn2 16 25 i st cn3 15 24 i st cn4 14 23 i st cn5 13 22 i st cn6 12 21 i st cn7 11 20 i st cn8 4 10 i st cn9 5 11 i st cn10 6 12 i st cn11 8 14 i st cn12 30 44 i st cn13 52 81 i st cn14 53 82 i st cn15 54 83 i st cn16 55 84 i st cn17 31 49 i st cn18 32 50 i st interrupt-on-change inputs cn19 ? 80 i st cn20 ? 47 i st cn21 ? 48 i st cv ref - 15 28 i ana comparator reference voltage (low) input cv ref + 16 29 i ana comparator reference voltage (high) input cv refout 23 34 o ana comparator voltage reference output d+ 37 57 i/o ana usb d+ d- 36 56 i/o ana usb d- emuc1 15 24 i/o st in-circuit emulator clock input/output emud1 16 25 i/o st in-circuit emulator data input/output emuc2 17 26 i/o st in-circuit emulator clock input/output emud2 18 27 i/o st in-circuit emulator data input/output envreg 57 86 i st enable for on-chip voltage regulator ic1 42 68 i st input capture inputs ic2 43 69 i st ic3 44 70 i st ic4 45 71 i st ic5 52 79 i st table 1-5: pic32mx3xx/4xx pinout descriptions ? usb (continued) function pin number i/o input buffer description 64-pin 100-pin legend: ttl = ttl input buffer st = schmitt trigger input buffer ana = analog level input/output i 2 c? = i 2 c/smbus input buffer note: in some cases, i/o pins are multiplexed with more than one peripheral. in general, the dominant output control of a multiplexed i/o pin can be determined by the order of the per ipheral output names assigned to a pin (read from left to right). multiplexed peripheral inputs have no priority.
pic32mx3xx/4xx ds61143e-page 26 preliminary ? 2008 microchip technology inc. int0 46 72 i st external interrupt inputs int1 42 18 i st int2 43 19 i st int3 44 66 i st int4 45 67 i st mclr 7 13 i st master clear (device reset) input bring this line low to cause a reset. oc1 46 72 o ? output compare/pwm outputs oc2 49 76 o ? oc3 50 77 o ? oc4 51 78 o ? oc5 52 81 o ? ocfa 17 26 i st output compare fault a input ocfb 30 44 i st output compare fault b input osc1 39 63 i ana main oscillator input connection osc2 40 64 o ana main oscillator output connection pgc1 15 24 i/o st in-circuit debugger and icsp? programming clock pgd1 16 25 i/o st in-circuit debugger and icsp programming data pgc2 17 26 i/o st in-circuit debugger and icsp? programming clock pgd2 18 27 i/o st in-circuit debugger and icsp programming data pmall 30 44 o? parallel master port address latch enable low-byte (multiplexed mas- ter modes) pmalh 29 43 o ? parallel master port address latch enable high-byte (multiplexed master modes) table 1-5: pic32mx3xx/4xx pinout descriptions ? usb (continued) function pin number i/o input buffer description 64-pin 100-pin legend: ttl = ttl input buffer st = schmitt trigger input buffer ana = analog level input/output i 2 c? = i 2 c/smbus input buffer note: in some cases, i/o pins are multiplexed with more than one peripheral. in general, the dominant output control of a multiplexed i/o pin can be determined by the order of the peripheral output names assigned to a pin (read from left to right). multiplexed peripheral inputs have no priority.
? 2008 microchip technology inc. preliminary ds61143e-page 27 pic32mx3xx/4xx pma0 30 44 o? parallel master port address bit 0 input (buffered slave modes) and output (master modes) pma1 29 43 o ? parallel master port address bit 1 input (buffered slave modes) and output (master modes) pma2 8 14 o ? parallel master port address (demultiplexed master modes) pma3 6 12 o ? pma4 5 11 o ? pma5 4 10 o ? pma6 16 29 o ? pma7 22 28 o ? pma8 32 50 o ? pma9 31 49 o ? pma10 28 42 o ? pma11 27 41 o ? pma12 24 35 o ? pma13 23 34 o ? pma14 45 71 o ? address bit 14 pma15 44 70 o ? address bit 15 pmcs1 45 71 o ? parallel master port chip select 1 strobe pmcs2 44 70 o ? parallel master port chip select 2 strobe pmd0 60 93 i/o st/ttl parallel master port data (demultiplexed master mode) or address/data (multiplexed master modes) pmd1 61 94 i/o st/ttl pmd2 62 98 i/o st/ttl pmd3 63 99 i/o st/ttl pmd4 64 100 i/o st/ttl pmd5 1 3 i/o st/ttl pmd6 2 4 i/o st/ttl pmd7 3 5 i/o st/ttl pmd8 ? 90 i/o st/ttl pmd9 ? 89 i/o st/ttl pmd10 ? 88 i/o st/ttl pmd11 ? 87 i/o st/ttl pmd12 ? 79 i/o st/ttl pmd13 ? 80 i/o st/ttl pmd14 ? 83 i/o st/ttl pmd15 ? 84 i/o st/ttl pmenb 52 81 o ? parallel master port enable strobe (master mode 1) pmrd 53 82 o ? parallel master port read strobe (master mode 2) pmrd/pmwr 53 82 o ? parallel master port read/write strobe (master mode 1) pmwr 52 81 o ? parallel master port write strobe (master mode 2) table 1-5: pic32mx3xx/4xx pinout descriptions ? usb (continued) function pin number i/o input buffer description 64-pin 100-pin legend: ttl = ttl input buffer st = schmitt trigger input buffer ana = analog level input/output i 2 c? = i 2 c/smbus input buffer note: in some cases, i/o pins are multiplexed with more than one peripheral. in general, the dominant output control of a multiplexed i/o pin can be determined by the order of the per ipheral output names assigned to a pin (read from left to right). multiplexed peripheral inputs have no priority.
pic32mx3xx/4xx ds61143e-page 28 preliminary ? 2008 microchip technology inc. ra0 ? 17 i/o st porta digital i/o notes: on 100-pin devices, jtag program/debug port is multi- plexed with port pins ra0, ra1, ra4 and ra5. at reset, these pins are controlled by the jtag port. to use these pins for general purpose i/o, the user?s application code must clear jtagen (ddpcon<3>) bit = 0 . to use these pins for jtag program/debug, the user?s application code must maintain jtagen bit = 1 . on specific 100-pin devices, the instruction trace port is multiplexed with porta pins ra6, ra7; portg pins rg12, rg13 and rg14. at power-on reset, these pins are general purpose i/o pins. to maintain these pins as general purpose i/o pins, the user?s application code must maintain troen (ddpcon<2>) bit = 0 . to use these pins as instruction trace pins, troen must be set = 1 . ra1 ? 38 i/o st ra2 ? 58 i/o st ra3 ? 59 i/o st ra4 ? 60 i/o st ra5 ? 61 i/o st ra6 ? 91 i/o st ra7 ? 92 i/o st ra9 ? 28 i/o st ra10 ? 29 i/o st ra14 ? 66 i/o st ra15 ? 67 i/o st rb0 16 25 i/o st portb digital i/o note: on 64-pin devices, jtag pr ogram/debug port is multi- plexed with port pins rb 10, rb11, rb12 and rb13. at reset, these pins are controll ed by the jtag port. to use these pins for general purpose i/o, the user?s application code must clear jtagen (ddpcon<3>) bit = 0 . to use these pins for jtag program/debug, the user?s application code must maintain jtagen bit = 1 . rb1 15 24 i/o st rb2 14 23 i/o st rb3 13 22 i/o st rb4 12 21 i/o st rb5 11 20 i/o st rb6 17 26 i/o st rb7 18 27 i/o st rb8 21 32 i/o st rb9 22 33 i/o st rb10 23 34 i/o st rb11 24 35 i/o st rb12 27 41 i/o st rb13 28 42 i/o st rb14 29 43 i/o st rb15 30 44 i/o st rc1 ? 6 i/o st portc digital i/o rc2 ? 7 i/o st rc3 ? 8 i/o st rc4 ? 9 i/o st rc12 39 63 i/o st rc13 47 73 i/o st rc14 48 74 i/o st rc15 40 64 i/o st table 1-5: pic32mx3xx/4xx pinout descriptions ? usb (continued) function pin number i/o input buffer description 64-pin 100-pin legend: ttl = ttl input buffer st = schmitt trigger input buffer ana = analog level input/output i 2 c? = i 2 c/smbus input buffer note: in some cases, i/o pins are multiplexed with more than one peripheral. in general, the dominant output control of a multiplexed i/o pin can be determined by the order of the peripheral output names assigned to a pin (read from left to right). multiplexed peripheral inputs have no priority.
? 2008 microchip technology inc. preliminary ds61143e-page 29 pic32mx3xx/4xx rd0 46 72 i/o st portd digital i/o rd1 49 76 i/o st rd2 50 77 i/o st rd3 51 78 i/o st rd4 52 81 i/o st rd5 53 82 i/o st rd6 54 83 i/o st rd7 55 84 i/o st rd8 42 68 i/o st rd9 43 69 i/o st rd10 44 70 i/o st rd11 45 71 i/o st rd12 ? 79 i/o st rd13 ? 80 i/o st rd14 ? 47 i/o st rd15 ? 48 i/o st re0 60 93 i/o st porte digital i/o re1 61 94 i/o st re2 62 98 i/o st re3 63 99 i/o st re4 64 100 i/o st re5 1 3 i/o st re6 2 4 i/o st re7 3 5 i/o st re8 ? 18 i/o st re9 ? 19 i/o st rf0 58 87 i/o st portf digital i/o rf1 59 88 i/o st rf2 ? 52 i/o st rf3 33 51 i/o st rf4 31 49 i/o st rf5 32 50 i/o st rf8 ? 53 i/o st rf12 ? 40 i/o st rf13 ? 39 i/o st table 1-5: pic32mx3xx/4xx pinout descriptions ? usb (continued) function pin number i/o input buffer description 64-pin 100-pin legend: ttl = ttl input buffer st = schmitt trigger input buffer ana = analog level input/output i 2 c? = i 2 c/smbus input buffer note: in some cases, i/o pins are multiplexed with more than one peripheral. in general, the dominant output control of a multiplexed i/o pin can be determined by the order of the per ipheral output names assigned to a pin (read from left to right). multiplexed peripheral inputs have no priority.
pic32mx3xx/4xx ds61143e-page 30 preliminary ? 2008 microchip technology inc. rg0 ? 90 i/o st portg digital i/o note: on specific 100-pin devices, the instruction trace port is multiplexed with porta pins ra6, ra7; portg pins rg12, rg13 and rg14. at power-on reset, these pins are general purpose i/o pins. to maintain these pins as general purpose i/o pins, the user?s application code must maintain troen (ddpcon<2>) bit = 0 . to use these pins as instruction trace pins, troen must be set = 1 . rg1 ? 89 i/o st rg2 37 57 i/o st rg3 36 56 i/o st rg6 4 10 i/o st rg7 5 11 i/o st rg8 6 12 i/o st rg9 8 14 i/o st rg12 ? 96 i/o st rg13 ? 97 i/o st rg14 ? 95 i/o st rg15 ? 1 i/o st rtcc 42 68 o ? real-time clock alarm output sck1 ? 70 o ? sck2 4 10 i/o st spi2 serial clock output scl1 44 66 i/o i 2 c i2c1 synchronous serial clock input/output scl2 32 58 i/o i 2 c i2c2 synchronous serial clock input/output sda1 43 67 i/o i 2 c i2c1 data input/output sda2 31 59 i/o i 2 c i2c2 data input/output sdi1 ? 9 i st sdi2 5 11 i st spi2 serial data input sdo1 ? 72 o ? sdo2 6 12 o ? spi2 serial data output sosci 47 73 i ana secondary oscillator/timer1 external clock input sosco 48 74 o ana secondary oscillator/timer1 external clock output ss1 ? 69 i/o st slave select input/frame select output (spi1) ss2 8 14 i/o st slave select input/frame select output (spi2) t1ck 48 74 i st timer1 external clock input t2ck ? 6 i st timer2 external clock input t3ck ? 7 i st timer3 external clock input t4ck ? 8 i st timer4 external clock input t5ck ? 9 i st timer5 external clock input tck 27 38 i st jtag test clock/programming clock input tdi 28 60 i st jtag test data/programming data input tdo 24 61 o ? jtag test data output tms 23 17 i st jtag test mode select input trclk ? 91 o ? trace clock trd0 ? 97 o ? trace data bit 0 trd1 ? 96 o ? trace data bit 1 trd2 ? 95 o ? trace data bit 2 trd3 ? 92 o ? trace data bit 3 table 1-5: pic32mx3xx/4xx pinout descriptions ? usb (continued) function pin number i/o input buffer description 64-pin 100-pin legend: ttl = ttl input buffer st = schmitt trigger input buffer ana = analog level input/output i 2 c? = i 2 c/smbus input buffer note: in some cases, i/o pins are multiplexed with more than one peripheral. in general, the dominant output control of a multiplexed i/o pin can be determined by the order of the peripheral output names assigned to a pin (read from left to right). multiplexed peripheral inputs have no priority.
? 2008 microchip technology inc. preliminary ds61143e-page 31 pic32mx3xx/4xx u1cts 43 47 i st uart1 clear to send input u1rts 49 48 o ? uart1 request to send output u1rx 50 52 i st uart1 receive u1tx 51 53 o ? uart1 transmit output u2cts 21 40 i st uart2 clear to send input u2rts 29 39 o ? uart2 request to send output u2rx 31 49 i st uart 2 receive input u2tx 32 50 o ? uart2 transmit output v dd 10, 26, 38 2, 16, 37, 46, 62 p ? positive supply for peripheral digital logic and i/o pins v ddcap 56 85 p? external filter capacitor connection (regulator enabled) v ddcore 56 85 p? positive supply for microcontroller core logic (regulator disabled) v ref - 15 28 i ana a/d and comparator reference voltage (low) input v ref + 16 29 i ana a/d and comparator reference voltage (high) input v ss 9, 25, 41 15, 36, 45, 65, 75 p ? ground reference for logic and i/o pins v bus 34 54 i ana usb bus power monitor v usb 35 55 p ? usb internal transceiver supply v buson 11 20 o ? usb host and otg bus power control output usbid 33 51 i st usb otg id detect table 1-5: pic32mx3xx/4xx pinout descriptions ? usb (continued) function pin number i/o input buffer description 64-pin 100-pin legend: ttl = ttl input buffer st = schmitt trigger input buffer ana = analog level input/output i 2 c? = i 2 c/smbus input buffer note: in some cases, i/o pins are multiplexed with more than one peripheral. in general, the dominant output control of a multiplexed i/o pin can be determined by the order of the per ipheral output names assigned to a pin (read from left to right). multiplexed peripheral inputs have no priority.
pic32mx3xx/4xx ds61143e-page 32 preliminary ? 2008 microchip technology inc. notes:
? 2008 microchip technology inc. preliminary ds61143e-page 33 pic32mx3xx/4xx 2.0 pic32mx mcu the mcu module is the heart of the pic32mx3xx/4xx family processor. the mcu fetches instructions, decodes each instruction, fetches source operands, executes each instruction and writes the results of instruction execution to the proper destinations. 2.1 features ? 5-stage pipeline ? 32-bit address and data paths ? mips32 enhanced architecture (release 2) - multiply-accumulate and multiply-subtract instructions - targeted multiply instruction - zero/one detect instructions - wait instruction - conditional move instructions ( movn , movz ) - vectored interrupts - programmable exception vector base - atomic interrupt enable/disable - gpr shadow registers to minimize latency for interrupt handlers - bit field manipulation instructions ? mips16e? code compression - 16-bit encoding of 32-bit instructions to improve code density - special pc-relative instructions for efficient loading of addresses and constants - save & restore macro instructions for setting up and tearing down stack frames within subroutines - improved support for handling 8 and 16-bit data types ? simple fixed mapping translation (fmt) mechanism ? simple dual bus interface - independent 32-bit address and data busses - transactions can be aborted to improve interrupt latency ? autonomous multiply/divide unit - maximum issue rate of one 32x16 multiply per clock - maximum issue rate of one 32x32 multiply every other clock - early-in iterative divide. minimum 11 and maximum 34 clock latency (dividend ( rs ) sign extension-dependent) ? power control - minimum frequency: 0 mhz - low-power mode (triggered by wait instruction) - extensive use of local gated clocks ? ejtag debug and instruction trace - support for single stepping - virtual instruction and data address/value breakpoints - pc tracing with trace compression note: this data sheet summarizes the features of the pic32mx3xx/4xx family of devices. it is not intended to be a comprehensive refer- ence source. refer to the ?pic32mx family reference manual? (ds61132) for a detailed description of the pic32mx mcu. resources for the mips32 ? m4k ? processor core are available at www.mips.com/products/cores/32-bit-cores/ mips32-m4k/#.
pic32mx3xx/4xx ds61143e-page 34 preliminary ? 2008 microchip technology inc. 2.2 architecture overview the pic32mx3xx/4xx family core contains several logic blocks working together in parallel, providing an efficient high performance computing engine. the following blocks are included with the core: ? execution unit ? multiply/divide unit (mdu) ? system control coprocessor (cp0) ? fixed mapping translation (fmt) ? dual internal bus interfaces ? power management ? mips16e support ? enhanced jtag (ejtag) controller figure 2-1: mcu block diagram dual bus i/f system coprocessor mdu fmt tap ejtag power mgmt off-chip debug i/f execution core (rf/alu/shift) bus matrix trace trace i/f bus interface
? 2008 microchip technology inc. preliminary ds61143e-page 35 pic32mx3xx/4xx 2.2.1 execution unit the pic32mx3xx/4xx family core execution unit implements a load/store architecture with single-cycle alu operations (logical, shift, add, subtract) and an autonomous multiply/divide unit. the core contains thirty-two 32-bit general purpose registers used for integer operations and address calculation. one additional register file shadow set (containing thirty-two registers) is added to minimize context switching overhead during interrupt/exception processing. the register file consists of two read ports and one write port and is fully bypassed to minimize operation latency in the pipeline. the execution unit includes: ? 32-bit adder used for calculating the data address ? address unit for calculating the next instruction address ? logic for branch determination and branch target address calculation ? load aligner ? bypass multiplexers used to avoid stalls when executing instructions streams where data producing instructions are followed closely by consumers of their results ? leading zero/one detect unit for implementing the clz and clo instructions ? arithmetic logic unit (alu) for performing bitwise logical operations ? shifter and store aligner 2.2.2 multiply/divide unit (mdu) the pic32mx3xx/4xx family core includes a multiply/divide unit (mdu) that contains a separate pipeline for multiply and divide operations. this pipeline operates in parallel with the integer unit (iu) pipeline and does not stall when the iu pipeline stalls. this allows mdu operations to be partially masked by system stalls and/or other integer unit instructions. the high-performance mdu consists of a 32x16 booth recoded multiplier, result/accumulation registers (hi and lo), a divide state machine, and the necessary multiplexers and control logic. the first number shown (?32? of 32x16) represents the rs operand. the second number (?16? of 32x16) represents the rt operand. the pic32mx core only checks the value of the latter ( rt) operand to determine how many times the operation must pass through the multiplier. the 16x16 and 32x16 operations pass through the multiplier once. a 32x32 operation passes through the multiplier twice. the mdu supports execution of one 16x16 or 32x16 multiply operation every clock cycle; 32x32 multiply operations can be issued every other clock cycle. appropriate interlocks are implemented to stall the issuance of back-to-back 32x32 multiply operations. the multiply operand size is automatically determined by logic built into the mdu. divide operations are implemented with a simple 1 bit per clock iterative algorithm. an early-in detection checks the sign extension of the dividend ( rs ) operand. if rs is 8 bits wide, 23 iterations are skipped. for a 16- bit-wide rs, 15 iterations are skipped, and for a 24-bit- wide rs, 7 iterations are skipped. any attempt to issue a subsequent mdu instruction while a divide is still active causes an iu pipeline stall until the divide operation is completed. table 2-1 lists the repeat rate (peak issue rate of cycles until the operation can be reissued) and latency (number of cycles until a result is available) for the pic32mx core multiply and divide instructions. the approximate latency and repeat rates are listed in terms of pipeline clocks.
pic32mx3xx/4xx ds61143e-page 36 preliminary ? 2008 microchip technology inc. the mips architecture defines that the result of a multiply or divide operation be placed in the hi and lo registers. using the move-from-hi ( mfhi ) and move- from-lo ( mflo ) instructions, these values can be transferred to the general purpose register file. in addition to the hi/lo targeted operations, the mips32 architecture also defines a multiply instruction, mul, which places the least significant results in the primary register file instead of the hi/lo register pair. by avoiding the explicit mflo instruction, required when using the lo register, and by supporting multiple destination registers, the throughput of multiply-intensive operations is increased. two other instructions, multiply-add ( madd ) and multiply-subtract ( msub ), are used to perform the multiply-accumulate and multiply-subtract operations. the madd instruction multiplies two numbers and then adds the product to the current contents of the hi and lo registers. similarly, the msub instruction multiplies two operands and then subtracts the product from the hi and lo registers. the madd and msub operations are commonly used in dsp algorithms. table 2-1: pic32mx3xx/4xx family core high-performance integer multiply/divide unit latencies and repeat rates opcode operand size (mul rt ) (div rs ) latency repeat rate mult/multu, madd/maddu, msub/msubu 16 bits 1 1 32 bits 2 2 mul 16 bits 2 1 32 bits 3 2 div/divu 8 bits 12 11 16 bits 19 18 24 bits 26 25 32 bits 33 32
? 2008 microchip technology inc. preliminary ds61143e-page 37 pic32mx3xx/4xx 2.2.3 system control coprocessor (cp0) in the mips architecture, cp0 is responsible for the virtual-to-physical address translation, the exception control system, the processor?s diagnostics capability, the operating modes (kernel, user, and debug), and whether interrupts are enabled or disabled. configuration information, such as presence of options like mips16e, is also available by accessing the cp0 registers, listed in table 2-2. table 2-2: coprocessor 0 registers register number register name function 0-6 reserved reserved in the pic32mx3xx/4xx family core 7 hwrena enables access via the rdhwr instruction to selected hardware registers 8 badvaddr ( 1) reports the address for the most recent address-related exception 9 count ( 1) processor cycle count 10 reserved reserved in the pic32mx3xx/4xx family core 11 compare ( 1) timer interrupt control 12 status ( 1) processor status and control 12 intctl ( 1) interrupt system status and control 12 srsctl ( 1) shadow register set status and control 12 srsmap ( 1) provides mapping from vectored interrupt to a shadow set 13 cause ( 1) cause of last general exception 14 epc ( 1) program counter at last exception 15 prid processor identification and revision 15 ebase exception vector base register 16 config configuration register 16 config1 configuration register 1 16 config2 configuration register 2 16 config3 configuration register 3 17-22 reserved reserved in the pic32mx3xx/4xx family core 23 debug ( 2) debug control and exception status 24 depc ( 2) program counter at last debug exception 25-29 reserved reserved in the pic32mx3xx/4xx family core 30 errorepc ( 1) program counter at last error 31 desave ( 2) debug handler scratchpad register note 1: registers used in exception processing. 2: registers used during debug.
pic32mx3xx/4xx ds61143e-page 38 preliminary ? 2008 microchip technology inc. coprocessor 0 also contains the logic for identifying and managing exceptions. exceptions can be caused by a variety of sources, including alignment errors in data, external events, or program errors. table 2-3 shows the exception types in order of priority. table 2-3: pic32mx3xx/4xx family core exception types exception description reset assertion mclr or a power-on reset (por) dss ejtag debug single step dint ejtag debug interrupt. caused by the assertion of the external ej_dint input, or by setting the ejtagbrk bit in the ecr register nmi assertion of nmi signal interrupt assertion of unmasked hardware or software interrupt signal dib ejtag debug hardware instruction break matched adel fetch address alignment error fetch reference to protected address ibe instruction fetch bus error dbp ejtag breakpoint (execution of sdbbp instruction) sys execution of syscall instruction bp execution of break instruction ri execution of a reserved instruction cpu execution of a coprocessor instruction for a coprocessor that is not enabled ceu execution of a corextend instruction when corextend is not enabled ov execution of an arithmetic instruction that overflowed tr execution of a trap (when trap condition is true) ddbl / ddbs ejtag data address break (address only) or ejtag data value break on store (address + value) adel load address alignment error load reference to protected address ades store address alignment error store to protected address dbe load or store bus error ddbl ejtag data hardware breakpoint matched in load data compare
? 2008 microchip technology inc. preliminary ds61143e-page 39 pic32mx3xx/4xx 2.2.4 interrupt handling the pic32mx3xx/4xx family core includes support for peripheral interrupts, two software interrupts, and a timer interrupt. the pic32mx mcu uses the mips external interrupt controller (eic) mode, which redefines the way in which interrupts are handled to provide full support for an external interrupt controller handling prioritization and vectoring of interrupts. this presence of this mode denoted by the veic bit in the config3 register. on the pic32mx core, the veic bit is always set to ? 1 ? to indicate the presence of an external interrupt controller. the interrupt controller specifies which shadow set should be used upon entry to a particular vector. the shadow registers further improve interrupt latency by avoiding the need to save context when invoking an interrupt handler. 2.2.5 gpr shadow registers release 2 of the mips32 architecture optionally removes the need to save and restore gprs on entry to high priority interrupts or exceptions, and to provide specified processor modes with the same capability. this is done by introducing multiple copies of the gprs, called ?shadow sets?, and allowing privileged software to associate a shadow set with entry to kernel mode via an interrupt vector or exception. the normal gprs are logically considered shadow set zero. the pic32mx3xx/4xx family core implements two sets of registers, the normal gprs, and one shadow set. this is indicated by the srsctl hss field. note: although eic mode is designated as ?external?, the interrupt controller is on-chip.
pic32mx3xx/4xx ds61143e-page 40 preliminary ? 2008 microchip technology inc. 2.3 modes of operation the pic32mx3xx/4xx family core supports three modes of operation: user mode, kernel mode and debug mode. user mode is most often used for applications programs. kernel mode is typically used for handling exceptions and operating system kernel functions, including cp0 management and i/o device accesses. an additional debug mode is used during system bring-up and software development. refer to the ejtag specification for more information on debug mode. figure 2-2: pic32mx3xx/4xx family core virtual address map kuseg kseg0 kseg1 kseg2 kseg3 0x00000000 0x7fffffff 0x80000000 0x9fffffff 0xa0000000 0xbfffffff 0xc0000000 0xdfffffff 0xe0000000 0xf1ffffff kernel virtual address space unmapped, 512 mb kernel virtual address space uncached unmapped, 512 mb kernel virtual address space user virtual address space note 1: this space is mapped to memory in user or kernel mode, and by the ejtag module in debug mode. 0xff200000 0xff3fffff 0xff400000 0xffffffff memory/ejtag (1) fixed mapped, 2048 mb fixed mapped, 512 mb fixed mapped fixed mapped
? 2008 microchip technology inc. preliminary ds61143e-page 41 pic32mx3xx/4xx 2.3.1 fixed mapping translation the pic32mx3xx/4xx family core provides a simple fixed mapping translation (fmt) mechanism that is smaller and simpler than a full translation lookaside buffer (tlb) found in other mips cores. like a tlb, the fmt performs virtual-to-physical address translation and provides attributes for the different segments. those segments that are unmapped in a tlb implementation (kseg0 and kseg1) are translated identically by the fmt. figure 2-3 shows how the fmt is implemented in the pic32mx core. figure 2-3: address translation during memory access in general, the fmt also determines the cacheability of each segment. these attributes are controlled via bits in the config register. table 2-4 shows the encoding for the k23 (bits 30:28), ku (bits 27:25), and k0 (bits 2:0) fields of the config register. the pic32mx core passes these config fields to the prefetch cache module to determine cacheability of program memory flash accesses. table 2-5 shows how the cacheability of the virtual address segments is controlled by these fields. instruction address calculator fmt data address calculator physical virtual address virtual address address physical address sram interface data sram instn sram table 2-4: cache coherency attributes config register fields k23, ku, and k0 cache coherency attribute 2 uncached 3 cacheable
pic32mx3xx/4xx ds61143e-page 42 preliminary ? 2008 microchip technology inc. in the pic32mx3xx/4xx family core, no translation exceptions are taken, although address errors are still possible. the fmt performs a simple translation to map from virtual addresses to physical addresses. this mapping is shown in figure 2-4. figure 2-4: fmt memory map (erl = 0 ) in the pic32mx3xx/4xx family core table 2-5: cacheability of segments with fixed mapping translation segment virtual address range cacheability useg/kuseg 0x0000_0000-0x7fff_ffff controlled by the ku field (bits 27:25) of the config register. see figure 2-4 for mapping. this segment is always uncached when erl = 1 . kseg0 0x8000_0000- 0x9fff_ffff controlled by the k0 field (bits 2:0) of the config register. see figure 2-4 for mapping. kseg1 0xa000_0000-0xbfff_ffff always uncacheable. kseg2 0xc000_0000-0xdfff_ffff controlled by the k23 field (bits 30:28) of the config register. see figure 2-4 for mapping. kseg3 0xe000_0000-0xffff_ffff controlled by the k23 field (bits 30:28) of the config register. see figure 2-4 for mapping. useg/kuseg kseg0 kseg3 kseg2 kseg1 virtual address 0x8000_0000 0x0000_0000 0xa000_0000 0xc000_0000 0xe000_0000 useg/kuseg kseg3 kseg2 physical address 0x0000_0000 0xc000_0000 0xe000_0000 0x2000_0000 kseg0/kseg1 0x4000_0000 reserved
? 2008 microchip technology inc. preliminary ds61143e-page 43 pic32mx3xx/4xx when erl = 1 , useg and kuseg become unmapped (virtual address is identical to the physical address) and uncached. this behavior is the same as if there was a tlb. this mapping is shown in figure 2-5. figure 2-5: pic32mx3xx/4xx family core fmt memory map (erl = 1 ) 2.3.2 dual internal bus interfaces the sram interface includes dual instruction and data interfaces. the dual interface enables independent connection to instruction and data devices. it yields the highest per- formance, since the pipeline can generate simultane- ous i and d requests which are then serviced in parallel. the internal buses are connected to the bus matrix unit, which is a switch fabric that provides this parallel operation. 2.3.3 mips16e execution when the core is operating in mips16e mode, instruction fetches only require 16 bits of data to be returned. for improved efficiency, however, the core will fetch 32 bits of instruction data whenever the address is word-aligned. thus for sequential mips16e code, fetches only occur for every other instruction, resulting in better performance and reduced system power. useg/kuseg kseg0 kseg3 kseg2 kseg1 virtual address useg/kuseg kseg3 kseg2 physical address kseg0/kseg1 reserved 0x8000_0000 0x0000_0000 0xa000_0000 0xc000_0000 0xe000_0000 0x8000_0000 0x0000_0000 0xc000_0000 0xe000_0000
pic32mx3xx/4xx ds61143e-page 44 preliminary ? 2008 microchip technology inc. 2.4 power management the pic32mx3xx/4xx family core offers a number of power management features, including low-power design, active power management, and power-down modes of operation. the core is a static design that supports slowing or halting the clocks, which reduces system power consumption during idle periods. 2.4.1 instructio n-controlled power management the mechanism for invoking power-down mode is through execution of the wait instruction. for more information on power management, see section 23.0 ?power saving? . 2.4.2 local clock gating the majority of the power consumed by the pic32mx3xx/4xx family core is in the clock tree and clocking registers. the pic32mx family uses extensive use of local gated-clocks to reduce this dynamic power consumption. 2.5 ejtag debug support the pic32mx3xx/4xx family core provides for an enhanced jtag (ejtag) interface for use in the software debug of application and kernel code. in addition to standard user mode and kernel modes of operation, the pic32mx3xx/4xx family core provides a debug mode that is entered after a debug exception (derived from a hardware breakpoint, single-step exception, etc.) is taken and continues until a debug exception return ( deret ) instruction is executed. during this time, the processor executes the debug exception handler routine. the ejtag interface operates through the test access port (tap), a serial communication port used for transferring test data in and out of the pic32mx3xx/4xx family core. in addition to the standard jtag instructions, special instructions defined in the ejtag specification define what registers are selected and how they are used. 2.5.1 debug registers three debug registers (debug, depc, and desave) have been added to the mips coprocessor 0 (cp0) register set. the debug register shows the cause of the debug exception and is used for setting up single- step operations. the depc, or debug exception program counter, register holds the address on which the debug exception was taken. this is used to resume program execution after the debug operation finishes. finally, the desave, or debug exception save, register enables the saving of general purpose registers used during execution of the debug exception handler. to exit debug mode, a debug exception return ( deret ) instruction is executed. when this instruction is executed, the system exits debug mode, allowing normal execution of application and system code to resume. 2.5.2 ejtag hardware breakpoints there are several types of simple hardware breakpoints defined in the ejtag specification. these stop the normal operation of the mcu and force the system into debug mode. there are two types of simple hardware breakpoints implemented in the pic32mx3xx/4xx family core: instruction breakpoints and data breakpoints. the pic32mx3xx/4xx family core has two data and six instruction breakpoints instruction breaks occur on instruction fetch operations, and the break is set on the virtual address. a mask can be applied to the virtual address to set breakpoints on a range of instructions. data breakpoints occur on load/store transactions. breakpoints are set on virtual address values, similar to the instruction breakpoint. data breakpoints can be set on a load, a store, or both. data breakpoints can also be set based on the value of the load/store operation. finally, masks can be applied to both the virtual address and the load/store value. 2.5.3 instruction tracing the pic32mx3xx/4xx family core includes trace support for real-time tracing of instruction addresses. the trace information is collected in an off-chip memory, for post-capture processing by trace regeneration software. off-chip trace memory is accessed through a special trace probe that consists of 4 data pins plus a clock.
? 2008 microchip technology inc. preliminary ds61143e-page 45 pic32mx3xx/4xx 2.6 mcu initialization software is required to initialize the following parts of the device after a reset event: ? general purpose registers ? coprocessor 0 state 2.6.1 general purpose registers the mcu register file powers up in an unknown state with the exception of r0 which is always 0 . initializing the rest of the register file is not required for proper operation of hardware. depending on the software environment however, several registers may need to be initialized. some of these are: ? sp ? stack pointer ? gp ? global pointer ? fp ? frame pointer 2.6.2 coprocessor 0 state miscellaneous cp0 states need to be initialized prior to leaving the boot code. there are various exceptions which are blocked by erl = 1 or exl = 1 and which are not cleared by reset. these can be cleared to avoid taking spurious exceptions when leaving the boot code. 2.7 i/o pin configuration the mcu module has ejtag pins that may be config- ured as user-available i/o pins. if ejtag is used for debug, it is important to make sure that software does not clear ddpcon. table 2-6: cp0 initialization cp0 register action cause wp (watch pending), sw0/1 (software interrupts) should be cleared. config typically, the k0, ku and k23 fields should be set to the desired cache coherency algorithm (cca) value prior to accessing the corresponding memory regions. but in the m4k core, all cca values are treated identically, so the hardware reset value of these fields need not be modified. count ( 1 ) should be set to a known value if timer interrupts are used. compare ( 1 ) should be set to a known value if timer interrupts are used. the write to compare will also clear any pending timer interrupts (thus, count should be set before compare to avoid any unexpected interrupts). status desired state of the device should be set. other cp0 state other registers should be written before they are read. some registers are not explicitly writable, and are only updated as a by-product of instruction execution or a taken exception. uninitialized bits should be masked off after reading these registers. note 1: when the count register is equal to the compare register, a timer interrupt is signaled. there is a mask bit in the interrupt controller to disable passing this interrupt to the mcu if desired.
pic32mx3xx/4xx ds61143e-page 46 preliminary ? 2008 microchip technology inc. notes:
? 2008 microchip technology inc. preliminary ds61143e-page 47 pic32mx3xx/4xx 3.0 instruction set the pic32mx3xx/4xx family instruction set complies with the mips32 release 2 instruction set architecture. pic32mx does not support the following features: ? coreextend instructions ? coprocessor 1 instructions ? coprocessor 2 instructions table 3-1 provides a summary of the instructions that are implemented by the pic32mx3xx/4xx family core. note: refer to ?mips32 ? architecture for pro- grammers volume ii: the mips32 ? instruction set? at www.mips.com for more information. table 3-1: pic32mx3xx/4xx instruction set instruction description function add integer add rd = rs + rt addi integer add immediate rt = rs + immed addiu unsigned integer add immediate rt = rs + u immed addiupc unsigned integer add immediate to pc (mips16e? only) rt = pc + u immed addu unsigned integer add rd = rs + u rt and logical and rd = rs & rt andi logical and immediate rt = rs & (0 16 || immed) b unconditional branch (assembler idiom for: beq r0, r0, offset) pc += (int)offset bal branch and link (assembler idiom for: bgezal r0, offset) gpr[31> = pc + 8 pc += (int)offset beq branch on equal if rs == rt pc += (int)offset beql branch on equal likely if rs == rt pc += (int)offset else ignore next instruction bgez branch on greater than or equal to zero if !rs[31> pc += (int)offset bgezal branch on greater than or equal to zero and link gpr[31> = pc + 8 if !rs[31> pc += (int)offset bgezall branch on greater than or equal to zero and link likely gpr[31> = pc + 8 if !rs[31> pc += (int)offset else ignore next instruction bgezl branch on greater than or equal to zero likely if !rs[31> pc += (int)offset else ignore next instruction bgtz branch on greater than zero if !rs[31> && rs != 0 pc += (int)offset bgtzl branch on greater than zero likely if !rs[31> && rs != 0 pc += (int)offset else ignore next instruction
pic32mx3xx/4xx ds61143e-page 48 preliminary ? 2008 microchip technology inc. blez branch on less than or equal to zero if rs[31> || rs == 0 pc += (int)offset blezl branch on less than or equal to zero likely if rs[31> || rs == 0 pc += (int)offset else ignore next instruction bltz branch on less than zero if rs[31> pc += (int)offset bltzal branch on less than zero and link gpr[31> = pc + 8 if rs[31> pc += (int)offset bltzall branch on less than zero and link likely gpr[31> = pc + 8 if rs[31> pc += (int)offset else ignore next instruction bltzl branch on less than zero likely if rs[31> pc += (int)offset else ignore next instruction bne branch on not equal if rs != rt pc += (int)offset bnel branch on not equal likely if rs != rt pc += (int)offset else ignore next instruction break breakpoint break exception clo count leading ones rd = numleadingones(rs) clz count leading zeroes rd = numleadingzeroes(rs) cop0 coprocessor 0 operation see software user?s manual deret return from debug exception pc = depc exit debug mode di atomically disable interrupts rt = status; status ie = 0 div divide lo = (int)rs / (int)rt hi = (int)rs % (int)rt divu unsigned divide lo = (uns)rs / (uns)rt hi = (uns)rs % (uns)rt ehb execution hazard barrier stop instruction execution until execution hazards are cleared ei atomically enable interrupts rt = status; status ie = 1 eret return from exception if sr[2> pc = errorepc else pc = epc sr[1> = 0 sr[2> = 0 ll = 0 ext extract bit field rt = extractfield(rs, pos, size) table 3-1: pic32mx3xx/4xx instruction set (continued) instruction description function
? 2008 microchip technology inc. preliminary ds61143e-page 49 pic32mx3xx/4xx ins insert bit field rt = insertfield(rs, rt, pos, size) j unconditional jump pc = pc[31:28> || offset<<2 jal jump and link gpr[31> = pc + 8 pc = pc[31:28> || offset<<2 jalr jump and link register rd = pc + 8 pc = rs jalr.hb jump and link register with hazard barrier like jalr , but also clears execution and instruction hazards jalrc jump and link register compact ? do not execute instruction in jump delay slot (mips16e? only) rd = pc + 2 pc = rs jr jump register pc = rs jr.hb jump register with hazard barrier like jr , but also clears execution and instruction hazards jrc jump register compact ? do not execute instruction in jump delay slot (mips16e only) pc = rs lb load byte rt = (byte)mem[rs+offset> lbu unsigned load byte rt = (ubyte))mem[rs+offset> lh load halfword rt = (half)mem[rs+offset> lhu unsigned load halfword rt = (uhalf)mem[rs+offset> ll load linked word rt = mem[rs+offset> ll = 1 lladr = rs + offset lui load upper immediate rt = immediate << 16 lw load word rt = mem[rs+offset> lwpc load word, pc relative rt = mem[pc+offset> lwl load word left see architecture reference manual lwr load word right see architecture reference manual madd multiply-add hi | lo += (int)rs * (int)rt maddu multiply-add unsigned hi | lo += (uns)rs * (uns)rt mfc0 move from coprocessor 0 rt = cpr[0, rd, sel> mfhi move from hi rd = hi mflo move from lo rd = lo movn move conditional on not zero if rt ? 0 then rd = rs movz move conditional on zero if rt = 0 then rd = rs msub multiply-subtract hi | lo -= (int)rs * (int)rt msubu multiply-subtract unsigned hi | lo -= (uns)rs * (uns)rt mtc0 move to coprocessor 0 cpr[0, n, sel> = rt mthi move to hi hi = rs mtlo move to lo lo = rs mul multiply with register write hi | lo =unpredictable rd = ((int)rs * (int)rt) 31..0 mult integer multiply hi | lo = (int)rs * (int)rd multu unsigned multiply hi | lo = (uns)rs * (uns)rd table 3-1: pic32mx3xx/4xx instruction set (continued) instruction description function
pic32mx3xx/4xx ds61143e-page 50 preliminary ? 2008 microchip technology inc. nop no operation (assembler idiom for: sll r0, r0, r0) nor logical nor rd = ~(rs | rt) or logical or rd = rs | rt ori logical or immediate rt = rs | immed rdhwr read hardware register allows unprivileged access to registers enabled by hwrena register rdpgpr read gpr from previous shadow set rt = sgpr[srsctl pss , rd> restore restore registers and deallocate stack frame (mips16e? only) see architecture reference manual rotr rotate word right rd = rt sa-1..0 || rt 31..sa rotrv rotate word right variable rd = rt rs-1..0 || rt 31..rs save save registers and allocate stack frame (mips16e only) see architecture reference manual sb store byte (byte)mem[rs+offset> = rt sc store conditional word if ll = 1 mem[rs+offset> = rt rt = ll sdbbp software debug break point trap to sw debug handler seb sign-extend byte rd = (byte)rs seh sign-extend half rd = (half)rs sh store half (half)mem[rs+offset> = rt sll shift left logical rd = rt << sa sllv shift left logical variable rd = rt << rs[4:0> slt set on less than if (int)rs < (int)rt rd = 1 else rd = 0 slti set on less than immediate if (int)rs < (int)immed rt = 1 else rt = 0 sltiu set on less than immediate unsigned if (uns)rs < (uns)immed rt = 1 else rt = 0 sltu set on less than unsigned if (uns)rs < (uns)immed rd = 1 else rd = 0 sra shift right arithmetic rd = (int)rt >> sa srav shift right arithmetic variable rd = (int)rt >> rs[4:0> srl shift right logical rd = (uns)rt >> sa srlv shift right logical variable rd = (uns)rt >> rs[4:0> ssnop superscalar inhibit no operation nop sub integer subtract rt = (int)rs - (int)rd subu unsigned subtract rt = (uns)rs - (uns)rd sw store word mem[rs+offset> = rt swl store word left see architecture reference manual table 3-1: pic32mx3xx/4xx instruction set (continued) instruction description function
? 2008 microchip technology inc. preliminary ds61143e-page 51 pic32mx3xx/4xx swr store word right see architecture reference manual sync synchronize see software user?s manual syscall system call systemcallexception teq trap if equal if rs == rt trapexception teqi trap if equal immediate if rs == (int)immed trapexception tge trap if greater than or equal if (int)rs >= (int)rt trapexception tgei trap if greater than or equal immediate if (int)rs >= (int)immed trapexception tgeiu trap if greater than or equal immediate unsigned if (uns)rs >= (uns)immed trapexception tgeu trap if greater than or equal unsigned if (uns)rs >= (uns)rt trapexception tlt trap if less than if (int)rs < (int)rt trapexception tlti trap if less than immediate if (int)rs < (int)immed trapexception tltiu trap if less than immediate unsigned if (uns)rs < (uns)immed trapexception tltu trap if less than unsigned if (uns)rs < (uns)rt trapexception tne trap if not equal if rs != rt trapexception tnei trap if not equal immediate if rs != (int)immed trapexception wait wait for interrupts stall until interrupt occurs wrpgpr write to gpr in previous shadow set sgpr[srsctl pss , rd> = rt wsbh word swap bytes within halfwords rd = rt 23..16 || rt 31..24 || rt 7..0 || rt 15..8 xor exclusive or rd = rs ^ rt xori exclusive or immediate rt = rs ^ (uns)immed zeb zero-extend byte (mips16e? only) rt = (ubyte) rs zeh zero-extend half (mips16e only) rt = (uhalf) rs table 3-1: pic32mx3xx/4xx instruction set (continued) instruction description function
pic32mx3xx/4xx ds61143e-page 52 preliminary ? 2008 microchip technology inc. notes:
? 2008 microchip technology inc. preliminary ds61143e-page 53 pic32mx3xx/4xx 4.0 oscillators this section describes the pic32mx3xx/4xx oscilla- tor system and its operation. the pic32mx oscillator system has the following modules and features: ? a total of four external and internal oscillator options as clock sources ? on-chip pll with user-selectable input divider, multiplier, and output divider to boost operating frequency on select internal and external oscillator sources ? on-chip user-selectable divisor postscaler on select oscillator sources ? software-controllable switching between various clock sources ? a fail-safe clock monitor (fscm) that detects clock failure and permits safe application recovery or shutdown a simplified diagram of the oscillator system is shown in figure 4-1. note: this data sheet summarizes the features of the pic32mx3xx/4xx family of devices. it is not intended to be a comprehensive refer- ence source. refer to the ?pic32mx family reference manual? (ds61132) for a detailed description of this peripheral.
pic32mx3xx/4xx ds61143e-page 54 preliminary ? 2008 microchip technology inc. figure 4-1: pic32mx3xx/4xx family clock diagram pll secondary oscillator (sosc) soscen and fsoscen sosco sosci timer1, rtcc osci osco primary oscillator xtpll, hspll, xt, hs, ec cpu & select peripherals peripherals frcdiv<2:0> wdt, pwrt 8 mhz typical frc 32 khz typical frc oscillator lprc oscillator sosc lprc clock control logic fail-safe clock monitor frcdiv ecpll, frcpll tun<5:0> div 16 fscm int fscm event postscaler fpllidiv<2:0> pbdiv<2:0> frc /16 postscaler pll multiplier cosc<2:0> cosc<2:0> f in div x (posc) div y pll output divider pllodiv<2:0> pll input divider div x 32.768 khz pllmult<2:0> nosc<2:0> oswen fscmen<1:0> pbclk 4 mhz uf in 5 mhz pll x24 usb clock (48 mhz) div 2 upllen ufrcen div x plldiv<2:0> uf in 4 mhz f in 5 mhz pbclk out in certain available on osco pin clock modes
? 2008 microchip technology inc. preliminary ds61143e-page 55 pic32mx3xx/4xx 4.1 control registers the oscillator module consists of the following special function registers (sfrs): ? osccon: control register for the oscillator module oscconclr, oscconset, oscconinv: atomic bit manipulation write-only registers for osccon register ? osctun: frc tuning register for the oscillator module osctunclr, osctunset, osctuninv: atomic bit manipulation write-only registers for osctun register the oscillator module also has the following associated bits for interrupt control: ? interrupt flag status bits (ifs1<14>) for clock fail fscmif in ifs1 interrupt register ? interrupt enable control bits (iec1<14>) for clock fail fscmie in iec1 interrupt register ? interrupt priority control bits (fscmip<12:10>) for clock fail in ipc8 interrupt register ? interrupt subpriority control bits (fscmip<9:8>) for clock fail in ipc8 interrupt register the following tables provide brief summaries of oscillator-module-related registers. corresponding registers appear after the summaries, followed by a detailed description of each register. table 4-2: watchdog timer sfr summary (1) table 4-1: oscillator sfr summary virtual address name bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/ 4 bit 27/19/11/ 3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 bf80_f000 osccon 31:24 ? ? pllodiv<2:0> frcdiv<2:0> 23:16 ? soscrdy ? pbdiv<1:0> pllmult<2:0> 15:8 ? cosc<2:0> ? nosc<2:0> 7:0 clklock ulock lock slpen cf ufrcen soscen oswen bf80_f004 oscconclr 31:0 write clears selected bits in osccon, read yields undefined value bf80_f008 oscconset 31:0 write sets selected bits in osccon, read yields undefined value bf80_f00c oscconinv 31:0 write inverts selected bits in osccon, read yields undefined value bf80_f010 osctun 31:24 ? ? ? ? ? ? ? ? 23:16 ? ? ? ? ? ? ? ? 15:8 ? ? ? ? ? ? ? ? 7:0 ? ? tun<5:0> bf80_f014 osctunclr 31:0 write clears selected bits in osctun, read yields undefined value bf80_f018 osctunset 31:0 write sets selected bits in osctun, read yields undefined value bf80_f01c osctuninv 31:0 write inverts selected bits in osctun, read yields undefined value virtual address name bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/ 4 bit 27/19/11/ 3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 bf80_0000 wdtcon 15:8 on ? ? ? ? ? ? ? note 1: this summary table contains partial register definitions t hat only pertain to the oscillator peripheral. refer to the ? pic32mx family reference manual ? (ds61132) for a detailed description of these registers.
pic32mx3xx/4xx ds61143e-page 56 preliminary ? 2008 microchip technology inc. table 4-3: oscillator interrupt register summary (1) virtual address name bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 bf88_1070 iec1 15:8 rtccie fscmie i2c2mie i2c2sie i2c2bie u2txie u2rxie u2eie bf88_1040 ifs1 15:8 rtccif fscmif i2c2mif i2c2sif i2c2bif u2txif u2rxif u2eif bf88_1110 ipc8 23:16 ? ? ? fscmip<2:0> fscmis<1:0> note 1: this summary table contains partial register definitions t hat only pertain to the oscillator peripheral. refer to the ?pic32mx family reference manual? (ds61132) for a detailed description of these registers. table 4-4: devcfg: device co nfiguration register summary (1, 2) virtual address name bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 bfc0_2ff8 devcfg1 23:16 fwdten ? ? fwdtps<4:0> 15:8 fcksm<1:0> fpbdiv<1:0> ?osciofnc poscmd<1:0> 7:0 ieso ? fsoscen ? ?fnosc<2:0> bfc0_2ff4 devcfg2 23:16 ? ? ? ? ? fpllodiv<2:0> 15:8 fupllen ? ? ? ? fupllidiv<2:0> 7:0 ? fpllmult<2:0> ? fpllidiv<2:0> note 1: fupllen and fpllodiv<2:0> are only available on pic32mx4xx family variants. 2: this summary table contains partial register definitions t hat only pertain to the oscillator peripheral. refer to the ?pic32mx family reference manual? (ds61132) for a detailed description of these registers.
? 2008 microchip technology inc. preliminary ds61143e-page 57 pic32mx3xx/4xx register 4-1: osccon: os cillator control register r-x r-x r/w-x r/w-x r/w-x r/w-0 r/w-0 r/w-1 ? ? pllodiv<2:0> frcdiv<2:0> bit 31 bit 24 r-x r-0 r-x r/w-x r/w-x r/w-x r/w-x r/w-x ? soscrdy ? pbdiv<1:0> pllmult<2:0> bit 23 bit 16 r-x r-0 r-0 r-0 r-x r/w-x r/w-x r/w-x ?cosc<2:0> ?nosc<2:0> bit 15 bit 8 r/w-0 r-0 r-0 r/w-0 r/w-0 r/w-0 r/w-x r/w-x clklock ulock lock slpen cf ufrcen soscen oswen bit 7 bit 0 legend: r = readable bit w = writable bit p = programmable bit r = reserved bit u = unimplemented bit -n = bit value at por: (?0?, ?1?, x = unknown) bit 31-30 reserved: write ? 0 ?; ignore read bit 29-27 pllodiv<2:0>: output divider for pll 111 = pll output divided by 256 110 = pll output divided by 64 101 = pll output divided by 32 100 = pll output divided by 16 011 = pll output divided by 8 010 = pll output divided by 4 001 = pll output divided by 2 000 = pll output divided by 1 note: on reset these bits are set to the value of the fpllodiv configuration bits (devcfg2<18:16>) bit 26-24 frcdiv<2:0>: fast internal rc clock divider bits 111 = frc divided by 256 110 = frc divided by 64 101 = frc divided by 32 100 = frc divided by 16 011 = frc divided by 8 010 = frc divided by 4 001 = frc divided by 2 (default setting) 000 = frc divided by 1 bit 23 reserved: write ? 0 ?; ignore read bit 22 soscrdy: secondary oscillator ready indicator bit 1 = indicates that the secondary oscillator is running and is stable 0 = secondary oscillator is either turned off or is still warming up bit 21 reserved: write ? 0 ?; ignore read
pic32mx3xx/4xx ds61143e-page 58 preliminary ? 2008 microchip technology inc. bit 20-19 pbdiv<1:0>: peripheral bus clock divisor 11 = pbclk is sysclk divided by 8 (default) 10 = pbclk is sysclk divided by 4 01 = pbclk is sysclk divided by 2 00 = pbclk is sysclk divided by 1 note: on reset these bits are set to the value of the fpbdiv configuration bits (devcfg1<13:12>). bit 18-16 pllmult<2:0>: pll multiplier bits 111 = clock is multiplied by 24 110 = clock is multiplied by 21 101 = clock is multiplied by 20 100 = clock is multiplied by 19 011 = clock is multiplied by 18 010 = clock is multiplied by 17 001 = clock is multiplied by 16 000 = clock is multiplied by 15 note: on reset these bits are set to the value of the fpllmult configuration bits (devcfg2<6:4>). bit 15 reserved: write ? 0 ?; ignore read bit 14-12 cosc<2:0>: current oscillator selection bits 111 = fast internal rc oscillator divided by osccon bits 110 = fast internal rc oscillator divided by 16 101 = low-power internal rc oscillator (lprc) 100 = secondary oscillator (sosc) 011 = primary oscillator with pll module (xtpll, hspll or ecpll) 010 = primary oscillator (xt, hs or ec) 001 = fast rc oscillator with pll module divided by 2 (frcpll) 000 = fast rc oscillator (frc) note: on reset these bits are set to the value of the fnosc configuration bits (devcfg1<2:0>). bit 11 reserved: write ? 0 ?; ignore read bit 10-8 nosc<2:0>: new oscillator selection bits 111 = fast internal rc oscillator divided by osccon bits 110 = fast internal rc oscillator divided by 16 101 = low-power internal rc oscillator (lprc) 100 = secondary oscillator (sosc) 011 = primary oscillator with pll module (xtpll, hspll or ecpll) 010 = primary oscillator (xt, hs or ec) 001 = fast internal rc oscillator with pll module via postscaler (frcpll) 000 = fast internal rc oscillator (frc) note: on reset these bits are set to the value of the fnosc configuration bits (devcfg1<2:0>). bit 7 clklock: clock selection lock enable bit if fscm is enabled (fcksm1 = 1 ): 1 = clock and pll selections are locked. 0 = clock and pll selections are not locked and may be modified if fscm is disabled (fcksm1 = 0 ): note: clock and pll selections are never locked and may be modified. bit 6 ulock: usb pll lock status bit 1 = indicates that the usb pll module is in lock or usb pll module start-up timer is satisfied 0 = indicates that the usb pll module is out of lock or usb pll module start-up timer is in progress or usb pll is disabled bit 5 lock: pll lock status bit 1 = pll module is in lock or pll module start-up timer is satisfied 0 = pll module is out of lock, pll start-up timer is running or pll is disabled register 4-1: osccon: os cillator control register
? 2008 microchip technology inc. preliminary ds61143e-page 59 pic32mx3xx/4xx bit 4 slpen: sleep mode enable bit 1 = device will enter sleep mode when a wait instruction is executed 0 = device will enter idle mode when a wait instruction is executed bit 3 cf: clock fail detect bit 1 = fscm (fail safe clock monitor) has detected a clock failure 0 = no clock failure has been detected bit 2 ufrcen: usb frc clock enable bit 1 = enable frc as the clock source for the usb clock source 0 = use the primary oscillator or usb pll as the usb clock source bit 1 soscen: 32.768 khz secondary oscillator (sosc) enable bit 1 = enable secondary oscillator 0 = disable secondary oscillator note: on reset these bits are set to the value of the fsoscen configuration bit (devcfg1<5>). bit 0 oswen: oscillator switch enable bit 1 = initiate an oscillator switch to selection specified by nosc2:nosc0 bits 0 = oscillator switch is complete register 4-1: osccon: os cillator control register
pic32mx3xx/4xx ds61143e-page 60 preliminary ? 2008 microchip technology inc. register 4-2: osctun: frc tuning register r-x r-x r-x r-x r-x r-x r-x r-x ? ? ? ? ? ? ? ? bit 31 bit 24 r-x r-x r-x r-x r-x r-x r-x r-x ? ? ? ? ? ? ? ? bit 23 bit 16 r-x r-x r-x r-x r-x r-x r-x r-x ? ? ? ? ? ? ? ? bit 15 bit 8 r-x r-x r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? tun<5:0> bit 7 bit 0 legend: r = readable bit w = writable bit p = programmable bit r = reserved bit u = unimplemented bit -n = bit value at por: (?0?, ?1?, x = unknown) bit 31:6 reserved: write ? 0 ?; ignore read bit 5-0 tun<5:0>: frc oscillator tuning bits 011111 = maximum frequency. 011110 = ? 000001 = 000000 = center frequency. oscillator runs at calibrated frequency. 111111 = ? 100001 = 100000 = minimum frequency.
? 2008 microchip technology inc. preliminary ds61143e-page 61 pic32mx3xx/4xx register 4-3: wdtcon: wat chdog timer control register r-x r-x r-x r-x r-x r-x r-x r-x ? ? ? ? ? ? ? ? bit 31 bit 24 r-x r-x r-x r-x r-x r-x r-x r-x ? ? ? ? ? ? ? ? bit 23 bit 16 r/w-0 r-x r-x r-x r-x r-1 r-1 r-0 on ? ? ? ? ? ? ? bit 15 bit 8 r-x r-x r-x r-x r-x r-x r-0 r/w-0 ? wdtps<4:0> ? wdtclr bit 7 bit 0 legend: r = readable bit w = writable bit p = programmable bit r = reserved bit u = unimplemented bit -n = bit value at por: (?0?, ?1?, x = unknown) bit 15 on: watchdog timer enable bit 1 = enables the wdt if it is not enabled by the device configuration 0 = disable the wdt if it was enabled in software notes: a read of this bit will result in a ? 1 ? if the wdt is enabled by the device configuration or by software. the lprc oscillator will automatically be enabled when this bit is set. note: shaded bit names in this register control other pic32mx3xx/4xx peripherals and are not related to the oscillator.
pic32mx3xx/4xx ds61143e-page 62 preliminary ? 2008 microchip technology inc. register 4-4: iec1: interrupt enable control register r-x r-x r-x r-x r-x r-x r/w-0 r/w-0 ? ? ? ? ? ? usbie fceie bit 31 bit 24 r-0 r-0 r-0 r-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ? ? dma3ie dma2ie dma1ie dma0ie bit 23 bit 16 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 rtccie fscmie i2c2mie i2c2sie i2c2bie u2txie u2rxie u2eie bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 spi2rxie spi2txie spi2eie cmp2ie cmp1ie pmpie ad1ie cnie bit 7 bit 0 legend: r = readable bit w = writable bit p = programmable bit r = reserved bit u = unimplemented bit -n = bit value at por: (?0?, ?1?, x = unknown) bit 14 fscmie: fail-safe clock monitor interrupt enable bit 1 = interrupt is enabled 0 = interrupt is disabled note: shaded bit names in this interrupt register control other pic32mx3xx/4xx peripherals and are not related to the oscillator.
? 2008 microchip technology inc. preliminary ds61143e-page 63 pic32mx3xx/4xx register 4-5: ifs1: interrupt flag status register r-x r-x r-x r-x r-x r-x r/w-0 r/w-0 ? ? ? ? ? ? usbif fceif bit 31 bit 24 r-0 r-0 r-0 r-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ? ? dma3if dma2if dma1if dma0if bit 23 bit 16 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 rtccif fscmif i2c2mif i2c2sif i2c2bif u2txif u2rxif u2eif bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 spi2rxif spi2txif spi2eif cmp2if cmp1if pmpif ad1if cnif bit 7 bit 0 legend: r = readable bit w = writable bit p = programmable bit r = reserved bit u = unimplemented bit -n = bit value at por: (?0?, ?1?, x = unknown) bit 14 fscmif: fail-safe clock monitor interrupt flag bit 1 = interrupt request has occured 0 = no interrupt request has occurred note: shaded bit names in this interrupt register control other pic32mx3xx/4xx peripherals and are not related to the oscillator.
pic32mx3xx/4xx ds61143e-page 64 preliminary ? 2008 microchip technology inc. register 4-6: ipc8: interrupt pr iority control register 8 r-x r-x r-x r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ? dma0ip<2:0> dma0is<1:0> bit 31 bit 24 r-x r-x r-x r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ? rtccip<2:0> rtccis<1:0> bit 23 bit 16 r-x r-x r-x r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ? fscmip<2:0> fscmis<1:0> bit 15 bit 8 r-x r-x r-x r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ? i2c2ip<2:0> i2c2is<1:0> bit 7 bit 0 legend: r = readable bit w = writable bit p = programmable bit r = reserved bit u = unimplemented bit -n = bit value at por: (?0?, ?1?, x = unknown) bit 12-10 fscmip<2:0>: fail-safe clock monitor interrupt priority bits 111 = interrupt priority is 7 110 = interrupt priority is 6 101 = interrupt priority is 5 100 = interrupt priority is 4 011 = interrupt priority is 3 010 = interrupt priority is 2 001 = interrupt priority is 1 000 = interrupt is disabled bit 9-8 fscmis<1:0>: fail-safe clock monitor interrupt subpriority bits 11 = interrupt subpriority is 3 10 = interrupt subpriority is 2 01 = interrupt subpriority is 1 00 = interrupt subpriority is 0 note: shaded bit names in this interrupt register control other pic32mx3xx/4xx peripherals and are not related to the oscillator.
? 2008 microchip technology inc. preliminary ds61143e-page 65 pic32mx3xx/4xx register 4-7: devcfg1 b oot configuration register r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 ? ? ? ? ? ? ? ? bit 31 bit 24 r/p-1 r/p-1 r-1 r/p-1 r/p-1 r/p-1 r/p-1 r/p-1 fwdten ? ? fwdtps4 fwdtps3 fwdtps2 fwdtps1 fwdtps0 bit 23 bit 16 r/p-1 r/p-1 r/p-1 r/p-1 r-1 r/p-1 r/p-1 r/p-1 fcksm<1:0> fpbdiv<1:0> ? osciofnc poscmd<1:0> bit 15 bit 8 r/p-1 r-1 r/p-1 r-1 r-1 r/p-1 r/p-1 r/p-1 ieso ? fsoscen ? ? fnosc2 fnosc1 fnosc0 bit 7 bit 0 legend: r = readable bit w = writable bit p = programmable bit r = reserved bit u = unimplemented bit -n = bit value at por: (?0?, ?1?, x = unknown) bit 15-14 fcksm<1:0>: fail-safe clock monitor (fscm) and clock switch configuration bits 1x = fscm and clock switching are disabled 01 = clock switching is enabled, fscm is disabled 00 = clock switching and fscm are enabled bit 13-12 fpbdiv<1:0>: peripheral bus clock divisor default value 11 = pbclk is sysclk divided by 8 10 = pbclk is sysclk divided by 4 01 = pbclk is sysclk divided by 2 00 = pbclk is sysclk divided by 1 bit 10 osciofnc: clko enable configuration bit 1 = clko output signal active on the osco pin; primary oscillator must be disabled or configured for the external clock mode (ec) for the clko to be active (poscmd<1:0> = 11 or = 00 ) 0 = clko output disabled bit 9-8 poscmd<1:0>: primary oscillator configuration bits 11 = primary oscillator disabled 10 = hs mode 01 = xt mode 00 = ec mode bit 7 ieso: internal external clock switchover select bit 1 = internal external clock switchover mode enabled; two-speed start-up mode 0 = internal external clock switchover mode disabled; single-speed start-up mode bit 5 fsoscen: secondary oscillator enable bit 1 = enable secondary oscillator 0 = disable secondary oscillator
pic32mx3xx/4xx ds61143e-page 66 preliminary ? 2008 microchip technology inc. bit 2-0 fnosc<2:0>: cpu clock oscillator select bits 111 = fast rc oscillator with divide-by-n (frcdiv) 110 = frc divided by 16 (frcdiv16) 101 = low-power rc oscillator (lprc) 100 = secondary oscillator (sosc) 011 = primary oscillator with pll (xtpll, hspll, or ecpll) 010 = primary oscillator without pll (xt, hs, or ec) 001 = fast rc oscillator with pll 000 = fast rc oscillator (frc) register 4-7: devcfg1 b oot configuration register
? 2008 microchip technology inc. preliminary ds61143e-page 67 pic32mx3xx/4xx register 4-8: devcfg2 b oot configuration register r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 ? ? ? ? ? ? ? ? bit 31 bit 24 r-1 r-1 r-1 r-1 r-1 r/p-1 r/p-1 r/p-1 ? ? ? ? ? fpllodiv<2:0> bit 23 bit 16 r/p-1 r-1 r-1 r-1 r-1 r/p-1 r/p-1 r/p-1 fupllen ? ? ? ? fupllidiv<2:0> bit 15 bit 8 r-x r/p-1 r/p-1 r/p-1 r-x r/p-1 r/p-1 r/p-1 ? fpllmult<2:0> ? fpllidiv<2:0> bit 7 bit 0 legend: r = readable bit w = writable bit p = programmable bit r = reserved bit u = unimplemented bit -n = bit value at por: (?0?, ?1?, x = unknown) bit 18-16 fpllodiv<2:0>: default postscaler for pll. 111 = pll output divided by 256 110 = pll output divided by 64 101 = pll output divided by 32 100 = pll output divided by 16 011 = pll output divided by 8 010 = pll output divided by 4 001 = pll output divided by 2 000 = pll output divided by 1 (default setting) bit 15 fupllen: usb pll enable bit 00 = enable usb pll 00 = disable and bypass usb pll bit 10-8 fupllidiv<2:0>: pll input divider bits 000 = 1x divider 001 = 2x divider 010 = 3x divider 011 = 4x divider 100 = 5x divider 101 = 6x divider 110 = 10x divider 111 = 12x divider bit 6-4 fpllmult<2:0>: default pll multiplier value bits 111 = 24x multiplier 110 = 21x multiplier 101 = 20x multiplier 100 = 19x multiplier 011 = 18x multiplier 010 = 17x multiplier 001 = 16x multiplier 000 = 15x multiplier
pic32mx3xx/4xx ds61143e-page 68 preliminary ? 2008 microchip technology inc. bit 2-0 fpllidiv<2:0>: default pll input divider value bits 111 = divide by 12 110 = divide by 10 101 = divide by 6 100 = divide by 5 011 = divide by 4 010 = divide by 3 001 = divide by 2 000 = divide by 1 register 4-8: devcfg2 b oot configuration register
? 2008 microchip technology inc. preliminary ds61143e-page 69 pic32mx3xx/4xx 4.2 operation: clock generation and clock sources the pic32mx3xx/4xx device has two internal clocks: cpu clock and pb clock. they are derived from the currently selected clock source. the clock source can be chosen from the 4 available internal or external clock sources. some of these clock sources have phase locked loops (plls), programmable output dividers, or input dividers to scale the input frequency to suit the application. the clock source can be changed on-the-fly by software. the oscillator control register is locked by hardware, it must be unlocked by a series of writes before software can perform a clock switch. there are three main clocks in the pic32mx3xx/4xx device: ? the system clock (sysclk) used by cpu and some peripherals ? the peripheral bus clock (pbclk) used by most peripherals ? the usb clock (usbclk) used by usb peripheral the pic32mx3xx/4xx clocks are derived from one of the following sources: ? primary oscillator (posc) on the osci and osco pins ? secondary oscillator (sosc) on the sosci and sosco pins ? internal fast rc oscillator (frc) ? internal low-power rc oscillator (lprc) each of the clock sources has unique configurable options, such as a pll, input divider and/or output divider, that are detailed in their respective sections. there are up to four internal clocks, depending on the specific device. the clocks are derived from the currently selected oscillator source. note: clock sources for peripherals that use external clocks, such as the rtcc and timer 1, are covered in their respective sections.
pic32mx3xx/4xx ds61143e-page 70 preliminary ? 2008 microchip technology inc. 4.2.1 system clock (sysclk) generation the sysclk is the primary clock used by the cpu and select peripherals such as dma, interrupt controller, and prefetch cache. the sysclk is derived from one of the four clock sources: posc, sosc, frc, or lprc. some of the clock sources have specific clock multipliers and/or divider options. no clock scaling is applied other than the user specified values. the sysclk source is selected by the device configuration and can be changed by software during operation. the ability to switch clock sources during operation allows the application to reduce power consumption by reduc- ing the clock speed. refer to table 4-5 for a list of sys- clk sources. table 4-5: clock selectio n configuration bit values oscillator mode oscillator source poscmd<1:0> fnosc2: fnosc0 notes fast rc oscillator with postscaler (frcdiv) internal xx 111 1, 2 fast rc oscillator divided by 16 (frcdiv16) internal xx 110 1 low-power rc oscillator (lprc) internal xx 101 1 secondary (timer1/rtcc) oscillator (sosc) secondary xx 100 1 primary oscillator (hs) with pll module (hspll) primary 10 011 3 primary oscillator (xt) with pll module (xtpll) primary 01 011 3 primary oscillator (ec) with pll module (ecpll) primary 00 011 3 primary oscillator (hs) primary 10 010 primary oscillator (xt) primary 01 010 primary oscillator (ec) primary 00 010 fast rc oscillator with pll module (frcpll) internal 10 001 1,4 fast rc oscillator (frc) internal xx 000 1 note 1: osco pin function as pbclk out or digital i/o is determined by the osciofnc configuration bit. when the pin is not required by the oscillator mode it may be configured for one of these noted options. 2: default oscillator mode for an unprogrammed (erased) device. 3: when using the pll modes the input divider must be chosen such that resulting frequency applied to the pll is in the range of 4 mhz to 5 mhz. 4: in this mode, the pll input divider is forced to ?2? to provide a 4 mhz input to the pll. this parameter cannot be modified and satisfies the requirements described in note 3.
? 2008 microchip technology inc. preliminary ds61143e-page 71 pic32mx3xx/4xx 4.2.1.1 primary oscillator (posc) the posc has six operating modes, as summarized in table 4-6. the first three modes can each be combined with a pll module to form the last three modes. figure 4-2, figure 4-3, and figure 4-4 show various posc configurations. the primary oscillator is con- nected to the osci and osco pins of the device fam- ily. the primary oscillator can be configured for an external clock input, or an external crystal or resonator. the xt, xtpll, hs, and hspll modes are external crystal or resonator controller oscillator modes. the xt and hs modes are functionally very similar. the pri- mary difference is the gain of the internal inverter of the oscillator circuit (see figure 4-2). the xt mode is a medium-power, medium-frequency mode and has medium inverter gain. hs mode is higher power and provides the highest oscillator frequencies and has the highest inverter gain. osco provides crystal/resonator feedback in both xt and hs oscillator modes and hence is not available for use as a input or output in these modes. the xtpll and hspll modes have a phase locked loop (pll) with user selectable input divider, multiplier, and output divider to provide a wide range of output frequencies. the oscillator circuit will consume more current when the pll is enabled. the external clock modes, ec and ecpll, allow the system clock to be derived from an external clock source. these modes configure the osci pin as a high-impedance input that can be driven by a cmos driver. the external clock can be used to drive the sys- tem clock directly (ec) or the ecpll module with pres- cale and postscaler can be used to change the input clock frequency (ecpll). the external clock modes also disable the internal feedback buffer, allowing the osco pin to be used for other functions. in external clock mode, the osco pin can be used as an addi- tional device i/o pin (see figure 4-4) or as a pbclk output pin (see figure 4-3). table 4-6: primary oscillator operating modes figure 4-2: crystal or ceramic resonator operation (xt, xtpll, hs, or hspll oscillator mode) note: when using pll modes, the input divider must be chosen such that the resulting frequency applied to the pll is in the range of 4 mhz to 5 mhz. oscillator mode description hs 10 mhz-40 mhz crystal xt 3.5 mhz-10 mhz resonator ec external clock input (0-80 mhz) hspll 10 mhz-40 mhz crystal, pll enabled xtpll 4 mhz-10 mhz resonator, pll enabled ecpll external clock input (5-80 mhz), pll enabled note: the clock applied to the cpu after applicable prescalers, postscalers, and pll multipliers must not exceed the maximum allowable processor frequency. c1 (3) c2 (3) xtal osco r s (1) osci r f (2) enable to internal logic pic32mx3xx/4xx note 1: a series resistor, rs, may be required for at strip cut crystals. 2: the internal feedback resistor, r f , is typically in the range of 2 to 10 m . 3: refer to the ? pic32mx family reference manual ? (ds61132) for help determining the best oscillator components.
pic32mx3xx/4xx ds61143e-page 72 preliminary ? 2008 microchip technology inc. figure 4-3: extern al clock input operation with clock-out (ec, ecpll mode) figure 4-4: extern al clock input operation with no clock-out (ec or ecpll mode) 4.2.1.2 primary oscillator (posc) configuration to configure the posc, the following steps should be performed: 1. select posc as the default oscillator in the device configuration register, devcfg1, by setting fnosc<2:0> = 010 , without pll; or fnosc<2:0> = 011 , with pll. 2. select the desired mode (hs, xt, or ec), using poscmd<1:0> in the devcfg1 register. 3. if the pll is to be used: a) select the appropriate configuration bits for the pll input divider to scale the input frequency to be between 4 mhz and 5 mhz using fpllidiv<2:0> in the devcfg2 register. b) select the desired pll multiplier ratio using fpllmult<2:0> in the devcfg2 register. c) at runtime, select the desired pll output divider using osccon<29:27> in the pllodiv register to provide the desired clock frequency. the default value is set by the devcfg1 register. 4.2.1.3 oscillator start-up timer in order to ensure that a crystal oscillator (or ceramic resonator) has started and stabilized, an oscillator start-up timer (ost) is provided. the ost is a simple 10-bit counter that counts 1024 t osc cycles before releasing the oscillator clock to the rest of the system. this time-out period is designated as t ost . the ampli- tude of the oscillator signal must reach the v il and v ih thresholds for the oscillator pins before the ost can begin to count cycles. the t ost interval is required every time the oscillator has to restart (i.e., on por, bor and wake-up from sleep mode). the oscillator start-up timer is applied to the xt and hs modes for the primary oscillator, as well as the secondary oscillator, see section 4.2.1.5 ?sec- ondary oscillator (sosc)? . osci osco (clock out) pbclk clock from ext. system pic32mx3xx/4xx osci i/o (osco) i/o clock from ext. system pic32mx3xx/4xx
? 2008 microchip technology inc. preliminary ds61143e-page 73 pic32mx3xx/4xx 4.2.1.4 system clock phase locked loop (pll) the system clock pll provides a user configurable input divider, multiplier, and output divider which can be used with the xt, hs and ec primary oscillator modes and with the internal fast rc oscillator (frc) mode to create a variety of clock frequencies from a single clock source. the input divider, multiplier, and output divider control initial value bits are contained in the in the devcfg2 device configuration register. the multiplier and output divider bits are also contained in the osccon register. as part of a device reset, values from the device con- figuration register, devcfg2, are copied to the osccon register. this allows the user to preset the input divider to provide the appropriate input frequency to the pll and set an initial pll multiplier when pro- gramming the device. at runtime the multiplier, divider and output divider can be changed by software to scale the clock frequency to suit the application. the pll input divider cannot be changed at run time. this is to prevent applying an input frequency outside the speci- fied limits to the pll. to configure the pll the following steps are required: 1. calculate the pll input divider, pll multiplier, and pll output divider values. 2. set the pll input divider and the initial pll mul- tiplier value in the devcfg2 register when pro- gramming the part. 3. at runtime the pll multiplier and pll output divider can be changed to suit the application. combinations of pll input divider, multiplier and output divider provide a combined multiplier of approximately 0.006 to 24 times the input frequency. for reliable oper- ation the output of the pll module must not exceed the maximum clock frequency of the device. the pll input divider value should be chosen to limit the input fre- quency to the pll to the range of 4 mhz to 5 mhz. due to the time required for the pll to provide a stable output, a status bit lock (osccon<5>) is provided. when the clock input to the pll is changed, this bit is driven low (? 0 ?). after the pll has achieved a lock or the pll start-up timer has expired, the bit is set. the bit will be set upon the expiration of the timer even if the pll has not achieved a lock.
pic32mx3xx/4xx ds61143e-page 74 preliminary ? 2008 microchip technology inc. table 4-7: net multiplier output for selected pll and output divider values multiplier postscaler net multiplication factor pllodiv <2:0> pllmult <2:0> multiplier postscaler net multiplication factor pllodiv <2:0> pllmult <2:0> 15 1 15 ? 000 ?? 000 ? 15 16 .938 ? 100 ?? 000 ? 16 1 16 ? 000 ? ? 001 ? 16 16 1 ? 100 ? ? 001 ? 17 1 17 ? 000 ? ? 010 ? 17 16 1.063 ? 100 ? ? 010 ? 18 1 18 ? 000 ? ? 011 ? 18 16 1.125 ? 100 ? ? 011 ? 19 1 19 ? 000 ? ? 100 ? 19 16 1.188 ? 100 ? ? 100 ? 20 1 20 ? 000 ? ? 101 ? 20 16 1.250 ? 100 ? ? 101 ? 21 1 21 ? 000 ? ? 110 ? 21 16 1.313 ? 100 ? ? 110 ? 24 1 24 ? 000 ? ? 111 ? 24 16 1.5 ? 100 ? ? 111 ? 15 2 7.5 ? 001 ?? 000 ? 15 32 .4688 ? 101 ? ? 000 ? 16 2 8 ? 001 ? ? 001 ? 16 32 .5 ? 101 ?? 001 ? 17 2 8.5 ? 001 ? ? 010 ? 17 32 .5313 ? 101 ?? 010 ? 18 2 9 ? 001 ? ? 011 ? 18 32 .5625 ? 101 ?? 011 ? 19 2 9.5 ? 001 ? ? 100 ? 19 32 .5938 ? 101 ?? 100 ? 20 2 10 ? 001 ? ? 101 ? 20 32 .6250 ? 101 ?? 101 ? 21 2 10.5 ? 001 ? ? 110 ? 21 32 .6563 ? 101 ?? 110 ? 24 2 12 ? 001 ? ? 111 ? 24 32 .7500 ? 101 ?? 111 ? 15 43.75? 010 ? ? 000 ? 15 64 .234 ? 110 ? ? 000 ? 16 4 4 ? 010 ?? 001 ? 16 64 .250 ? 110 ?? 001 ? 17 4 4.25 ? 010 ?? 010 ? 17 64 .266 ? 110 ?? 010 ? 18 4 4.5 ? 010 ?? 011 ? 18 64 .281 ? 110 ?? 011 ? 19 4 4.75 ? 010 ?? 100 ? 19 64 .297 ? 110 ?? 100 ? 20 4 5 ? 010 ?? 101 ? 20 64 .313 ? 110 ?? 101 ? 21 4 5.25 ? 010 ?? 110 ? 21 64 .328 ? 110 ?? 110 ? 24 4 6 ? 010 ?? 111 ? 24 64 .375 ? 110 ?? 111 ? 15 8 1.875 ? 011 ? ? 000 ? 15 256 .05859 ? 111 ? ? 000 ? 16 8 2 ? 011 ?? 001 ? 16 256 .06250 ? 111 ?? 001 ? 17 8 2.125 ? 011 ?? 010 ? 17 256 .06641 ? 111 ?? 010 ? 18 8 2.250 ? 011 ?? 011 ? 18 256 .07031 ? 111 ?? 011 ? 19 8 2.375 ? 011 ?? 100 ? 19 256 .07422 ? 111 ?? 100 ? 20 8 2.5 ? 011 ?? 101 ? 20 256 .07813 ? 111 ?? 101 ? 21 8 2.625 ? 011 ?? 110 ? 21 256 .08203 ? 111 ?? 110 ? 24 8 3 ? 011 ?? 111 ? 24 256 .09375 ? 111 ?? 111 ?
? 2008 microchip technology inc. preliminary ds61143e-page 75 pic32mx3xx/4xx 4.2.1.4.1 pll lock status the lock bit (osccon<5>) is a read-only status bit that indicates the lock status of the pll. it is automati- cally set after the typical time delay for the pll to achieve lock, also designated as t lock . if the pll does not stabilize properly during start-up, lock may not reflect the actual status of pll lock, nor does it detect when the pll loses lock during normal opera- tion. the lock bit is cleared at a power-on reset and on clock switches when the pll is selected as a destina- tion clock source. it remains clear when any clock source not using the pll is selected. refer to the electrical characteristics section in the specific device data sheet for further information on the pll lock interval. 4.2.1.4.2 usb pll lock status the ulock bit (osccon<6>) is a read-only status bit that indicates the lock status of the usb pll. it is auto- matically set after the typical time delay for the pll to achieve lock, also designated as t lock . if the pll does not stabilize properly during start-up, lock may not reflect the actual status of pll lock, nor does it detect when the pll loses lock during normal opera- tion. the ulock bit is cleared at a power-on reset. it remains clear when any clock source not using the pll is selected. refer to the electrical characteristics section in the specific device data sheet for further information on the pll lock interval. 4.2.1.4.3 primary oscillator start-up from sleep mode to ensure reliable wake-up from sleep, care must be taken to properly design the primary oscillator circuit. this is because the load capacitors have both partially charged to some quiescent value and phase differential at wake-up is minimal. thus, more time is required to achieve stable oscillation. remember also that low- voltage, high temperatures and the lower frequency clock modes also impose limitations on loop gain, which in turn, affects start-up. each of the following factors increases the start-up time: ? low-frequency design (with a low gain clock mode) ? quiet environment (such as a battery operated device) ? operating in a shielded box (away from the noisy rf area) ? low voltage ? high temperature ? wake-up from sleep mode 4.2.1.5 secondary oscillator (sosc) the secondary oscillator (sosc) is designed specifi- cally for low-power operation with a external 32.768 khz crystal. the oscillator is located on the sosco and sosci device pins and serves as a sec- ondary crystal clock source for low-power operation. it can also drive timer1 and/or the real-time clock/cal- endar module for real-time clock applications. 4.2.1.5.1 enabling the sosc oscillator the sosc is hardware enabled by the fsoscen configuration bit (devcfg1<5>). once sosc is enabled, software can control it by modifying soscen bit (osccon<1>). setting soscen enables the oscil- lator; the sosco and sosci pins are controlled by the oscillator and cannot be used for port i/o or other func- tions. the secondary oscillator requires a warm-up period before it can be used as a clock source. when the oscil- lator is enabled, a warm-up counter increments to 1024. when the counter expires the soscrdy (osccon<22>) is set to ? 1 ?. 4.2.1.5.2 sosc continuous operation the sosc is always enabled when soscen (osccon<1>) is set. leaving the oscillator running at all times allows a fast switch to the 32 khz system clock for lower power operation. returning to the faster main oscillator will still require an oscillator start-up time if it is a crystal type source and/or uses the pll. in addition, the oscillator will need to remain running at all times for real-time clock applications and may be required for timer1. note: an unlock sequence is required before a write to osccon can occur. refer to section 4.2.6.2 ?oscillator switching sequence? for more information.
pic32mx3xx/4xx ds61143e-page 76 preliminary ? 2008 microchip technology inc. example 4-1: enabling the sosc 4.2.1.6 internal fast rc oscillator (frc) the frc oscillator is a fast (8 mhz nominal), user trim- mable, internal rc oscillator with user selectable input divider, pll multiplier, and output divider. 4.2.1.6.1 frc postscaler mode (frcdiv) users are not limited to the nominal 8 mhz frc output if they wish to use the fast internal oscillator as a clock source. an additional frc mode, frcdiv, implements a selectable output divider that allows the choice of a lower clock frequency from 7 different options, plus the direct 8 mhz output. the output divider is configured using the frcdiv<2:0> bits (osccon<26:24>). assuming a nominal 8 mhz output, available lower fre- quency options range from 4 mhz (divide-by-2) to 31 khz (divide-by-256). the range of frequencies allows users the ability to save power at any time in an application by simply changing the frcdiv bits. the frcdiv mode is selected whenever the cosc bits (osccon<14:12>) are ? 111 ?. 4.2.1.6.2 frc oscillator with pll mode (frcpll) the output of the frc may also be combined with a user selectable pll multiplier and output divider to pro- duce a sysclk across a wide range of frequencies. the frc pll mode is selected whenever the cosc bits (osccon<14:12>) are ? 001 ?. the desired pll multiplier and output divider values can be chosen to provide the desired device frequency 4.2.1.6.3 oscillator tune register (osctun) the frc oscillator tuning register osctun allows the user to fine tune the frc oscillator over a range of approximately 12% (typical). each bit increment or decrement changes the factory calibrated frequency of the frc oscillator by a fixed amount. 4.2.1.7 internal low-power rc oscillator (lprc) the lprc oscillator is separate from the frc. it oscil- lates at a nominal frequency of 31.25 khz. the lprc oscillator is the clock source for the power-up timer (pwrt), watchdog timer (wdt), fail safe clock mon- itor (fscm) and pll reference circuits. it may also be used to provide a low-frequency clock source option for the device in those applications where power consumption is critical, and timing accuracy is not required. syskey = 0x12345678; // ensure osccon is locked syskey = 0xaa996655; // write key1 to syskey syskey = 0x556699aa; // write key2 to syskey // osccon is now unlocked // make the desired change oscconset = 2; // request clock switch // relock the syskey syskey = 0x12345678; // write any value other than key1 or key2 // osccon is relocked note: in this mode, the pll input divider is forced to ?2? to provide a 4 mhz input to the pll. this parameter cannot be modified.
? 2008 microchip technology inc. preliminary ds61143e-page 77 pic32mx3xx/4xx 4.2.1.7.1 enabling the lprc oscillator since it serves the pwrt clock source, the lprc oscillator is disabled at power-on reset whenever the on-board voltage regulator is enabled. after the pwrt expires, the lprc oscillator will remain on if any one of the following is true: ? the fail-safe clock monitor is enabled. ? the wdt is enabled. ? the lprc oscillator is selected as the system clock (cosc2:cosc0 = 100 ). if none of the above is true, the lprc will shut off after the pwrt expires. 4.2.2 peripheral bus clock (pbclk) generation the pbclk is derived from the system clock (sys- clk) divided by pbdiv<1:0> (osccon<20:19>). the pbclk divisor bits pbdiv<1:0> allow postscalers of 1:1, 1:2, 1:4, and 1:8. refer to the individual peripheral module section(s) for information regarding which bus a specific peripheral uses. 4.2.3 usb clock (usbclk) generation the usbclk can be derived from 8 mhz internal frc oscillator, 48 mhz posc, or 96 mhz pll from posc. for normal operation, the usb module requires exact 48 mhz clock. when using 96 mhz pll, the output is internally divided to obtain 48 mhz clock. the frc clock source is used to detect usb activity and bring usb module out of suspend mode. once usb mod- ule is out of suspend mode, it starts using any of two 48 mhz clock sources. the internal frc oscillator is not used for normal usb module operation. 4.2.3.0.1 usb clock phase locked loop (upll) the usb clock pll provides a user configurable input divider which can be used with the xt, hs and ec pri- mary oscillator modes and with the internal fast rc oscillator (frc) mode to create a variety of clock fre- quencies from a clock source. the actual source must be able to provide stable clock as required by the usb specifications. the upll enable and input divider bits are contained in the in the devcfg2 device configuration register. the input to the upll must be limited to 4 mhz only. appropriate input divider must be selected to ensure that the upll input is 4 mhz. to configure the upll the following steps are required: 1. enable usb pll by setting fupllen bit in devcfg2 register. 2. based on the source clock, calculate the upll input divider value such that the pll input is 4 mhz 3. set the upll input divider fupllidiv bits in the devcfg2 register when programming the part. 4.2.3.0.2 usb pll lock status the ulock bit (osccon<6>) is a read-only status bit that indicates the lock status of the usb pll. it is auto- matically set after the typical time delay for the pll to achieve lock, also designated as t ulock . if the pll does not stabilize properly during start-up, ulock may not reflect the actual status of pll lock, nor does it detect when the pll loses lock during normal opera- tion. the ulock bit is cleared at a power-on reset. it remains clear when any clock source not using the pll is selected. refer to the electrical characteristics section in the specific device data sheet for further information on the usb pll lock interval. notes: when the pbdiv divisor is set to a ratio of ?1:1? the sysclk and pbclk are equiva- lent in frequency. the pbclk frequency is never greater than the processor clock fre- quency. the effect of changing the pbclk fre- quency on individual peripherals should be taken into account when selecting or changing the pbdiv value. performing back-to-back operations on pbclk peripheral registers when the pb divisor is not set at 1:1 will cause the cpu to stall for a number of cycles. this stall occurs to prevent an operation from occur- ring before the pervious one has com- pleted. the length of the stall is determined by the ratio of the cpu and pbclk and synchronizing time between the two busses. changing the pbclk frequency has no effect on the sysclk peripherals operation.
pic32mx3xx/4xx ds61143e-page 78 preliminary ? 2008 microchip technology inc. 4.2.3.0.3 using internal frc oscillator with usb the internal 8 mhz frc oscillator is available as a clock source to detect any usb activity during usb suspend mode and bring the module out of the sus- pend mode. to enable frc for usb usage, the ufrcen bit (osccon<2>) must be set ? 1 ? before put- ting usb module to suspend mode. 4.2.4 two-speed start-up two-speed start-up mode can be used to reduce the device start-up latency when using all external crystal posc modes, including pll. two-speed start-up uses the frc clock as the sysclk source until the primary oscillator (posc) has stabilized. after the user selected oscillator has stabilized, the clock source will switch to posc. this allows the cpu to begin running code, at a lower speed, while the oscillator is stabiliz- ing. when the posc has met the start-up criteria an automatic clock switch occurs to switch to posc. this mode is enabled by the device configuration bits fcksm<1:0> (devcfg1<15:14>). two-speed start- up operates after a power-on reset (por) or exit from sleep. software can determine the oscillator source currently in use by reading the cosc<2:0> bits in the osccon register. 4.2.5 fail-safe clock monitor operation the fail-safe clock monitor (fscm) is designed to allow continued device operation if the current oscilla- tor fails. it is intended for use with the primary oscillator (posc) and automatically switches to the frc oscilla- tor if a posc failure is detected. the switch to the fast internal rc oscillator (frc) oscillator allows continued device operation and the ability to retry the posc or to execute code appropriate for a clock failure. the fscm mode is controlled by the fcksm<1:0> bits in the device configuration register, devcfg1. any of the posc modes can be used with fscm. when a clock failure is detected with fscm enabled and the fscm interrupt enable bit fscmie (iec1<14>) set, the clock source will be switched from posc to frc. an oscillator fail interrupt will be gen- erated, with the cf bit (osccon<3>) set. this inter- rupt has a user-settable priority fscmip<2:0> (ipc8<12:10>) and subpriority fscmis<1:0> (ipc8<9:8>). the clock source will remain frc until a device reset or a clock switch is performed. failure to enable the fscm interrupt will not inhibit the actual clock switch. the fscm module takes the following actions when switching to the frc oscillator: 1. the cosc bits (osccon<14:12>) are loaded with ? 000 ?. 2. the cf osccon<3> bit is set to indicate the clock failure 3. the oswen control bit (osccon<0>) is cleared to cancel any pending clock switches. to enable fscm the following steps should be performed: 1. enable the fscm in the device configuration register, devcfg1, by configuring the fcksm<1:0> bits to ? 00 ?. 01 = clock switching is enabled, fscm is disabled 00 = clock switching and fscm are enabled 2. select the desired mode hs, xt, or ec using fnosc<2:0> in devcfg1. 3. select posc as the default oscillator in the device configuration register, devcfg1 by configuring fnosc<2:0> = 010 without pll or 011 with pll. if the pll is to be used: 1. select the appropriate configuration bits for the pll input divider to scale the input fre- quency to be between 4 mhz and 5 mhz using fpllidiv<2:0> (devcfg2<2:0>). 2. select the desired pll multiplier using fpll- mult<2:0> (devcfg2<6:4>). 3. select the desired pll output divider using fpllodiv<2:0> (devcfg2<18:16>). if a fscm interrupt is desired when a fscm event occurs, the following steps should be performed during start-up code: 1. clear the fscm interrupt bit fscmif (ifs1<14>). 2. set the interrupt priority fscmip<2:0> (ipc8<12:10>) and subpriority fscmis<1:0> (ipc8<9:8>). 3. set the fscm interrupt enable bit fscmie (iec1<14>) note: the watchdog timer (wdt), if enabled, will continue to count at the same rate regardless of the sysclk frequency. care must be taken to service the wdt during two-speed start-up, taking into account the change in sysclk. note: when using frcpll mode, the pll input divider is forced to ?2? to provide a 4 mhz input to the pll. this parameter cannot be modified. note: the watchdog timer, if enabled, will con- tinue to count at the same rate regardless of the sysclk frequency. care must be taken to service the wdt after a fail-safe clock monitor event, taking into account the change in sysclk.
? 2008 microchip technology inc. preliminary ds61143e-page 79 pic32mx3xx/4xx 4.2.5.1 fscm delay on a por, bor or wake from sleep mode event, a nominal delay (t fscm ) may be inserted before the fscm begins to monitor the system clock source. refer to section 5.0 ?resets? for fscm delay timing information. the t fscm interval is applied whenever the fscm is enabled and the hs, hspll, xt, xtpll, or sosc oscillator modes are selected as the system clock. 4.2.5.2 fscm and slow oscillator start-up a slow oscillator start-up will not generate a fscm event. the fscm does not begin monitoring until the source to be monitored is running. if the oscillator does not start-up the device will not run due to the lack of a clock source. to detect the failure and prevent this the user should use two-speed start-up to allow the device to run using the frc oscillator while the posc oscillator starts up. the cosc<2:0> bits can then be polled to test for the clock switch to posc. refer to section 4.2.4 ?two-speed start-up? for further infor- mation. 4.2.5.3 fscm and slow clock sources use of the fscm with slow clock sources (below 100 khz) is not recommended. slow clock sources may cause the fscm to incorrectly detect a clock failure event. 4.2.5.4 fscm and wdt the fscm and the wdt both use the lprc oscillator as their time base. in the event of a clock failure, the wdt is unaffected and continues to run. 4.2.6 clock switching operation with few limitations, applications are free to switch between any of the four clock sources (posc, sosc, frc and lprc) under software control and at any time. to limit the possible side effects that could result from this flexibility, pic32mx3xx/4xx devices have a safeguard lock built into the switch process. 4.2.6.1 enabling clock switching to enable clock switching, the fcksm1 configuration bit (devcfg1<15>) must be programmed to ? 0 ?. if the fcksm1 configuration bit is unprogrammed (= 1 ), the clock switching function and fail-safe clock monitor function are disabled. this is the default setting. the nosc control bits (osccon<10:8>) do not con- trol the clock selection when clock switching is dis- abled. however, the cosc bits (osccon<14:12>) will reflect the clock source selected by the fnosc configuration bits. the oswen control bit (osccon<0>) has no effect when clock switching is disabled. it is held at ? 0 ? at all times. 4.2.6.2 oscillator switching sequence at a minimum, performing a clock switch requires the following sequence: 1. if desired, read the cosc<2:0> bits (osccon<14:12>) to determine the current oscillator source. 2. perform the unlock sequence to allow a write to the osccon register. the unlock sequence has critical timing requirements and should be performed with interrupts and dma disabled. 3. write the appropriate value to the nosc<2:0> control bits (osccon<10:8>) for the new oscillator source. 4. set the oswen bit (osccon<0>) to initiate the oscillator switch. 5. optionally perform the lock sequence to lock the osccon. the lock sequence must be per- formed separately from any other operation. once the basic sequence is completed, the system clock hardware responds automatically as follows: 1. the clock switching hardware compares the cosc<2:0> status bits with the new value of the nosc control bits. if they are the same, then the clock switch is a redundant operation. in this note: please refer to the electrical characteristics section for t fscm specification values. note: primary oscillator mode has three differ- ent submodes (xt, hs and ec) which are determined by the poscmd configura- tion bits in devcfg1. while an applica- tion can switch to and from primary oscillator mode in software, it cannot switch between the different primary sub- modes without reprogramming the device. note: the device does not prevent changing the pll postscaler or multiplier values on the clock source that is in use. the device will not permit direct switching between pll clock sources. the user should not change the pll multiplier values or post- scaler values when running from the affected pll source. to perform either of the above clock switching functions, the clock switch should be performed in two steps. the clock source should first be switched to a non-pll source, such as frc, and then switched to the desired source. this requirement only applies to pll-based clock sources.
pic32mx3xx/4xx ds61143e-page 80 preliminary ? 2008 microchip technology inc. case, the oswen bit is cleared automatically and the clock switch is aborted. 2. the new oscillator is turned on by the hardware if it is not currently running. if a crystal oscillator must be turned on, the hardware will wait until the oscillator start-up timer (ost) expires. if the new source is using the pll, then the hardware waits until a pll lock is detected (lock = 1 ). 3. the hardware clears the oswen bit to indicate a successful clock transition. in addition, the nosc bit values are transferred to the cosc status bits. 4. the old clock source is turned off at this time if the clock is not being used by any modules. the following is a recommended code sequence for a clock switch: 1. disable interrupts and dma prior to the system unlock sequence. 2. execute the system unlock sequence by writing the key values of 0xaa996655 and 0x556699aa to the syskey register in two back-to-back assembly or ?c? instructions. 3. write the new oscillator source value to the nosc control bits. 4. set the oswen bit in the osccon register to initiate the clock switch. 5. write a non-key value (such as 0x12345678) to the syskey register to perform a lock. con- tinue to execute code that is not clock-sensitive (optional). 6. check to see if oswen is ? 0 ?. if it is, the switch was successful. loop until the bit is ? 0 ?. 7. re-enable interrupts and dma. 4.2.6.3 clock switching considerations when incorporating clock switching into an application, users should keep certain things in mind when designing their code. ? the syslock unlock sequence is timing critical. the two key values must be written back-to-back with no in-between peripheral register access. to prevent unintended peripheral register accesses, it is recommended that all interrupts and dma transfers are disabled. ? the system will not relock automatically. the user should perform the relock sequence as soon after the clock switch as is possible. ? the unlock sequence unlocks other registers such as the those related to real-time clock control. ? if the destination clock source is a crystal oscilla- tor, the clock switch time will be dictated by the oscillator start-up time. ? if the new clock source does not start, or is not present, the oswen bit will remain set. ? a clock switch to a different frequency will affect the clocks to peripherals. peripherals may require reconfiguration to continue operation at the same rate as they did before the clock switch occurred. ? if the new clock source uses the pll, a clock switch will not occur until lock has been achieved. ? if the wdt is used, care must be taken to ensure it can be serviced in a timely manner at the new clock rate. note: the processor will continue to execute code throughout the clock switching sequence. timing-sensitive code should not be executed during this time. notes: there are no timing requirements for the steps other than the initial back-to-back writing of the key values to perform the unlock sequence. the unlock sequence unlocks all registers that are secured by the lock function. it is recommended that amount to time is the system is unlock is kept to a minimum. the core sequence for unlocking the osccon register and initiating a clock switch is shown in example 4-2. note: the application should not attempt to switch to a clock with a frequency lower than 100 khz when the fail-safe clock monitor is enabled. clock switching in these instances may generate a false oscillator fail event and result in a switch to the internal fast rc oscillator. note: the device does not prevent changing the pll postscaler or multiplier values on the clock source that is in use. the device will not permit direct switching between pll clock sources. the user should not change the pll multiplier values or post- scaler values when running from the affected pll source. to perform either of the above clock switching functions, the clock switch should be performed in two steps. the clock source should first be switched to a non-pll source, such as frc, and then switched to the desired source. this requirement only applies to pll-based clock sources.
? 2008 microchip technology inc. preliminary ds61143e-page 81 pic32mx3xx/4xx example 4-2: performi ng a clock switch 4.2.6.4 entering sleep mode during a clock switch if the device enters sleep mode during a clock switch operation, the clock switch operation is aborted. the processor keeps the old clock selection and the oswen bit (osccon<0>) is cleared. the wait instruction is then executed normally. 4.2.6.5 sosc control the sosc can be used by modules, as well as the cpu. therefore, the sosc is controlled by a combina- tion of software and hardware. setting the soscen bit (osccon<1>) to a ? 1 ? enables the sosc. the sosc is disabled when it is not being used by the cpu mod- ule and the soscen bit is ? 0 ?. if the sosc is being used as sysclk, such as after a clock switch, it can- not be disabled by writing to the soscen bit. if the sosc is enabled by the soscen bit, it will continue to operate when the device is in sleep. to prevent inad- vertent clock changes the osccon register is locked. it must be unlocked prior to software enabling or disabling the sosc. 4.3 input/output pins the pins used by the posc and sosc are shared by other peripherals modules. table shows the function of these shared pins in the available oscillator modes. when the pins are not used by a oscillator they are available for use as general i/o pins or by use by a peripheral sharing the pin. // note: clock switching must be enabled in the device configuration syskey = 0x0; // write invalid key to force lock syskey = 0xaa996655; // write key1 to syskey syskey = 0x556699aa; // write key2 to syskey // osccon is now unlocked // make the desired change oscconclr = 7 << 8; // clear the clock select bits oscconset = 7 << 8; // set the new clock source to frc oscconset = 1; // request clock switch // relock the syskey syskey = 0x0; // write any value other than key1 or key2 // osccon is relocked table 4-8: configuration of pins associated with the oscillator module pin name clock mode configuration bit field (1) tris pin type osci hs, hspll, xt, xtpll cosc<2:0>, poscmd<1:0> x osc osco hs, hspll, xt, xtpll cosc<2:0>, poscmd xosc osci ec, ecpll cosc<2:0>, poscmd xc lock i n osco ec, ecpll cosc<2:0>, poscmd, oscofnc x pbclk o ut osco ec, ecpll cosc<2:0>, poscmd, oscofnc i nput i nput osco ec, ecpll cosc<2:0>, poscmd, oscofnc o utput o utput n/a frc, frcpll, frcdiv16, frcdiv, lprc cosc<2:0> xgpio n/a frc, frcpll, frcdiv16, frcdiv, lprc cosc<2:0> xgpio n/a frc, frcpll, frcdiv16, frcdiv, lprc cosc<2:0> xgpio n/a frc, frcpll, frcdiv16, frcdiv, lprc cosc<2:0> xgpio sosci sosc cosc<2:0> xosc sosco sosc cosc<2:0> xosc note 1: during device start-up, the device oscillator configuration data is copied from device configuration to cosc.
pic32mx3xx/4xx ds61143e-page 82 preliminary ? 2008 microchip technology inc. 4.3.1 osci and osco pin functions in non-external oscillator modes when the primary oscillator (posc) on osci and osco is not configured as a clock source the osci pin is automatically reconfigured as a digital i/o. in this configuration, as well as when the primary oscillator is configured for ec mode (poscmd1:poscmd0 = 00 ), the osco pin can also be configured as a digital i/o by programming the osciofcn configuration bit. when osciofcn is unprogrammed (? 1 ?), a pbclk is available on osco for testing or synchronization pur- poses. with osciofcn programmed (? 0 ?), the osco pin becomes a general purpose i/o pin. in both of these configurations, the feedback device between osci and osco is turned off to save current. 4.3.2 sosci and soci pin functions in non-external oscillator modes when the secondary oscillator (sosc) on sosci and sosco pin is not configured as a clock source the pins are automatically reconfigured as a digital i/o.
? 2008 microchip technology inc. preliminary ds61143e-page 83 pic32mx3xx/4xx 5.0 resets the reset module combines all reset sources and controls the device master reset signal, sysrst. the following is a list of device reset sources: ? por: power-on reset ?mclr : master clear reset pin ? swr: software reset ? wdtr: watchdog timer reset ? bor: brown-out reset ? cmr: configuration mismatch reset a simplified block diagram of the reset module is shown in figure 5-1. figure 5-1: system reset block diagram note: this data sheet summarizes the features of the pic32mx3xx/4xx family of devices. it is not intended to be a comprehensive refer- ence source. refer to the ?pic32mx family reference manual? (ds61132) for a detailed description of this peripheral. mclr v dd v dd rise detect por sleep or idle brown-out reset wdt time-out glitch filter bor configuration sysrst software reset power-up timer voltage enabled reset wdtr swr cmr mclr mismatch regulator
pic32mx3xx/4xx ds61143e-page 84 preliminary ? 2008 microchip technology inc. 5.1 reset registers table 5-1: reset sfr summary virtual address name bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 bf80_f600 rcon 31:24 ? ? ? ? ? ? ? ? 23:16 ? ? ? ? ? ? ? ? 15:8 ? ? ? ? ? ? cmr vregs 7:0 extr swr ? wdto sleep idle bor por bf80_f604 rconclr 31:0 write clears selected bits in rcon, read yields undefined value bf80_f608 rconset 31:0 write sets selected bits in rcon, read yields undefined value bf80_f60c rconinv 31:0 write inverts selected bits in rcon, read yields undefined value bf80_f610 rswrst 31:24 ? ? ? ? ? ? ? ? 23:16 ? ? ? ? ? ? ? ? 15:8 ? ? ? ? ? ? ? ? 7:0 ? ? ? ? ? ? ?swrst bf80_f614 rswrstclr 31:0 write clears selected bits in rswrst, read yields undefined value bf80_f618 rswrstset 31:0 write sets selected bits in rswrst, read yields undefined value bf80_f61c rswrstinv 31:0 write inverts selected bits in rswrst, read yields undefined value
? 2008 microchip technology inc. preliminary ds61143e-page 85 pic32mx3xx/4xx register 5-1: rcon: re set control register (3) r-x r-x r-x r-x r-x r-x r-x r-x ? ? ? ? ? ? ? ? bit 31 bit 24 r-x r-x r-x r-x r-x r-x r-x r-x ? ? ? ? ? ? ? ? bit 23 bit 16 r-x r-x r-x r-x r-x r-0 r/w-0 r/w-0 ? ? ? ? ? ? cmr vregs bit 15 bit 8 r/w-0 r/w-0 r-x r/w-0 r/w-0 r/w-0 r/w-1 r/w-1 extr swr ? wdto sleep idle bor por bit 7 bit 0 legend: r = readable bit w = writable bit p = programmable bit r = reserved bit u = unimplemented bit -n = bit value at por: (?0?, ?1?, x = unknown) bit 31-10 reserved: write ? 0 ?; ignore read bit 9 cmr: configuration mismatch flag bit 1 = a configuration mismatch reset has occurred 0 = a configuration mismatch reset has not occurred note: this bit is set in hardware, it can only be cleared (= 0 ) in software. bit 8 vregs: voltage regulator standby enable bit 1 = regulator will be active during sleep 0 = regulator will go to standby mode during sleep bit 7 extr: external reset (mclr ) pin flag bit 1 = a master clear (pin) reset has occurred 0 = a master clear (pin) reset has not occurred note: this bit is set in hardware, it can only be cleared (= 0 ) in software. bit 6 swr: software reset flag bit 1 = a software reset was executed 0 = a software reset was not executed note: this bit is set in hardware, it can only be cleared (= 0 ) in software. bit 5 reserved: write ? 0 ?; ignore read bit 4 wdto: watchdog timer time-out flag bit 1 = wdt time-out has occurred 0 = wdt time-out has not occurred note: this bit is set in hardware, it can only be cleared (= 0 ) in software. bit 3 sleep: wake from sleep flag bit 1 = device was in sleep mode 0 = device was not in sleep mode note: this bit is set in hardware, it can only be cleared (= 0 ) in software. note 1: user must clear this bit to view next detection. 2: bor is also set after a power-on reset. 3: the rcon flag bits only serve as status bits. setting a particular reset status bit in software will not cause a device reset to occur.
pic32mx3xx/4xx ds61143e-page 86 preliminary ? 2008 microchip technology inc. bit 2 idle: wake-up from idle flag bit 1 = device was in idle mode 0 = device was not in idle mode note: this bit is set in hardware, it can only be cleared (= 0 ) in software. bit 1 bor: brown-out reset flag bit (1,2) 1 = a brown-out reset has occurred. 0 = a brown-out reset has not occurred note: this bit is set in hardware, it can only be cleared (= 0 ) in software. bit 0 por: power-on reset flag bit (1) 1 = a power-on reset has occurred 0 = a power-on reset has not occurred note: this bit is set in hardware, it can only be cleared (= 0 ) in software. register 5-1: rcon: re set control register (3) (continued) note 1: user must clear this bit to view next detection. 2: bor is also set after a power-on reset. 3: the rcon flag bits only serve as status bits. setting a particular reset status bit in software will not cause a device reset to occur.
? 2008 microchip technology inc. preliminary ds61143e-page 87 pic32mx3xx/4xx register 5-2: rswrst: software reset register r-x r-x r-x r-x r-x r-x r-x r-x ? ? ? ? ? ? ? ? bit 31 bit 24 r-x r-x r-x r-x r-x r-x r-x r-x ? ? ? ? ? ? ? ? bit 23 bit 16 r-x r-x r-x r-x r-x r-x r-x r-x ? ? ? ? ? ? ? ? bit 15 bit 8 r-x r-x r-x r-x r-x r-x r-x w-0 ? ? ? ? ? ? ?swrst bit 7 bit 0 legend: r = readable bit w = writable bit p = programmable bit r = reserved bit u = unimplemented bit -n = bit value at por: (?0?, ?1?, x = unknown) bit 31-1 reserved: write ? 0 ?; ignore read bit 0 swrst: software reset trigger bit 1 = enable software reset event 0 = has no effect note: the system unlock sequence must be performed before the swrst bit can be written. a read must follow the write of this bit to generate a reset.
pic32mx3xx/4xx ds61143e-page 88 preliminary ? 2008 microchip technology inc. 5.2 reset modes the pic32mx3xx/4xx internal device reset signal is sysrst and can be generated from multiple reset sources, such as por (power-on reset), bor (brown-out reset), mclr (master clear reset), wdto (watchdog time-out reset), swr (software reset) and cmr (configuration mismatch reset). a reset source sets a corresponding status bit in the rcon register to indicate the type of reset (see register 5-1). a system reset is active at first the por and asserted until device configuration settings are loaded and the clock oscillator sources become stable. the system reset is then deasserted allowing the cpu to start fetching code after 8 system clock cycles (sys- clk). 5.2.1 power-on reset (por) a power-on event generates an internal power-on reset pulse when a v dd rise is detected above v por . the device supply voltage characteristics must meet the specified starting voltage and rise rate require- ments to generate the por pulse. in particular, v dd must fall below v por before a new por is initiated. for more information on the v por and v dd rise rate speci- fications, refer to section 30.0 ?electrical character- istics? of this device family data sheet. 5.2.2 mclr reset (extr) whenever the mclr pin is driven low, the device asyn- chronously asserts sysrst provided t he input pulse on mclr is longer than a certain minimum width, as spec- ified in section 30.0 ?electrical characteristics? of this device family data sheet. mclr provides a filter to minimize the effects of noise and to avoid unwanted reset conditions. the extr bit (rcon<7>) is set to indicate the mclr reset. 5.2.3 software reset (swr) the pic32mx3xx/4xx cpu core doesn?t provide a specific reset ?instruction?; however, a hardware reset can be performed in software (software reset) by executing a software reset command sequence: ? write the system unlock sequence ? set bit, swrst (rswrst<0>) = 1 ? read rswrst register ? reset occurs ? follow with ?while(1);? or 4 ? nop ? instructions writing a ? 1 ? to the rswrst register sets bit swrst, arming the software reset. the subsequent read of the rswrst register triggers the software reset, which should occur on the next clock cycle following the read operation. to ensure no other user code is executed before the reset event occurs, it is recom- mended that 4 ? nop ? instructions or a ?while(1);? state- ment be placed after the read instruction. the swr status bit (rcon<6>) is set to indicate the software reset. example 5-1: software reset command sequence /* the following code illustrates a software reset */ // assume interrupts are disabled // assume the dma controller is suspended // assume the device is locked /* perform a system unlock sequence */ // starting critical sequence syskey = 0x12345678; //write invalid key to force lock syskey = 0xaa996655 //write key1 to syskey syskey = 0x556699aa //write key2 to syskey // osccon is now unlocked /* set swrst bit to arm reset */ rswrstset = 1; /* read rswrst register to trigger reset */ unsigned int dummy; dummy = rswrst; /* prevent any unwanted code execution until reset occurs*/
? 2008 microchip technology inc. preliminary ds61143e-page 89 pic32mx3xx/4xx 5.2.4 watchdog timer time-out reset (wdtr) a watchdog timer time-out causes the device reset, sysrst, to be asserted asynchronously. note that a wdt time-out during sleep or idle mode will wake-up the processor and branch to the pic32mx3xx/4xx reset vector, but not reset the processor. the only bits affected are wdto and the sleep or idle bits in the rcon register. for more information, refer to section 26.0 ?watchdog timer? . 5.2.5 brown-out reset (bor) pic32mx3xx/4xx devices have a simple brown-out capability. if the voltage supplied to the regulator is inad- equate to maintain a regulated level, the regulator reset circuitry will generate a brown-out reset. this event is captured by the bor flag bit (rcon<1>). refer to section 30.2 ?ac characteristics and timing param- eters? for further details. 5.2.6 configuration mismatch reset to maintain the integrity of the stored configuration val- ues, all device configuration bits are implemented as a complementary set of register bits. for each bit, as the actual value of the register is written as ? 1 ?, a comple- mentary value, ? 0 ?, is stored into its corresponding background register and vice versa. the bit pairs are compared every time, including sleep mode. during this comparison, if the configuration bit values are not found opposite to each other, a configuration mismatch event is generated which causes a device reset. if a device reset occurs as a result of a configuration mismatch, the cm bit (rcon<9>) is set. 5.3 reset states 5.3.1 special function register reset states most of the special function registers (sfrs) associ- ated with the pic32mx3xx/4xx cpu and peripherals are reset to a particular value at a device reset. refer to the corresponding data sheet section for a periph- eral?s sfr details. the reset value for each sfr will depend on the type of reset. 5.3.2 configuration word register reset states all reset conditions force the flash configuration word registers to be re-loaded. however, a por forces flash configuration word registers to be reset prior to being reloaded. for all other reset conditions, the flash configuration word registers are not reset prior to being re-loaded. this difference accommodates mclr assertions during debug mode without affecting the state of the debug operations. note: in this document, a distinction is made between a power mode as it is used in a specific module, and a power mode as it is used by the device, e.g., sleep mode of the comparator and sleep mode of the cpu. to indicate which type of power mode is intended, uppercase and lowercase letters (sleep, idle, debug) signify a module power mode, and all uppercase letters (sleep, idle, debug) signify a device power mode.
pic32mx3xx/4xx ds61143e-page 90 preliminary ? 2008 microchip technology inc. 5.3.3 rcon register states status bits from the rcon register are set or cleared differently in different reset situations, as indicated in table 5-2. the rcon bits only serve as status bits. the user may set or clear any of the bits at any time during code execution. setting a particular reset bit in software will not cause a device reset to occur. the rcon register also has other bits associated with the watchdog timer and device power-saving states. table 5-2: status bits, initialization condition for rcon register 5.4 using the rcon status bits the user can read the rcon register after any device reset to determine the cause of the reset. the status bits in the rcon register should be cleared after they are read so that the next rcon register value after a device reset will be meaningful. condition program counter extr swr wdto sleep idle cm bor por power-on reset 0xbfc0_0000 00000011 brown-out reset 000000 10 mclr during run mode 1 uuuuuuu mclr during idle mode 1 u u u 1 (2) uuu mclr during sleep mode 1 u u1 (2) uuuu software reset command u1uuuuuu configuration word mismatch reset uuuuu1uu wdt time-out reset during run mode uu1uuuuu wdt time-out reset during idle mode uu1u1 (2) uuu wdt time-out reset during sleep mode uu11 (2) uuuu interrupt exit from idle mode vector (1) uu0u1 (2) uuu interrupt exit from sleep mode uu01 (2) uuuu legend: u = unchanged note 1: depends on interrupt source. 2: sleep and idle bits states defined by previously executed wait instruction.
? 2008 microchip technology inc. preliminary ds61143e-page 91 pic32mx3xx/4xx table 5-3: reset flag bit operation 5.4.1 device reset to code execution start time the delay between the end of a reset event and when the device actually begins to execute code is determined by two main factors: the type of reset and the system clock source coming out of the reset. the code execu- tion start time for various types of device resets are characterized in section 30.2 ?ac characteristics and timing parameters? . flag bit set by: cleared by: por (rcon<0>) por user software bor (rcon<1>) por, bor user software extr (rcon<7>) mclr reset user software, por, bor swr (rcon<6>) software reset command user software, por, bor cmr (rcon<9> configuration mismatch user software, por, bor wdto (rcon<4>) wdt time-out user software, por, bor sleep (rcon<3>) wait instruction user software, por, bor idle (rcon<2>) wait instruction user software, por, bor note: all reset flag bits may be set or cleared by the user software. table 5-4: code execution start time for various device resets reset type clock source power-up delay (1)(2)(3) system clock delay (4)(5) fscm delay (6) por ec, frc, frcdiv, lprc (t pu or t pwrt ) + t sysdly ?? ecpll, frcpll (t pu or t pwrt ) + t sysdly t lock t fscm xt, hs, sosc (t pu or t pwrt ) + t sysdly t ost t fscm xtpll, hspll (t pu or t pwrt ) + t sysdly t ost + t lock t fscm bor ec, frc, frcdiv, lprc t sysdly ?? ecpll, frcpll t sysdly t lock t fscm xt, hs, sosc t sysdly t ost t fscm xtpll t sysdly t ost + t lock t fscm mclr , cmr, swr, wdto any clock t sysdly ? ? note 1: t pu = power-up period with on-chip regulator enabled. 2: t pwrt = power-up period (p ower - up t imer ) with on-chip regulator disabled. 3: t sysdly = time required to reload device configuration fuses plus 8 sysclk cycles. 4: t ost = oscillator start-up timer. 5: t lock = pll lock time. 6: t fscm = fail-safe clock monitor delay. note: for parameter specifications, see section 30.2 ?ac characteristics and timing parameters.?
pic32mx3xx/4xx ds61143e-page 92 preliminary ? 2008 microchip technology inc. 5.5 interrupts there are no interrupts for this module. 5.6 i/o pin control there are not i/o pin controls associated with this module.
? 2008 microchip technology inc. preliminary ds61143e-page 93 pic32mx3xx/4xx 6.0 memory organization pic32mx3xx/4xx microcontrollers provides 4 gb of unified virtual memory address space. all memory regions including program, data memory, sfrs, and configuration registers reside in this address space at their respective unique addresses. the program and data memories can be optionally partitioned into user and kernel memories. in addition, the data memory can be made executable, allowing pic32mx3xx/4xx to execute from data memory. key features: ? 32-bit native data width ? separate user and kernel mode address space ? flexible program flash memory partitioning ? flexible data ram partitioning for data and program space ? separate boot flash memory for protected code ? robust bus exception handling to intercept runaway code. ? simple memory mapping with fixed mapping translation (fmt) unit ? cacheable and non-cacheable address regions 6.1 pic32mx3xx/4xx memory layout pic32mx3xx/4xx microcontrollers implement two address spaces: virtual and physical. all hardware resources such as program memory, data memory and peripherals are located at their respective physical addresses. virtual addresses are exclusively used by the cpu to fetch and execute instructions as well as access peripherals. physical addresses are used by peripherals such as dma and flash controller that access memory independently of cpu. the entire 4 gb virtual address space is divided into two primary regions ? user and kernel space. the lower 2 gb of space forms the user mode segment, called useg/kuseg. the upper 2 gb of virtual address space forms the kernel-only space. the kernel space is divided into four segments of 512 mb each: kseg 0, kseg 1, kseg 2 and kseg 3. only kernel mode applica- tions can access kernel space memory. the peripheral registers are only visible through kernel space. the fixed mapping translation (fmt) unit translates the memory segments into corresponding physical address regions. a virtual memory segment may also be cached, provided the cache module is available on the device. please note that the kseg 1 memory seg- ment is not cacheable, while kseg 0 and useg/kuseg are cacheable. note: this data sheet summarizes the features of the pic32mx3xx/4xx family of devices. it is not intended to be a comprehensive refer- ence source. refer to the ?pic32mx family reference manual? (ds61132) for a detailed description of this peripheral.
pic32mx3xx/4xx ds61143e-page 94 preliminary ? 2008 microchip technology inc. figure 6-1: virtual to phys ical fixed memory mapping internal boot flash internal peripherals internal program flash 0x1fc00000 0x00000000 0x1d000000 0x1f800000 internal flash (user partition) 0x40000000 internal ram (user partition) 0xbf000000 + bmxdudba physical memory map 0xffffffff internal ram reserved reserved 0x4fffffff 0x0fffffff 0xbd000000 + bmxpupba bmxdudba internal boot flash internal peripherals internal program flash internal boot flash internal program flash program flash (user partition) 0x0fffffff 0x80000000 0xbfc00000 0xa0000000 0xbd000000 0xbf800000 0x9d000000 0x9fc00000 internal ram (user partition) 0x7f000000 virtual memory map 0xc0000000 kseg2/kseg3 0xffffffff kseg1 0 g e s k g e s u k / g e s u reserved internal ram reserved 0x7d000000+ bmxpupba 0xafffffff internal ram 0x8fffffff reserved 0x00000000
? 2008 microchip technology inc. preliminary ds61143e-page 95 pic32mx3xx/4xx 6.2 bus matrix registers table 6-1: bus matrix register summary virtual address name bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 bf88_2000 bmxcon 31:24 ? ? ? ? ?bmx- chedma ? ? 23:16 ? ? ? bmxerrixi bmxerricd bmx- errdma bmxerrds bmxerris 15:8 ? ? ? ? ? ? ? ? 7:0 ? bmxwsdrm ? ? ? bmxarb<2:0> bf88_2004 bmxcon- clr 31:0 write clears selected bits in bmxcon, read yields undefined value bf88_2008 bmxcon- set 31:0 write sets selected bits in bm xcon, read yields undefined value bf88_200c bmxcon- inv 31:0 write inverts selected bits in bmxcon, read yields undefined value bf88_2010 bmxdkpba 31:24 ? ? ? ? ? ? ? ? 23:16 ? ? ? ? ? ? ? ? 15:8 bmxdkpba<15:8> 7:0 bmxdkpba<7:0> bf88_2014 bmx- dkpbaclr 31:0 write clears selected bits in bmxdkpba, read yields undefined value bf88_2018 bmx- dkpbaset 31:0 write sets selected bits in bmxdkpba, read yields undefined value bf88_201c bmx dkpbainv 31:0 write inverts selected bits in bmxdkpba, read yields undefined value bf88_2020 bmxdudba 31:24 ? ? ? ? ? ? ? ? 23:16 ? ? ? ? ? ? ? ? 15:8 bmxdudba<15:8> 7:0 bmxdudba<7:0> bf88_2024 bmx- dudbaclr 31:0 write clears selected bits in bmxdudba, read yields undefined value bf88_2028 bmx- dudbaset 31:0 write sets selected bits in bmxdudba, read yields undefined value bf88_202c bmx- dudbainv 31:0 write inverts selected bits in bmxdudba, read yields undefined value bf88_2030 bmx dupba 31:24 ? ? ? ? ? ? ? ? 23:16 ? ? ? ? ? ? ? ? 15:8 bmxdupba<15:8> 7:0 bmxdupba<7:0> bf88_2034 bmx dupbaclr 31:0 write clears selected bits in bmxdupba, read yields undefined value bf88_2038 bmx dupbaset 31:0 write sets selected bits in bmxdupba, read yields undefined value bf88_203c bmx dupbainv 31:0 write inverts selected bits in bmxdupba, read yields undefined value bf88_2040 bmxdrmsz 31:24 bmxdrmsz<31:24> 23:16 bmxdrmsz<23:16> 15:8 bmxdrmsz<15:8> 7:0 bmxdrmsz<7:0> bf88_2050 bmxpupba 31:24 ? ? ? ? ? ? ? ? 23:16 ? ? ? ? bmxpupba<19:16> 15:8 bmxpupba<15:8> 7:0 bmxpupba<7:0> bf88_2060 bmxpfmsz 31:24 bmxpfmsz<31:24> 23:16 bmxpfmsz<23:16> 15:8 bmxpfmsz<15:8> 7:0 bmxpfmsz<7:0> bf88_2070 bmx- bootsz 31:24 bmxbootsz<31:24> 23:16 bmxbootsz<23:16> 15:8 bmxbootsz<15:8> 7:0 bmxbootsz<7:0>
pic32mx3xx/4xx ds61143e-page 96 preliminary ? 2008 microchip technology inc. register 6-1: bmxcon: bus matrix configuration register r-x r-x r-x r-x r-x r/w-0 r-x r-x ? ? ? ? ?bmx- chedma ? ? bit 31 bit 24 r-x r-x r-x r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 ? ? ? bmxerrixi bmxer- ricd bmx- errdma bmx- errds bmxerris bit 23 bit 16 r-x r-x r-x r-x r-x r-x r-x r-x ? ? ? ? ? ? ? ? bit 15 bit 8 r-x r/w-1 r-x r-x r-x r/w-0 r/w-0 r/w-0 ?bmxws- drm ? ? ? bmxarb<2:0> bit 7 bit 0 legend: r = readable bit w = writable bit p = programmable bit r = reserved bit u = unimplemented bit -n = bit value at por: (?0?, ?1?, x = unknown) bit 31-27 reserved: write ? 0 ?; ignore read bit 26 bmxchedma: bmx pfm cacheability for dma accesses bit 1 = enable program flash memory (data) cacheability for dma accesses (requires cache to have data caching enabled) 0 = disable program flash memory (data) cacheability for dma accesses (hits are still read from the cache, but misses do not update the cache) bit 25-21 reserved: write ? 0 ?; ignore read bit 20 bmxerrixi: enable bus error from ixi bit 1 = enable bus error exceptions for unmapped address accesses initiated from ixi shared bus 0 = disable bus error exceptions for unmapped address accesses initiated from ixi shared bus bit 19 bmxerricd: enable bus error from icd debug unit bit 1 = enable bus error exceptions for unmapped address accesses initiated from icd 0 = disable bus error exceptions for unmapped address accesses initiated from icd bit 18 bmxerrdma: bus error from dma bit 1 = enable bus error exceptions for unmapped address accesses initiated from dma 0 = disable bus error exceptions for unmapped address accesses initiated from dma bit 17 bmxerrds: bus error from cpu data access bit (disabled in debug mode) 1 = enable bus error exceptions for unmapped address accesses initiated from cpu data access 0 = disable bus error exceptions for unmapped address accesses initiated from cpu data access bit 16 bmxerris: bus error from cpu instruction access bit (disabled in debug mode) 1 = enable bus error exceptions for unmapped address accesses initiated from cpu instruction access 0 = disable bus error exceptions for unmapped address accesses initiated from cpu instruction access bit 15-7 reserved: write ? 0 ?; ignore read
? 2008 microchip technology inc. preliminary ds61143e-page 97 pic32mx3xx/4xx bit 6 bmxwsdrm: cpu instruction or data access from data ram wait state bit 1 = data ram accesses from cpu have one wait state for address setup 0 = data ram accesses from cpu have zero wait states for address setup bit 5-3 reserved: write ? 0 ?; ignore read bit 2-0 bmxarb<2:0>: bus matrix arbitration mode bits 111...011 = reserved (using these configuration modes will produce undefined behavior) 010 = arbitration mode 2 001 = arbitration mode 1 000 = arbitration mode 0 note: for detailed descriptions of the arbitration modes, refer to the ? pic32mx family reference manual, chapter 3. memory organization, section 3.5 bus matrix? (ds61132). register 6-1: bmxcon: bus matrix configuration register (continued)
pic32mx3xx/4xx ds61143e-page 98 preliminary ? 2008 microchip technology inc. register 6-2: bmxdkpba: data ram kernel program base address register r-x r-x r-x r-x r-x r-x r-x r-x ? ? ? ? ? ? ? ? bit 31 bit 24 r-x r-x r-x r-x r-x r-x r-x r-x ? ? ? ? ? ? ? ? bit 23 bit 16 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r-0 r-0 r-0 bmxdkpba<15:8> bit 15 bit 8 r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 bmxdkpba<7:0> bit 7 bit 0 legend: r = readable bit w = writable bit p = programmable bit r = reserved bit u = unimplemented bit -n = bit value at por: (?0?, ?1?, x = unknown) bit 31-16 reserved: write ? 0 ?; ignore read bit 15-11 bmxdkpba<15:11>: drm kernel program base address bits when non-zero, this value selects the relative base address for kernel program space in ram bit 10-0 bmxdkpba<10:0>: read-only bits value is always ? 0 ?, which forces 2 kb increments
? 2008 microchip technology inc. preliminary ds61143e-page 99 pic32mx3xx/4xx register 6-3: bmxdudba: data ram user data base address register r-x r-x r-x r-x r-x r-x r-x r-x ? ? ? ? ? ? ? ? bit 31 bit 24 r-x r-x r-x r-x r-x r-x r-x r-x ? ? ? ? ? ? ? ? bit 23 bit 16 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r-0 r-0 r-0 bmxdudba<15:8> bit 15 bit 8 r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 bmxdudba<7:0> bit 7 bit 0 legend: r = readable bit w = writable bit p = programmable bit r = reserved bit u = unimplemented bit -n = bit value at por: (?0?, ?1?, x = unknown) bit 31-16 reserved: write ? 0 ?; ignore read bit 15-11 bmxdudba<15:11>: drm user data base address bits when non-zero, the value selects the relative base address for user mode data space in ram note: if non-zero, the value must be greater than bmxdkpba. bit 10-0 bmxdudba<10:0>: read-only bits value is always ? 0 ?, which forces 2 kb increments
pic32mx3xx/4xx ds61143e-page 100 preliminary ? 2008 microchip technology inc. register 6-4: bmxdupba: data ram user program base address register r-x r-x r-x r-x r-x r-x r-x r-x ? ? ? ? ? ? ? ? bit 31 bit 24 r-x r-x r-x r-x r-x r-x r-x r-x ? ? ? ? ? ? ? ? bit 23 bit 16 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r-0 r-0 r-0 bmxdupba<15:8> bit 15 bit 8 r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 bmxdupba<7:0> bit 7 bit 0 legend: r = readable bit w = writable bit p = programmable bit r = reserved bit u = unimplemented bit -n = bit value at por: (?0?, ?1?, x = unknown) bit 31-16 reserved: write ? 0 ?; ignore read bit 15-11 bmxdupba<15:11>: drm user program base address bits when non-zero, the value selects the relative base address for user mode program space in ram note: if non-zero, bmxdupba must be greater than bmxdudba. bit 10-0 bmxdupba<10:0>: read-only bits value is always ? 0 ?, which forces 2 kb increments
? 2008 microchip technology inc. preliminary ds61143e-page 101 pic32mx3xx/4xx register 6-5: bmxdrmsz: data ram size register rrrrrrrr bmxdrmsz<31:24> bit 31 bit 24 rrrrrrrr bmxdrmsz<23:16> bit 23 bit 16 rrrrrrrr bmxdrmsz<15:8> bit 15 bit 8 rrrrrrrr bmxdrmsz<7:0> bit 7 bit 0 legend: r = readable bit w = writable bit p = programmable bit r = reserved bit u = unimplemented bit -n = bit value at por: (?0?, ?1?, x = unknown) bit 31-0 bmxdrmsz: data ram memory (drm) size bits static value that indicates the size of the data ram in bytes: 0x00002000 = device has 8 kb ram 0x00004000 = device has 16 kb ram 0x00008000 = device has 32 kb ram
pic32mx3xx/4xx ds61143e-page 102 preliminary ? 2008 microchip technology inc. register 6-6: bmxpupba: program flash (pfm) user program base address register r-x r-x r-x r-x r-x r-x r-x r-x ? ? ? ? ? ? ? ? bit 31 bit 24 r-x r-x r-x r-x r/w-0 r/w-0 r/w-0 r/w-0 ? ? ? ? bmxpupba<19:16> bit 23 bit 16 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r-0 r-0 r-0 bmxpupba<15:8> bit 15 bit 8 r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 bmxpupba<7:0> bit 7 bit 0 legend: r = readable bit w = writable bit p = programmable bit r = reserved bit u = unimplemented bit -n = bit value at por: (?0?, ?1?, x = unknown) bit 31-20 reserved: write ? 0 ?; ignore read bit 19-11 bmxpupba<19:11>: program flash (pfm) user program base address bits when non-zero, this value selects the pfm relative base address for user mode program space. bit 10-0 bmxpupba<10:0>: read-only bits value is always ? 0 ?, which forces 2 kb increments
? 2008 microchip technology inc. preliminary ds61143e-page 103 pic32mx3xx/4xx register 6-7: bmxpfmsz: program flash (pfm) size register rrrrrrrr bmxpfmsz<31:24> bit 31 bit 24 rrrrrrrr bmxpfmsz<23:16> bit 23 bit 16 rrrrrrrr bmxpfmsz<15:8> bit 15 bit 8 rrrrrrrr bmxpfmsz<7:0> bit 7 bit 0 legend: r = readable bit w = writable bit p = programmable bit r = reserved bit u = unimplemented bit -n = bit value at por: (?0?, ?1?, x = unknown) bit 31-0 bmxpfmsz: program flash memory (pfm) size bits static value that indicates the size of the pfm in bytes: 0x00008000 = device has 32 kb flash 0x00010000 = device has 64 kb flash 0x00020000 = device has 128 kb flash 0x00040000 = device has 256 kb flash 0x00080000 = device has 512 kb flash
pic32mx3xx/4xx ds61143e-page 104 preliminary ? 2008 microchip technology inc. register 6-8: bmxbootsz: boot flash (ifm) size register rrrrrrrr bmxbootsz<31:24> bit 31 bit 24 rrrrrrrr bmxbootsz<23:16> bit 23 bit 16 rrrrrrrr bmxbootsz<15:8> bit 15 bit 8 rrrrrrrr bmxbootsz<7:0> bit 7 bit 0 legend: r = readable bit w = writable bit p = programmable bit r = reserved bit u = unimplemented bit -n = bit value at por: (?0?, ?1?, x = unknown) bit 31-0 bmxbootsz: boot flash memory (bfm) size bits static value that indicates the size of the boot pfm in bytes: 0x00003000 = device has 12 kb boot flash
? 2008 microchip technology inc. preliminary ds61143e-page 105 pic32mx3xx/4xx 6.3 user and kernel memory areas the two modes of operation of the pic32mx3xx/4xx core are user mode and kernel mode. to support these modes, the virtual address space is also divided into two segments, kernel segments and user seg- ments. the lower 2 gigabytes of virtual addresses form the user mode partition, and the upper 2 gigabytes forms the kernel mode partition. most application will run only in kernel mode. for these applications, the entire program can reside in the ker- nel address space providing full access to all resources. figure 6-2: user/kernel address segments kernel segments (kseg 0,1,2,3) user / kernel segment (useg / kuseg) 0x00000000 0x7fffffff 0x80000000 0xffffffff
pic32mx3xx/4xx ds61143e-page 106 preliminary ? 2008 microchip technology inc. 6.4 pic32mx3xx/4xx address map table 6-2 shows the address map of the pic32mx3xx/4xx microcontroller. on reset, the pic32mx3xx/4xx starts executing code from 0xbfc0_0000 virtual address which reside in the kseg1 segment (non cacheable segment). 6.4.1 physical memory address the kernel program flash address space starts at physical address 0x1d000000, whereas the user pro- gram flash space starts at physical address 0xbd000000 + bmxpupba register value. similarly, the internal ram is also divided into kernel and user partitions. the kernel ram space starts at physical address 0x00000000, whereas the user ram space starts at physical address 0xbf000000 + bmxdudba register value. by default the entire flash memory and ram are mapped to the kernel mode application only. table 6-2: pic32mx3xx/4xx address map virtual addresses physical addresses size in bytes memory type begin address end address be gin address end address calculation kernel address space boot flash 0xbfc00000 0xbfc02fff 0x1fc00000 0x1fc02fff 12 kb program flash (1) 0xbd000000 0xbd000000 + bmxpupba - 1 0x1d000000 0x1d00000 + bmxpupba - 1 bmxpupba program flash (2) 0x9d000000 0x9d000000 + bmxpupba - 1 0x1d000000 0x1d000000 + bmxpupba - 1 bmxpupba ram (data) 0x80000000 0x80000000 + bmxdkpba - 1 0x00000000 bmxdkpba - 1 bmxdkpba ram (prog) 0x80000000 + bmxdkpba 0x80000000 + bmxdudba -1 bmxdkpba bmxdudba -1 bmxdudba - bmxdkpba peripheral 0xbf800000 0xbf8fffff 0x1f800000 0x1f8fffff 1 mb user address space program flash 0x7d000000 + bmxpupba 0x7d000000 + pfm size - 1 0xbd000000 + bmxpupba 0xbd000000 + pfm size - 1 pfm size - bmxpupba ram (data) 0x7f000000 + bmxdudba 0x7f000000 + bmxdupba - 1 0xbf000000 + bmxdudba 0xbf000000 + bmxdupba - 1 bmxdupba - bmxdudba ram (prog) 0x7f000000 + bmxdupba 0x7f000000 + ram size (3) - 1 0xbf000000 + bmxdupba 0xbf000000 + ram size (3) - 1 drm size - bmxdupba note 1: program flash virtual addresses in the non-cacheable range (kseg1). 2: program flash virtual addresses in the cacheable and prefetchable range (kseg0). 3: the ram size varies between pic32mx3xx/4xx device family members.
? 2008 microchip technology inc. preliminary ds61143e-page 107 pic32mx3xx/4xx 6.5 program flash memory wait states for optimal performance, pfmws(checon<2:0>) must be programmed to the minimum value possible. there are two parameters that determine this value: flash access time ? the flash access time is 33 nsec for the pic32mx3xx/4xx processor family. cpu core frequency ? the core frequency is programmable. care must be taken when changing fre- quencies to make sure that there are enough wait states to prevent any flash memory access timing violations. to determine the required number of wait states for a particular core clock frequency, refer to table 30-11 in section 30.0 ?electrical characteristics? of this data sheet. 6.6 program flash memory partitioning the program flash memory can be partitioned for user and kernel mode programs as shown in figure 6-3. at reset, the user mode partition does not exist (bmx-pupba is initialized to ? 0 ?). the entire program flash memory is mapped to kernel mode program space starting at virtual address kseg1: 0xbd000000 (or kseg0: 0x9d000000). to set up a partition for the user mode program, initialize bmxpupba as follows: bmxpupba = bmxpfmsz ? user_flash_pgm_sz the user_flash_pgm_sz is the partition size of the user mode program. bmxpfmsz is the bus matrix register that holds the total size of program flash memory. example: assuming the pic32mx3xx/4xx device has 512 kbytes of flash memory, the bmxpfmsz will contain 0x00080000. to create a user flash program partition of 20 kbytes (0x5000): bmxpupba = 0x80000 ? 0x5000 = 0x7b000 the size of the user flash will be 20k and the size left for the kernel flash will be 512k ? 20k = 492k. the user flash partition will extend from 0x7d07b000 to 0x7d07ffff (virtual addresses). the kernel mode partition always starts from kseg1: 0xbd000000 or kseg0: 0x9d000000. in the above example, the kernel partition will extend from 0xbd000000 to 0xbd07afff (492 kbytes in size).
pic32mx3xx/4xx ds61143e-page 108 preliminary ? 2008 microchip technology inc. figure 6-3: flash partitioning 6.6.1 ram partitioning the ram memory can be divided into 4 partitions. these are: 1. kernel data 2. kernel program 3. user data 4. user program in order to execute from data ram, a kernel or user program partition must be defined. at power-on reset, the entire data ram is assigned to the kernel data par- tition. this partition always starts from the base of the data ram. see figure 6-4 for details. the registers controlling the ram partitions are bmxd- kpba, bmxdudba, and bmxdupba. for a detailed discussion on how to use these registers for partition- ing the ram, please refer to the memory organization section of the pic32mx3xx/4xx family reference manual (ds61132). note 1: kernel flash size = bmxpupba 2: user flash size = bmxpfmsz-bmxpupba 3: if bmxpupba is ? 0 ? , then: k flash size = bmxpfmsz (i.e., all the flash) usr flash size = 0 physical address 0x1d000000 virtual address kseg0: 0x9d000000 +bmxpupba +bmxpupba kseg1: 0xbd000000 kseg0: 0x9d000000 kseg1: 0xbd000000 0x7d000000+ bmxpupba 0x00000000 0xbd000000+ bmxpupba kernel flash size (1) user flash size (2) flash partition for kernel program (kseg 0/1) optional flash partition for user program (useg/kuseg)
? 2008 microchip technology inc. preliminary ds61143e-page 109 pic32mx3xx/4xx figure 6-4: ram partitioning 6.6.2 address decode table 6-3 shows the address map for system resources available to the cpu when it is operating in either user mode or kernel mode. table 6-4 shows the address map for system resources mapped in kseg0 that are available to the cpu when it is operating in kernel mode. table 6-5 shows the address map for system resources mapped in kseg1 that are available to the cpu when it is operating in kernel mode. note 1: kernel data ram size = bmxdkpba 2: kernel program ram size = bmxdudba ? bmxdkpba 3: user data ram size = bmxdupba ? bmxdudba 4: user program ram size = drm size ? bmxdupba 5: if bmxdkpba, bmxdudba or bmxdupba is ? 0 ? , then: kernel data ram size = bmxdrmsz (i.e., all ram) kernel program ram size = 0 user data ram size = 0 user program ram size = 0 physical address 0x00000000 virtual address kseg0: 0x80000000 +bmxdudba +bmxdudba kseg1: 0xa0000000 kseg0: 0x80000000 kseg1: 0xa0000000 0x7f000000 +bmxdupba 0x00000000 0xbf000000 +bmxdupba kernel program user program optional kernel program partition kseg 0/1 kernel data partition kseg 0/1 +bmxdkpba +bmxdkpba kseg0: 0x80000000 kseg1: 0xa0000000 0x7f000000 +bmxdudba +bmxdudba 0x00000000 0x00000000 0xbf000000 +bmxdkpba +bmxdudba kernel data user data optional user program ram partition (useg/kuseg) optional user ram partition (useg/kuseg) ram size (2) ram size (1) ram size (4) ram size (3)
pic32mx3xx/4xx ds61143e-page 110 preliminary ? 2008 microchip technology inc. table 6-3: useg/kuseg address map virtual address physical address pic32mx3xxf032x pic32mx3xxf064x pic32mx3xxf128x pic32mx3xxf256x pic32mx3xxf512x 0x0000_0000 0x4000_0000 rsvd rsvd rsvd rsvd rsvd 0x7d00_0000 + bmxpupba - 1 0xbd00_0000 + bmxpupba - 1 0x7d00_0000 + bmxpupba 0xbd00_0000 + bmxpupba pfm user program pfm user program pfm user program pfm user program pfm user program 0x7d00_7fff 0xbd00_7fff rsvd 0x7d00_ffff 0xbd00_ffff rsvd 0x7d01_ffff 0xbd01_ffff rsvd 0x7d03_ffff 0xbd03_ffff rsvd 0x7d07_ffff 0xbd07_ffff 0x7d08_0000 0xbd08_0000 rsvd 0x7d08_0000 + bmxdupba - 1 0xbd08_0000 + bmxdupba - 1 0x7f00_0000 + bmxdudba 0xbf00_0000 + bmxdudba drm user data drm user data drm user data drm user data drm user data 0x7f00_0000 + bmxdupba - 1 0xbf00_0000 + bmxdupba - 1 0x7f00_0000 + bmxdupba 0xbf00_0000 + bmxdupba drm user program drm user program drm user program drm user program drm user program 0x7f00_1fff 0xbf00_1fff drm=8kb drm=8kb rsvd 0x7f00_3fff 0xbf00_3fff drm=16kb drm=16kb drm=16kb rsvd 0x7f00_7fff 0xbf00_7fff drm=32kb drm=32kb drm=32kb 0x7f0_8000 0xbf0_8000 rsvd rsvd rsvd 0x7fff_ffff 0xbfff_ffff
? 2008 microchip technology inc. preliminary ds61143e-page 111 pic32mx3xx/4xx table 6-4: kseg0 address map virtual address physical address pic32mx3xxf032x pic32mx3xxf064x pic32mx3xxf128x pic32mx3xxf256x pic32mx3xxf512x 0x8000_0000 0x0000_0000 drm kernel data drm kernel data drm kernel data drm kernel data drm kernel data 0x8000_0000 + bmxdkpba - 1 0x0000_0000 + bmxdkpba - 1 0x8000_0000 + bmxdkbpa 0x0000_0000 + bmxdkbpa drm kernel program drm kernel program drm kernel program drm kernel program drm kernel program 0x8000_0000 + bmxdudba - 1 0x0000_0000 + bmxdudba - 1 note 1 note 1 note 1 note 1 note 1 0x8000_1fff 0x0000_1fff drm=8kb drm=8kb rsvd 0x8000_3fff 0x0000_3fff drm=16kb drm=16kb drm=16kb rsvd 0x8000_7fff 0x0000_7fff drm=32kb drm=32kb drm=32kb rsvd rsvd rsvd 0x9cff_ffff 0x1cff_ffff 0x9d00_0000 0x1d00_0000 pfm kernel program pfm kernel program pfm kernel program pfm kernel program pfm kernel program 0x9d00_0000 + bmxpupba - 1 0x1d00_0000 + bmxpupba - 1 note 2 note 2 note 2 note 2 note 2 0x9d00_7fff 0x1d00_7fff rsvd 0x9d00_ffff 0x1d00_ffff rsvd 0x9d01_ffff 0x1d01_ffff rsvd 0x9d03_ffff 0x1d03_ffff rsvd 0x9d07_ffff 0x1d07_ffff 0x9d08_0000 0x1d08_0000 rsvd 0x9fbf_ffff 0x1fbf_ffff 0x9fc0_0000 0x1fc0_0000 boot flash boot flash boot flash boot flash boot flash 0x9fc0_2fff 0x1fc0_2fff 0x9fc0_3000 0x1fc0_3000 rsvd rsvd rsvd rsvd rsvd 0x9fff_efff 0x1fff_efff 0x9fff_f000 0x1fff_f000 test flash test flash test flash test flash test flash 0x9fff_ffff 0x1fff_ffff note 1: not available in kseg0 if mapped to useg/kuseg (i.e. bmxdudba or bmxdupba non-zero). 2: not available in kseg0 if mapped in useg/kuseg (i.e. bmxpupba non-zero).
pic32mx3xx/4xx ds61143e-page 112 preliminary ? 2008 microchip technology inc. table 6-5: kseg1 address map virtual address physical address pic32mx3xxf032x pic32mx3xxf064x pic32mx3xxf128x pic32mx3xxf256x pic32mx3xxf512x 0xa000_0000 0x0000_0000 drm kernel data drm kernel data drm kernel data drm kernel data drm kernel data 0xa000_0000 + bmxdkpba - 1 0x0000_0000 + bmxdkpba - 1 0xa000_0000 + bmxdkbpa 0x0000_0000 + bmxdkbpa drm kernel program drm kernel program drm kernel program drm kernel program drm kernel program 0xa000_0000 + bmxdudba - 1 0x0000_0000 + bmxdudba - 1 note 1 note 1 note 1 note 1 note 1 0xa000_1fff 0x0000_1fff drm=8kb drm=8kb rsvd 0xa000_3fff 0x0000_3fff drm=16kb drm=16kb drm=16kb rsvd 0xa000_7fff 0x0000_7fff drm=32kb drm=32kb drm=32kb 0xa000_8000 0x0000_8000 rsvd rsvd rsvd 0xbcff_ffff 0x1cff_ffff 0xbd00_0000 0x1d00_0000 pfm kernel program pfm kernel program pfm kernel program pfm kernel program pfm kernel program 0xbd00_0000 + bmxpupba - 1 0x1d00_0000 + bmxpupba - 1 0xbd00_0000 + bmxpupba 0x1d00_0000 + bmxpupba note 2 note 2 note 2 note 2 note 2 0xbd00_7fff 0x1d00_7fff rsvd 0xbd00_ffff 0x1d00_ffff rsvd 0xbd01_ffff 0x1d01_ffff rsvd 0xbd03_ffff 0x1d03_ffff rsvd 0xbd07_ffff 0x1d07_ffff 0xbd08_0000 0x1d08_0000 rsvd 0xbf7f_ffff 0x1f7f_ffff 0xbf80_0000 0x1f80_0000 peripherals peripherals p eripherals peripherals peripherals 0xbf8f_ffff 0x1f8f_ffff 0xbf90_0000 0x1f90_0000 rsvd rsvd rsvd rsvd rsvd 0xbfb_ffff 0x1fb_ffff 0xbfc0_0000 0x1fc0_0000 boot flash boot fl ash boot flash boot flash boot flash 0xbfc0_2fff 0x1fc0_2fff 0xbfc0_3000 0x1fc0_3000 rsvd rsvd rsvd rsvd rsvd 0xbfff_efff 0x1fff_efff 0xbfff_f000 0x1fff_f000 test flash test flash test flash test flash test flash 0xbfff_ffff 0x1fff_ffff note 1: not available in kseg1 if mapped to useg/kuseg (i.e. bmxdudba or bmxdupba non-zero). 2: not available in kseg1 if mapped in useg/kuseg (i.e. bmxpupba non-zero).
? 2008 microchip technology inc. preliminary ds61143e-page 113 pic32mx3xx/4xx 6.6.3 peripheral registers locations table 6-6 contains the peripheral address map for the pic32mx3xx/4xx device. peripherals located on the pb bus are mapped to 512 byte boundaries. peripher- als on the fpb bus are mapped to 4 kbyte boundaries. table 6-6: peripheral address table peripheral virtual address physical address start end start end wdt bf80_0000 bf80_01ff 1f80_0000 1f80_01ff rtcc bf80_0200 bf80_03ff 1f80_0200 1f80_03ff tmr1 bf80_0600 bf80_07ff 1f80_0600 1f80_07ff tmr2 bf80_0800 bf80_09ff 1f80_0800 1f80_09ff tmr3 bf80_0a00 bf80_0bff 1f80_0a00 1f80_0bff tmr4 bf80_0c00 bf80_0dff 1f80_0c00 1f80_0dff tmr5 bf80_0e00 bf80_0fff 1f80_0e00 1f80_0fff input capture1 bf80_2000 bf80_21ff 1f80_2000 1f80_21ff input capture2 bf80_2200 bf80_23ff 1f80_2200 1f80_23ff input capture3 bf80_2400 bf80_25ff 1f80_2400 1f80_25ff input capture4 bf80_2600 bf80_27ff 1f80_2600 1f80_27ff input capture5 bf80_2800 bf80_29ff 1f80_2800 1f80_29ff output compare1 bf80_3000 bf80_31ff 1f80_3000 1f80_31ff output compare2 bf80_3200 bf80_33ff 1f80_3200 1f80_33ff output compare3 bf80_3400 bf80_35ff 1f80_3400 1f80_35ff output compare4 bf80_3600 bf80_37ff 1f80_3600 1f80_37ff output compare5 bf80_3800 bf80_39ff 1f80_3800 1f80_39ff i2c1 bf80_5000 bf80_51ff 1f80_5000 1f80_51ff i2c2 bf80_5200 bf80_53ff 1f80_5200 1f80_53ff spi1 bf80_5800 bf80_59ff 1f80_5800 1f80_59ff spi2 bf80_5a00 bf80_5bff 1f80_5a00 1f80_5bff uart1 bf80_6000 bf80_61ff 1f80_6000 1f80_61ff uart2 bf80_6200 bf80_63ff 1f80_6200 1f80_63ff parallel master port bf80_7000 bf80_71ff 1f80_7000 1f80_71ff adc bf80_9000 bf80_91ff 1f80_9000 1f80_91ff comparator voltage ref bf80_9800 bf80_99ff 1f80_9800 1f80_99ff comparator bf80_a000 bf80_a1ff 1f80_a000 1f80_a1ff oscillator bf80_f000 bf80_f1ff 1f80_f000 1f80_f1ff configuration bf80_f200 bf80_f3ff 1f80_f200 1f80_f3ff flash (nvm) bf80_f400 bf80_f5ff 1f80_f400 1f80_f5ff reset bf80_f600 bf80_f7ff 1f80_f600 1f80_f7ff interrupts bf88_1000 bf88_1fff 1f88_1000 1f88_1fff bus matrix bf88_2000 bf88_2fff 1f88_2000 1f88_2fff dma bf88_3000 bf88_3fff 1f88_3000 1f88_3fff prefetch cache bf88_4000 bf88_4fff 1f88_4000 1f88_4fff usb bf88_5000 bf88_53ff 1f88_5000 1f88_53ff gpio bf88_6000 bf88_61ff 1f88_6000 1f88_61ff
pic32mx3xx/4xx ds61143e-page 114 preliminary ? 2008 microchip technology inc. notes:
? 2008 microchip technology inc. preliminary ds61143e-page 115 pic32mx3xx/4xx 7.0 flash program memory the pic32mx3xx/4xx of devices contain internal pro- gram flash memory for executing user code. there are three methods by which the user can program this memory: 1. run-time self programming (rtsp) 2. in-circuit serial programming? (icsp?) 3. ejtag programming rtsp is performed by software executing from either flash or ram memory. ejtag is performed using the ejtag port of the device and a ejtag capable pro- grammer. icsp is performed using a serial data con- nection to the device and allows much faster programming times than rtsp. rtsp techniques are described in this chapter. the icsp and ejtag meth- ods are described in the ? pic32mx3xx/4xx program- ming specification ? (ds61145) document, which may be downloaded from the microchip web site. note: this data sheet summarizes the features of the pic32mx3xx/4xx family of devices. it is not intended to be a comprehensive refer- ence source. refer to the ?pic32mx family reference manual? (ds61132) for a detailed description of this peripheral.
pic32mx3xx/4xx ds61143e-page 116 preliminary ? 2008 microchip technology inc. 7.1 flash controller registers table 7-1: flash controller sfr summary virtual address name bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 bf80_f400 nvmcon 31:24 ? ? ? ? ? ? ? ? 23:16 ? ? ? ? ? ? ? ? 15:8 nvmwr nvmwren nvmerr lvderr lvdstat ? ? ? 7:0 ? ? ? ? nvmop<3:0> bf80_f404 nvmconclr 31:0 write clears selected bi ts in nvmcon, read yields undefined value bf80_f408 nvmconset 31:0 write sets selected bits in nvmcon, read yields undefined value bf80_f40c nvmcon-inv 31:0 write inverts selected bits in nvmcon, read yields undefined value bf80_f410 nvmkey 31:24 nvmkey<31:24> 23:16 nvmkey<23:16> 15:8 nvmkey<15:8> 7:0 nvmkey<7:0> bf80_f420 nvmaddr 31:24 nvmaddr<31:24> 23:16 nvmaddr<23:16> 15:8 nvmaddr<15:8> 7:0 nvmaddr<7:0> bf80_f424 nvmaddr- clr 31:0 write clears selected bits in nvmaddr, read yields undefined value bf80_f428 nvmaddr- set 31:0 write sets selected bits in nvmaddr, read yields undefined value bf80_f42c nvmaddr inv 31:0 write inverts selected bits in nvmaddr, read yields undefined value bf80_f430 nvmdata 31:24 nvmdata<31:24> 23:16 nvmdata<23:16> 15:8 nvmdata<15:8> 7:0 nvmdata<7:0> bf80_f440 nvmsr- caddr 31:24 nvmsrcaddr<31:24> 23:16 nvmsrcaddr<23:16> 15:8 nvmsrcaddr<15:8> 7:0 nvmsrcaddr<7:0> table 7-2: flash controller interrupt register summary virtual address name bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 bf88_1070 iec1 31:24 ? ? ? ? ? ? usbie fceie bf88_1040 ifs1 31:24 ? ? ? ? ? ? usbif fceif bf88_1140 ipc11 7:0 ? ? ? fceip<2:0> fceis<1:0> note: this summary table contains partial regist er definitions that only pertain to the flash memory controller peripheral. refer to the ? pic32mx family reference manual ? (ds61132) for a detailed description of these registers.
? 2008 microchip technology inc. preliminary ds61143e-page 117 pic32mx3xx/4xx register 7-1: nvmcon: programming control register r-x r-x r-x r-x r-x r-x r-x r-x ? ? ? ? ? ? ? ? bit 31 bit 24 r-x r-x r-x r-x r-x r-x r-x r-x ? ? ? ? ? ? ? ? bit 23 bit 16 r/w-0 r/w-0 r-0 r-0 r-0 r-x r-x r-x nvmwr nvmwren nvmerr lvderr lvdstat ? ? ? bit 15 bit 8 r-x r-x r-x r-x r/w-0 r/w-0 r/w-0 r/w-0 ? ? ? ? nvmop3 nvmop2 nvmop1 nvmop0 bit 7 bit 0 legend: r = readable bit w = writable bit p = programmable bit r = reserved bit u = unimplemented bit -n = bit value at por: (?0?, ?1?, x = unknown) bit 31-16 reserved: write ? 0 ?; ignore read bit 15 nvmwr: write control bit this bit is writable when nvmwren = 1 and the unlock sequence is followed. 1 = initiate a flash operation (hardware clears this bit when the operation completes.) 0 = flash operation complete or inactive note: wait at least 500 nsec after detecting a ? 0 ? in nvmwr bit before writing to any nvm registers. bit 14 nvmwren: write enable bit 1 = enables writes to nvmwr bit and enables lvd circuit 0 = disables writes to nvmwr bit and disables lvd circuit note: this is the only bit in this register that is reset by a device reset. bit 13 nvmerr: write error bit 1 = program or erase sequence did not complete successfully 0 = program or erase sequence completed normally note: cleared by setting nvmop==0000b, and initiating a flash operation (i.e., nvmwr). bit 12 lvderr: low-voltage detect error bit (lvd circuit must be enabled) this error is only captured for programming/erase operations 1 = low-voltage detected 0 = voltage level ok for programming note: cleared by setting nvmop==0000b, and initiating a flash operation (i.e., nvmwr). bit 11 lvdstat: low-voltage detect status bit (lvd circuit must be enabled) this bit is read-only and is automatically set by hardware 1 = low-voltage event active 0 = low-voltage event not active note: cleared by setting nvmop==0000b, and initiating a flash operation (i.e., nvmwr). bit 10-4 reserved: write ? 0 ?; ignore read
pic32mx3xx/4xx ds61143e-page 118 preliminary ? 2008 microchip technology inc. bit 3-0 nvmop<3:0> : nvm operation bits 0111 = reserved 0110 = no operation 0101 = program flash (pfm) erase operation: erases pfm, if all pages are not write-protected 0100 = page erase operation: erases page selected by nvmaddr, if it is not write-protected 0011 = row program operation: programs row selected by nvmaddr, if it is not write-protected 0010 = no operation 0001 = word program operation: programs word selected by nvmadd,r if it is not write-protected 0000 = no operation register 7-1: nvmcon: programming control register (continued)
? 2008 microchip technology inc. preliminary ds61143e-page 119 pic32mx3xx/4xx 7.2 rtsp operation rtsp allows the user code to modify flash program memory contents. the device flash memory is divided into two logical flash partitions: the program flash memory (pfm), and the boot flash memory (bfm). the last page in boot flash memory contains the debug page, which is reserved for use by the debugger tool while debugging. the program flash array for the pic32mx3xx/4xx device is built up of a series of rows. a row contains 128 32-bit instruction words or 512 bytes. a group of 8 rows compose a page; which, therefore, contains 8 512 = 4096 bytes or 1024 instruction words. a page of flash is the smallest unit of memory that can be erased at a single time. the program flash array can be pro- grammed in one of two ways: ? row programming, with 128 instruction words at a time. ? word programming, with 1 instruction word at a time. the cpu stalls (waits) until the programming opera- tion is finished. the cpu will not execute any instruc- tion, or respond to interrupts, during this time. if any interrupts occur during the programming cycle, they remain pending until the cycle completes. 7.3 control registers there are two sfrs used to erase and write the pfm: nvmcon and nvmkey. the nvmcon register (register 7-1) controls which blocks are to be erased, which memory block is to be programmed and the start of the programming cycle. nvmkey is a write-only register that is used for write- protection. to start a pr ogramming or erase sequence, the user must consecutively write 0xaa996655 and 0x556699aa to the nvmkey register. interrupts should be disabled. refer to section 7.4 ?programming operations? for further details. 7.4 programming operations a complete programming sequence is necessary for programming or erasing the internal flash in rtsp mode. a programming operation is nominally 5 ms in duration and the processor stalls ( waits ) until the operation is finished. setting the nvmwr bit (nvm- con<15>) starts the operation, and the nvmwr bit is automatically cleared when the operation is finished. note: a minimum v dd requirement for flash erase and write operations is required. refer to section 30.1 ?dc characteris- tics? for details.
pic32mx3xx/4xx ds61143e-page 120 preliminary ? 2008 microchip technology inc. 7.4.1 programming algorithm the user can program one row of program flash memory at a time. to do this, it is necessary to erase the 8-row erase block containing the desired row. the general process is: 1. read eight rows of program memory (1024 instructions) and store in data ram. 2. update the program data in ram with the desired new data. 3. erase the page (see example 7-1): 4. write the first 128 words from data ram into the program memory buffers (see example 7-1). 5. repeat steps 4 and 5, using the next available 128 words from the block in data ram by incre- menting the value in nvmaddr and nvmasrcaddr, until all 1024 instructions are written back to flash memory. for protection against accidental operations, the write initiate sequence for nvmkey must be used to allow any erase or program operation to proceed. after the programming command has been executed, the user must wait for the programming time until programming is complete. example 7-1: erasing flash page unsigned int nvmunlock (unsigned int nvmop) { unsigned int status; // suspend or disable all interrupts asm volatile (?di %0? : ?=r? (status)); // enable flash write/erase operations and select // flash operation to perform nvmcon = nvmop; // write keys nvmkey = 0xaa996655; nvmkey = 0x556699aa; // start the operation using the set register nvmconset = 0x8000; // wait for operation to complete while (nvmcon & 0x8000); // restore interrupts if (status & 0x00000001 asm volatile (?ei?); else asm volatile (?di?); // return nvmerr and lvderr error status bits return (nvmcon & 0x3000) } unsigned int nvmerasepage(void* address) { unsigned int res; // set nvmaddr to the start address of page to erase nvmaddr = (unsigned int) address; // unlock and erase page res = nvmunlock(0x4004); // return result return res; }
? 2008 microchip technology inc. preliminary ds61143e-page 121 pic32mx3xx/4xx example 7-2: row prog ramming sequence unsigned int nvmunlock (unsigned int nvmop) { unsigned int status; // suspend or disable all interrupts asm volatile (?di %0? : ?=r? (status)); // enable flash write/erase operations and select // flash operation to perform nvmcon = nvmop; // write keys nvmkey = 0xaa996655; nvmkey = 0x556699aa; // start the operation using the set register nvmconset = 0x8000; // wait for operation to complete while (nvmcon & 0x8000); // restore interrupts if (status & 0x00000001 asm volatile (?ei?); else asm volatile (?di?); // return nvmerr and lvderr error status bits return (nvmcon & 0x3000) } unsigned int nvmwriterow (void* address, void* data) { unsigned int res; // set nvmaddr to start address of row to program nvmaddr = (unsigned int) address; // set nvmsrcaddr to the sram data buffer address nvmsrcaddr = (unsigned int) data; // unlock and write row res = nvmunlock(0x4003); // return result return res; }
pic32mx3xx/4xx ds61143e-page 122 preliminary ? 2008 microchip technology inc. example 7-3: word programming sequence unsigned int nvmunlock (unsigned int nvmop) { unsigned int status; // suspend or disable all interrupts asm volatile (?di %0? : ?=r? (status)); // enable flash write/erase operations and select // flash operation to perform nvmcon = nvmop; // write keys nvmkey = 0xaa996655; nvmkey = 0x556699aa; // start the operation using the set register nvmconset = 0x8000; // wait for operation to complete while (nvmcon & 0x8000); // restore interrupts if (status & 0x00000001 asm volatile (?ei?); else asm volatile (?di?); // return nvmerr and lvderr error status bits return (nvmcon & 0x3000) } unsigned int nvmwriteword (void* address, unsigned int data) { unsigned int res; // load data into nvmdata register nvmdata = data; // load address to program into nvmaddr register nvmaddr = (unsigned int) address; // unlock and write word res = nvmunlock (0x4001); // return result return res; }
? 2008 microchip technology inc. preliminary ds61143e-page 123 pic32mx3xx/4xx example 7-4: program flash erase sequence unsigned int nvmunlock (unsigned int nvmop) { unsigned int status; // suspend or disable all interrupts asm volatile (?di %0? : ?=r? (status)); // enable flash write/erase operations and select // flash operation to perform nvmcon = nvmop; // write keys nvmkey = 0xaa996655; nvmkey = 0x556699aa; // start the operation using the set register nvmconset = 0x8000; // wait for operation to complete while (nvmcon & 0x8000); // restore interrupts if (status & 0x00000001 asm volatile (?ei?); else asm volatile (?di?); // return nvmerr and lvderr error status bits return (nvmcon & 0x3000) } unsigned int nvmerasepfm(void) { unsigned int res; // unlock and erase program flash res = nvmunlock(0x4005); // return result return res; }
pic32mx3xx/4xx ds61143e-page 124 preliminary ? 2008 microchip technology inc. notes:
? 2008 microchip technology inc. preliminary ds61143e-page 125 pic32mx3xx/4xx 8.0 interrupts pic32mx3xx/4xx generates interrupt requests in response to interrupt events from peripheral modules. the interrupt control module exists external to the cpu logic and prioritizes the interrupt events before presenting them to the cpu. the pic32mx3xx/4xx interrupts module includes the following features: ? up to 96 interrupt sources ? up to 64 interrupt vectors ? single and multi-vector mode operations ? 5 external interrupts with edge polarity control ? interrupt proximity timer ? module freeze in debug mode ? 7 user-selectable priority levels for each vector ? 4 user-selectable subpriority levels within each priority ? dedicated shadow set for highest priority level ? software can generate any interrupt ? user-configurable interrupt vector table location ? user-configurable interrupt vector spacing figure 8-1: interrup t controller module note: this data sheet summarizes the features of the pic32mx3xx/4xx family of devices. it is not intended to be a comprehensive refer- ence source. refer to the ?pic32mx family reference manual? (ds61132) for a detailed description of this peripheral. note: several of the registers cited in this section are not in the interrupt controller module. these registers (and bits) are associated with the cpu. details about them are available in section 2.0 "pic32mx mcu". to avoid confusion, a typographic distinction is made for registers in the cpu. the register names in this section, and all other sections of this manual, are signified by uppercase letters only.cpu register names are signified by upper and lowercase letters. for example, intstat is an interrupts register; whereas, intctl is a cpu register. interrupt controller interrupt requests vector number cpu core priority level shadow set number
pic32mx3xx/4xx ds61143e-page 126 preliminary ? 2008 microchip technology inc. 8.1 control registers the interrupts module consists of the following special function registers (sfrs): ? intcon: interrupt control register intconclr, intconset, intconinv: atomic bit manipulation, write-only registers for intcon ? intstat: interrupt status register intstatclr, intstatset, intstatinv: atomic bit manipulation, write-only registers for intstat ? iptmr: interrupt proximity timer register iptmrclr, iptmrset, iptmrninv: atomic bit manipulation, write-only registers for iptmr ? ifs0, ifs1: interrupt flag status registers ifsxclr, ifsxset, ifsxinv: atomic bit manipulation, write-only registers for ifsx ? iec0, iec1: interrupt enable control registers iecxclr, iecxset, iecxinv: atomic bit manipulation, write-only registers for iecx ? ipc0 - ipc11: interrupt priority control registers ipcxclr, ipcxset, ipcxinv: atomic bit manipulation, write-only registers for ipcx the following table provides a brief summary of inter- rupts module related registers. corresponding regis- ters appear after the summary, followed by a detailed description of each register. note: each pic32mx device variant may have one or more interrupt channels. an ?x? used in the names of control/status bits and registers denotes the particular chan- nel. refer to the specific device data sheets for more details. table 8-1: interrupt sfr summary virtual address name bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 bf88_1000 intcon 31:24 ? ? ? ? ? ? ? ? 23:16 ? ? ? ? ? ? ?ss0 15:8 ?frz ?mvec ?tpc<2:0> 7:0 ? ? ? int4ep int3ep int2ep int1ep int0ep bf88_1004 intconclr 31:0 write clears the selected bits in intcon, read yields undefined value bf88_1008 intconset 31:0 write sets the selected bits in intcon, read yields undefined value bf88_100c intconinv 31:0 write inverts the selected bits in intcon, read yields undefined value bf88_1010 intstat 31:24 ? ? ? ? ? ? ? ? 23:16 ? ? ? ? ? ? ? ? 15:8 ? ? ? ? ? ripl<2:0> 7:0 ? ?vec<5:0> bf88_1014 intstatclr 31:0 write clears the selected bits in intstat, read yields undefined value bf88_1018 intstatset 31:0 write sets the selected bits in intstat, read yields undefined value bf88_101c intstatinv 31:0 write inverts the selected bits in intstat, read yields undefined value bf88_1020 iptmr 31:24 23:16 iptmr<31:0> 15:8 7:0 bf88_1024 iptmrclr 31:0 write clears the selected bits in iptmr, read yields undefined value bf88_1028 iptmrset 31:0 write clears the selected bits in iptmr, read yields undefined value bf88_102c iptmrinv 31:0 write clears the selected bits in iptmr, read yields undefined value bf88_1030 ifs0 31:24 i2c1mif i2c1sif i2c1bif u1txif u1rxif u1eif spi1rxif spi1txif 23:16 spi1eif oc5if ic5if t5if int4if oc4if ic4if t4if 15:8 int3if oc3if ic3if t3if int2if oc2if ic2if t2if 7:0 int1if oc1if ic1if t1if int0if cs1if cs0if ctif bf88_1034 ifs0clr 31:0 write clears the selected bits in ifs0, read yields undefined value bf88_1038 ifs0set 31:0 write sets the selected bits in ifs0, read yields undefined value bf88_103c ifs0inv 31:0 write inverts the selected bits in ifs0, read yields undefined value
? 2008 microchip technology inc. preliminary ds61143e-page 127 pic32mx3xx/4xx bf88_1040 ifs1 31:24 ? ? ? ? ? ? usbif fceif 23:16 ? ? ? ? dma3if dma2if dma1if dma0if 15:8 rtccif fscmif i2c2mif i2c2sif i2c2bif u2txif u2rxif u2eif 7:0 spi2rxif spi2txif spi2eif cmp2if cmp1if pmpif ad1if cnif bf88_1044 ifs1clr 31:0 write clears the selected bits in ifs1, read yields undefined value bf88_1048 ifs1set 31:0 write sets the selected bits in ifs1, read yields undefined value bf88_104c ifs1inv 31:0 write inverts the selected bits in ifs1, read yields undefined value bf88_1060 iec0 31:24 i2c1mie i2c1sie i2c1bie u1txie u1rxie u1eie spi1rxie spi1txie 23:16 spi1eie oc5ie ic5ie t5ie int4ie oc4ie ic4ie t4ie 15:8 int3ie oc3ie ic3ie t3ie int2ie oc2ie ic2ie t2ie 7:0 int1ie oc1ie ic1ie t1ie int0ie cs1ie cs0ie ctie bf88_1064 iec0clr 31:0 write clears the selected bits in iec0, read yields undefined value bf88_1068 iec0set 31:0 write sets the selected bits in iec0, read yields undefined value bf88_106c iec0inv 31:0 write inverts the selected bits in iec0, read yields undefined value bf88_1070 iec1 31:24 ? ? ? ? ? ?usbiefceie 23:16 ? ? ? ? dma3ie dma2ie dma1ie dma0ie 15:8 rtccie fscmie i2c2mie i2c2sie i2c2bie u2txie u2rxie u2eie 7:0 spi2rxie spi2txie spi2eie cmp2ie cmp1ie pmpie ad1ie cnie bf88_1074 iec1clr 31:0 write clears the selected bits in iec1, read yields undefined value bf88_1078 iec1set 31:0 write sets the selected bits in iec1, read yields undefined value bf88_107c iec1inv 31:0 write inverts the selected bits in iec1, read yields undefined value bf88_1090 ipc0 31:24 ? ? ? int0ip<2:0> int0is<1:0> 23:16 ? ? ? cs1ip<2:0> cs1is<1:0> 15:8 ? ? ? cs0ip<2:0> cs0is<1:0> 7:0 ? ? ? ctip<2:0> ctis<1:0> bf88_1094 ipc0clr 31:0 write clears the selected bits in ipc0, read yields undefined value bf88_1098 ipc0set 31:0 write sets the selected bits in ipc0, read yields undefined value bf88_109c ipc0inv 31:0 write inverts the selected bits in ipc0, read yields undefined value bf88_10a0 ipc1 31:24 ? ? ? int1ip<2:0> int1is<1:0> 23:16 ? ? ? oc1ip<2:0> oc1is<1:0> 15:8 ? ? ? ic1ip<2:0> ic1is<1:0> 7:0 ? ? ? t1ip<2:0> t1is<1:0> bf88_10a4 ipc1clr 31:0 write clears the selected bits in ipc1, read yields undefined value bf88_10a8 ipc1set 31:0 write sets the selected bits in ipc1, read yields undefined value bf88_10ac ipc1inv 31:0 write inverts the selected bits in ipc1, read yields undefined value bf88_10b0 ipc2 31:24 ? ? ? int2ip<2:0> int2is<1:0> 23:16 ? ? ? oc2ip<2:0> oc2is<1:0> 15:8 ? ? ? ic2ip<2:0> ic2is<1:0> 7:0 ? ? ? t2ip<2:0> t2is<1:0> bf88_10b4 ipc2clr 31:0 write clears the selected bits in ipc2, read yields undefined value bf88_10b8 ipc2set 31:0 write sets the selected bits in ipc2, read yields undefined value bf88_10bc ipc2inv 31:0 write inverts the selected bits in ipc2, read yields undefined value table 8-1: interrupt sfr summary (continued) virtual address name bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0
pic32mx3xx/4xx ds61143e-page 128 preliminary ? 2008 microchip technology inc. bf88_10c0 ipc3 31:24 ? ? ? int3ip<2:0> int3is<1:0> 23:16 ? ? ? oc3ip<2:0> oc3is<1:0> 15:8 ? ? ? ic3ip<2:0> ic3is<1:0> 7:0 ? ? ? t3ip<2:0> t3is<1:0> bf88_10c4 ipc3clr 31:0 write clears the selected bits in ipc3, read yields undefined value bf88_10c8 ipc3set 31:0 write sets the selected bits in ipc3, read yields undefined value bf88_10cc ipc3inv 31:0 write inverts the selected bits in ipc3, read yields undefined value bf88_10d0 ipc4 31:24 ? ? ? int4ip<2:0> int4is<1:0> 23:16 ? ? ? oc4ip<2:0> oc4is<1:0> 15:8 ? ? ? ic4ip<2:0> ic4is<1:0> 7:0 ? ? ? t4ip<2:0> t4is<1:0> bf88_10d4 ipc4clr 31:0 write clears the selected bits in ipc4, read yields undefined value bf88_10d8 ipc4set 31:0 write sets the selected bits in ipc4, read yields undefined value bf88_10dc ipc4inv 31:0 write inverts the selected bits in ipc4, read yields undefined value bf88_10e0 ipc5 31:24 ? ? ? spi1ip<2:0> spi1is<1:0> 23:16 ? ? ? oc5ip<2:0> oc5is<1:0> 15:8 ? ? ? ic5ip<2:0> ic5is<1:0> 7:0 ? ? ? t5ip<2:0> t5is<1:0> bf88_10e4 ipc5clr 31:0 write clears the selected bits in ipc5, read yields undefined value bf88_10e8 ipc5set 31:0 write sets the selected bits in ipc5, read yields undefined value bf88_10ec ipc5inv 31:0 write inverts the selected bits in ipc5, read yields undefined value bf88_10f0 ipc6 31:24 ? ? ? ad1ip<2:0> ad1is<1:0> 23:16 ? ? ? cnip<2:0> cnis<1:0> 15:8 ? ? ? i2c1ip<2:0> i2c1is<1:0> 7:0 ? ? ? u1ip<2:0> u1is<1:0> bf88_10f4 ipc6clr 31:0 write clears the selected bits in ipc6, read yields undefined value bf88_10f8 ipc6set 31:0 write sets the selected bits in ipc6, read yields undefined value bf88_10fc ipc6inv 31:0 write inverts the selected bits in ipc6, read yields undefined value bf88_1100 ipc7 31:24 ? ? ? spi2ip<2:0> spi2is<1:0> 23:16 ? ? ? cmp2ip<2:0> cmp2is<1:0> 15:8 ? ? ? cmp1ip<2:0> cmp1is<1:0> 7:0 ? ? ? pmpip<2:0> pmpis<1:0> bf88_1104 ipc7clr 31:0 write clears the selected bits in ipc7, read yields undefined value bf88_1108 ipc7set 31:0 write sets the selected bits in ipc7, read yields undefined value bf88_110c ipc7inv 31:0 write inverts the selected bits in ipc7, read yields undefined value bf88_1110 ipc8 31:24 ? ? ? rtccip<2:0> rtccis<1:0> 23:16 ? ? ? fscmip<2:0> fscmis<1:0> 15:8 ? ? ? i2c2ip<2:0> i2c2is<1:0> 7:0 ? ? ? u2ip<2:0> u2is<1:0> bf88_1114 ipc8clr 31:0 write clears the selected bits in ipc8, read yields undefined value bf88_1118 ipc8set 31:0 write sets the selected bits in ipc8, read yields undefined value bf88_111c ipc8inv 31:0 write inverts the selected bits in ipc8, read yields undefined value table 8-1: interrupt sfr summary (continued) virtual address name bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0
? 2008 microchip technology inc. preliminary ds61143e-page 129 pic32mx3xx/4xx bf88_1120 ipc9 31:24 ? ? ? dma3ip<2:0> dma3is<1:0> 23:16 ? ? ? dma2ip<2:0> dma2is<1:0> 15:8 ? ? ? dma1ip<2:0> dma1is<1:0> 7:0 ? ? ? dma0ip<2:0> dma0is<1:0> bf88_1124 ipc9clr 31:0 write clears the selected bits in ipc9, read yields undefined value bf88_1128 ipc9set 31:0 write sets the selected bits in ipc9, read yields undefined value bf88_112c ipc9inv 31:0 write inverts the selected bits in ipc9, read yields undefined value bf88_1130 ipc10 31:24 ? ? ? ? _ 23:16 ? ? ? ? ? 15:8 ? ? ? ? _ 7:0 ? ? ? ? ? bf88_1134 ipc10clr 31:0 write clears the selected bits in ipc10, read yields undefined value bf88_1138 ipc10set 31:0 write sets the selected bits in ipc10, read yields undefined value bf88_113c ipc10inv 31:0 write inverts the selected bits in ipc10, read yields undefined value bf88_1140 ipc11 31:24 ? ? ? ? _ 23:16 ? ? ? ? ? 15:8 ? ? ? usbip<2:0> usbis<1:0> 7:0 ? ? ? fceip<2:0> fceis<1:0> bf88_1144 ipc11clr 31:0 write clears the selected bits in ipc11, read yields undefined value bf88_1148 ipc11set 31:0 write sets the selected bits in ipc11, read yields undefined value bf88_114c ipc11inv 31:0 write inverts the selected bits in ipc11, read yields undefined value table 8-1: interrupt sfr summary (continued) virtual address name bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0
pic32mx3xx/4xx ds61143e-page 130 preliminary ? 2008 microchip technology inc. register 8-1: intcon: interrupt control register r-x r-x r-x r-x r-x r-x r-x r-x ? ? ? ? ? ? ? ? bit 31 bit 24 r-x r-x r-x r-x r-x r-x r-x r/w-0 ? ? ? ? ? ? ? ss0 bit 23 bit 16 r-x r/w-0 r-x r/w-0 r-x r/w-0 r/w-0 r/w-0 ?frz ? mvec ?tpc<2:0> bit 15 bit 8 r-x r-x r-x r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ? int4ep int3ep int2ep int1ep int0ep bit 7 bit 0 legend: r = readable bit w = writable bit p = programmable bit r = reserved bit u = unimplemented bit -n = bit value at por (?0?, ?1?, x = unknown) bit 31-17 reserved: write ? 0 ?; ignore read bit 16 ss0: single vector shadow register set bit 1 = single vector is presented with a shadow register set 0 = single vector is not presented with a shadow register set bit 15 reserved: write ? 0 ?; ignore read bit 14 frz: freeze in debug exception mode bit 1 = freeze operation when cpu is in debug exception mode 0 = continue operation even when cpu is in debug exception mode note: frz is writable in debug exception mode only, it is forced to ? 0 ? in normal mode. bit 13 reserved: write ? 0 ?; ignore read bit 12 mvec: multi-vector configuration bit 1 = interrupt controller configured for multi-vectored mode 0 = interrupt controller configured for single vectored mode bit 11 reserved: write ? 0 ?; ignore read bit 10-8 tpc<2:0>: temporal proximity control bits 111 = interrupt of group priority 7 or lower starts the ip timer 110 = interrupt of group priority 6 or lower starts the ip timer 101 = interrupt of group priority 5 or lower starts the ip timer 100 = interrupt of group priority 4 or lower starts the ip timer 011 = interrupt of group priority 3 or lower starts the ip timer 010 = interrupt of group priority 2 or lower starts the ip timer 001 = interrupt of group priority 1 starts the ip timer 000 = disables proximity timer bit 7-5 reserved: write ? 0 ?; ignore read bit 4 int4ep: external interrupt 4 edge polarity control bit 1 = rising edge 0 = falling edge
? 2008 microchip technology inc. preliminary ds61143e-page 131 pic32mx3xx/4xx bit 3 int3ep: external interrupt 3 edge polarity control bit 1 = rising edge 0 = falling edge bit 2 int2ep: external interrupt 2 edge polarity control bit 1 = rising edge 0 = falling edge bit 1 int1ep: external interrupt 1 edge polarity control bit 1 = rising edge 0 = falling edge bit 0 int0ep: external interrupt 0 edge polarity control bit 1 = rising edge 0 = falling edge register 8-1: intcon: interrupt control register (continued)
pic32mx3xx/4xx ds61143e-page 132 preliminary ? 2008 microchip technology inc. register 8-2: intstat: interrupt status register r-x r-x r-x r-x r-x r-x r-x r-x ? ? ? ? ? ? ? ? bit 31 bit 24 r-x r-x r-x r-x r-x r-x r-x r-x ? ? ? ? ? ? ? ? bit 23 bit 16 r-x r-x r-x r-x r-x r-0 r-0 r-0 ? ? ? ? ? ripl<2:0> bit 15 bit 8 r-x r-x r-0 r-0 r-0 r-0 r-0 r-0 ? ? vec<5:0> bit 7 bit 0 legend: r = readable bit w = writable bit p = programmable bit r = reserved bit u = unimplemented bit -n = bit value at por (?0?, ?1?, x = unknown) bit 31-11 reserved: write ? 0 ?; ignore read bit 10-8 ripl<2:0>: requested priority level bits 000 ? 111 = the priority level of the latest interrupt presented to the cpu note : this value should only be used when the interrupt controller is configured for single vector mode. bit 5-0 vec: interrupt vector bits 00000 ? 11111 = the interrupt vector that is presented to the cpu note : this value should only be used when the interrupt controller is configured for single vector mode.
? 2008 microchip technology inc. preliminary ds61143e-page 133 pic32mx3xx/4xx register 8-3: iptmr: interrupt proximity timer register r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 iptmr<31:24> bit 31 bit 24 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 iptmr<23:16> bit 23 bit 16 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 iptmr<15:8> bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 iptmr<7:0> bit 7 bit 0 legend: r = readable bit w = writable bit p = programmable bit r = reserved bit u = unimplemented bit -n = bit value at por (?0?, ?1?, x = unknown) bit 31-0 iptmr: interrupt proximity timer reload bits used by the interrupt proximity timer as a reload value when the interrupt proximity timer is triggered by an interrupt event.
pic32mx3xx/4xx ds61143e-page 134 preliminary ? 2008 microchip technology inc. register 8-4: ifs0: interrupt flag status register 0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 i2c1mif i2csif i2cbif u1txif u1rxif u1eif spi1rxif spi1txif bit 31 bit 24 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 spi1eif oc5if ic5if t5if int4if oc4if ic4if t4if bit 23 bit 16 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 int3if oc3if ic3if t3if int2if oc2if ic2if t2if bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 int1if oc1if ic2if t1if int0if cs1if cs0if ctif bit 7 bit 0 legend: r = readable bit w = writable bit p = programmable bit r = reserved bit u = unimplemented bit -n = bit value at por (?0?, ?1?, x = unknown) bit 31 i2c1mif: i2c1 master interrupt request flag bit 1 = interrupt request has occurred 0 = no interrupt request has a occurred bit 30 i2csif: i2c1 slave interrupt request flag bit 1 = interrupt request has occurred 0 = no interrupt request has a occurred bit 29 i2cbif: i2c1 bus collision interrupt request flag bit 1 = interrupt request has occurred 0 = no interrupt request has a occurred bit 28 u1txif: uart1 transmitter interrupt request flag bit 1 = interrupt request has occurred 0 = no interrupt request has a occurred bit 27 u1rxif: uart1 receiver interrupt request flag bit 1 = interrupt request has occurred 0 = no interrupt request has a occurred bit 26 u1eif: uart1 error interrupt request flag bit 1 = interrupt request has occurred 0 = no interrupt request has a occurred bit 25 spi1rxif: spi1 receive interrupt request flag bit 1 = interrupt request has occurred 0 = no interrupt request has a occurred bit 24 spi1txif: spi1 transmitter interrupt request flag bit 1 = interrupt request has occurred 0 = no interrupt request has a occurred bit 23 spi1eif: spi1 error interrupt request flag bit 1 = interrupt request has occurred 0 = no interrupt request has a occurred
? 2008 microchip technology inc. preliminary ds61143e-page 135 pic32mx3xx/4xx bit 22 oc5if: output compare 5 interrupt request flag bit 1 = interrupt request has occurred 0 = no interrupt request has a occurred bit 21 ic5if: input compare 5 interrupt request flag bit 1 = interrupt request has occurred 0 = no interrupt request has a occurred bit 20 t5if: timer5 interrupt request flag bit 1 = interrupt request has occurred 0 = no interrupt request has a occurred bit 19 int4if: external interrupt 4 request flag bit 1 = interrupt request has occurred 0 = no interrupt request has a occurred bit 18 oc4if: output compare 4 interrupt request flag bit 1 = interrupt request has occurred 0 = no interrupt request has a occurred bit 17 ic4if: input compare 4 interrupt request flag bit 1 = interrupt request has occurred 0 = no interrupt request has a occurred bit 16 t4if: timer4 interrupt request flag bit 1 = interrupt request has occurred 0 = no interrupt request has a occurred bit 15 int3if: external interrupt 3 request flag bit 1 = interrupt request has occurred 0 = no interrupt request has a occurred bit 14 oc3if: output compare 3 interrupt request flag bit 1 = interrupt request has occurred 0 = no interrupt request has a occurred bit 13 ic3if: input compare 3 interrupt request flag bit 1 = interrupt request has occurred 0 = no interrupt request has a occurred bit 12 t3if: timer3 interrupt request flag bit 1 = interrupt request has occurred 0 = no interrupt request has a occurred bit 11 int2if: external interrupt 2 request flag bit 1 = interrupt request has occurred 0 = no interrupt request has a occurred bit 10 oc2if: output compare 2 interrupt request flag bit 1 = interrupt request has occurred 0 = no interrupt request has a occurred bit 9 ic2if: input compare 2 interrupt request flag bit 1 = interrupt request has occurred 0 = no interrupt request has a occurred bit 8 t2if: timer2 interrupt request flag bit 1 = interrupt request has occurred 0 = no interrupt request has a occurred bit 7 int1if: external interrupt 1 request flag bit 1 = interrupt request has occurred 0 = no interrupt request has a occurred bit 6 oc1if: output compare 1 interrupt request flag bit 1 = interrupt request has occurred 0 = no interrupt request has a occurred register 8-4: ifs0: interrupt fla g status register 0 (continued)
pic32mx3xx/4xx ds61143e-page 136 preliminary ? 2008 microchip technology inc. bit 5 ic1if: input compare 1 interrupt request flag bit 1 = interrupt request has occurred 0 = no interrupt request has a occurred bit 4 t1if: timer1 interrupt request flag bit 1 = interrupt request has occurred 0 = no interrupt request has a occurred bit 3 int0if: external interrupt 0 request flag bit 1 = interrupt request has occurred 0 = no interrupt request has a occurred bit 2 cs1if: core software interrupt 1 request flag bit 1 = interrupt request has occurred 0 = no interrupt request has a occurred bit 1 cs0if: core software interrupt 0 request flag bit 1 = interrupt request has occurred 0 = no interrupt request has a occurred bit 0 ctif: core timer interrupt request flag bit 1 = interrupt request has occurred 0 = no interrupt request has a occurred register 8-4: ifs0: interrupt fla g status register 0 (continued)
? 2008 microchip technology inc. preliminary ds61143e-page 137 pic32mx3xx/4xx register 8-5: ifs1: interrupt flag status register 1 r-x r-x r-x r-x r-x r-x r/w-0 r/w-0 ? ? ? ? ? ? usbif fceif bit 31 bit 24 r-x r-x r-x r-x r/w-0 r/w-0 r/w-0 r/w-0 ? ? ? ? dma3if dma2if dma1if dma0if bit 23 bit 16 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 rtccif fscmif i2c2mif i2c2sif i2c2bif u2txif u2rxif u2eif bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 spi2rxif spi2txif spi2eif cmp2if cmp1if pmpif ad1if cnif bit 7 bit 0 legend: r = readable bit w = writable bit p = programmable bit r = reserved bit u = unimplemented bit -n = bit value at por (?0?, ?1?, x = unknown) bit 31-26 reserved: write ? 0 ?; ignore read bit 25 usbif: usb interrupt request flag bit 1 = interrupt request has occurred 0 = no interrupt request has a occurred bit 24 fceif: flash control event interrupt flag bit 1 = interrupt request has occurred 0 = no interrupt request has a occurred bit 23-20 reserved: write ? 0 ?; ignore read bit 19 dma3if: dma3 interrupt request flag bit 1 = interrupt request has occurred 0 = no interrupt request has a occurred bit 18 dma2if: dma2 interrupt request flag bit 1 = interrupt request has occurred 0 = no interrupt request has a occurred bit 17 dma1if: dma1 interrupt request flag bit 1 = interrupt request has occurred 0 = no interrupt request has a occurred bit 16 dma0if: dma0 interrupt request flag bit 1 = interrupt request has occurred 0 = no interrupt request has a occurred bit 15 rtccif: real time clock interrupt flag bit 1 = interrupt request has occurred 0 = no interrupt request has a occurred bit 14 fscmif: fail-safe clock monitor interrupt flag bit 1 = interrupt request has occurred 0 = no interrupt request has a occurred
pic32mx3xx/4xx ds61143e-page 138 preliminary ? 2008 microchip technology inc. bit 13 i2c2mif: i2c2 master interrupt request bit 1 = interrupt request has occurred 0 = no interrupt request has a occurred bit 12 i2c2sif: i2c2 slave interrupt request bit 1 = interrupt request has occurred 0 = no interrupt request has a occurred bit 11 i2c2bif: i2c2 bus collision interrupt request bit 1 = interrupt request has occurred 0 = no interrupt request has a occurred bit 10 u2txif: uart2 transmitter interrupt request bit 1 = interrupt request has occurred 0 = no interrupt request has a occurred bit 9 u2rxif: uart2 receiver interrupt request flag bit 1 = interrupt request has occurred 0 = no interrupt request has a occurred bit 8 u2eif: uart2 error interrupt request flag bit 1 = interrupt request has occurred 0 = no interrupt request has a occurred bit 7 spi2rxif: spi2 receiver interrupt request flag bit 1 = interrupt request has occurred 0 = no interrupt request has a occurred bit 6 spi2txif: spi2 transmitter interrupt request flag bit 1 = interrupt request has occurred 0 = no interrupt request has a occurred bit 5 spi2eif: spi2 error interrupt request flag bit 1 = interrupt request has occurred 0 = no interrupt request has a occurred bit 4 cmp2if: comparator 2 interrupt request flag bit 1 = interrupt request has occurred 0 = no interrupt request has a occurred bit 3 cmp1if: comparator 1 interrupt request flag bit 1 = interrupt request has occurred 0 = no interrupt request has a occurred bit 2 pmpif: parallel master port interrupt request flag bit 1 = interrupt request has occurred 0 = no interrupt request has a occurred bit 1 ad1if: analog-to-digital 1 interrupt request flag bit 1 = interrupt request has occurred 0 = no interrupt request has a occurred bit 0 cnif: input change interrupt request flag bit 1 = interrupt request has occurred 0 = no interrupt request has a occurred register 8-5: ifs1: interrupt fla g status register 1 (continued)
? 2008 microchip technology inc. preliminary ds61143e-page 139 pic32mx3xx/4xx register 8-6: iec0: interrupt enable control register 0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 i2c1mie i2c1sie i2c1bie u1txie u1rxie u1eie spi1rxie spi1txie bit 31 bit 24 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 spi1eie oc5ie ic5ie t5ie int4ie oc4ie ic4ie t4ie bit 23 bit 16 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 int3ie oc3ie ic3ie t3ie int2ie oc2ie ic2ie t2ie bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 int1ie oc1ie ic1ie t1ie int0ie cs1ie cs0ie ctie bit 7 bit 0 legend: r = readable bit w = writable bit p = programmable bit r = reserved bit u = unimplemented bit -n = bit value at por: (?0?, ?1?, x = unknown) bit 31 i2c2mie: i2c2 master interrupt enable bit 1 = interrupt is enabled 0 = interrupt is disabled bit 30 i2c1sie: i2c1 slave interrupt enable bit 1 = interrupt is enabled 0 = interrupt is disabled bit 29 i2c1bie: i2c1 bus collision interrupt enable bit 1 = interrupt is enabled 0 = interrupt is disabled bit 28 u1txie: uart1 transmitter interrupt enable bit 1 = interrupt is enabled 0 = interrupt is disabled bit 27 u1rxie: uart1 receiver interrupt enable bit 1 = interrupt is enabled 0 = interrupt is disabled bit 26 u1eie: uart1 error interrupt enable bit 1 = interrupt is enabled 0 = interrupt is disabled bit 25 spi1rxie: spi1 receive interrupt enable bit 1 = interrupt is enabled 0 = interrupt is disabled bit 24 spi1txie: spi1 transmitter interrupt enable bit 1 = interrupt is enabled 0 = interrupt is disabled bit 23 spi1eie: spi1 error interrupt enable bit 1 = interrupt is enabled 0 = interrupt is disabled
pic32mx3xx/4xx ds61143e-page 140 preliminary ? 2008 microchip technology inc. bit 22 oc5ie: output compare 5 interrupt enable bit 1 = interrupt is enabled 0 = interrupt is disabled bit 21 ic5ie: input compare 5 interrupt enable bit 1 = interrupt is enabled 0 = interrupt is disabled bit 20 t5ie: timer5 interrupt enable bit 1 = interrupt is enabled 0 = interrupt is disabled bit 19 int4ie: external interrupt 4 enable bit 1 = interrupt is enabled 0 = interrupt is disabled bit 18 oc4ie: output compare 4 interrupt enable bit 1 = interrupt is enabled 0 = interrupt is disabled bit 17 ic4ie: input compare 4 interrupt enable bit 1 = interrupt is enabled 0 = interrupt is disabled bit 16 t4ie: timer4 interrupt enable bit 1 = interrupt is enabled 0 = interrupt is disabled bit 15 int3ie: external interrupt 3 enable bit 1 = interrupt is enabled 0 = interrupt is disabled bit 14 oc3ie: output compare 3 interrupt enable bit 1 = interrupt is enabled 0 = interrupt is disabled bit 13 ic3ie: input compare 3 interrupt enable bit 1 = interrupt is enabled 0 = interrupt is disabled bit 12 t3ie: timer3 interrupt enable bit 1 = interrupt is enabled 0 = interrupt is disabled bit 11 int2ie: external interrupt 2 enable bit 1 = interrupt is enabled 0 = interrupt is disabled bit 10 oc2ie: output compare 2 interrupt enable bit 1 = interrupt is enabled 0 = interrupt is disabled bit 9 ic2ie: input compare 2 interrupt enable bit 1 = interrupt is enabled 0 = interrupt is disabled bit 8 t2ie: timer2 interrupt enable bit 1 = interrupt is enabled 0 = interrupt is disabled bit 7 int1ie: external interrupt 1 enable bit 1 = interrupt is enabled 0 = interrupt is disabled bit 6 oc1ie: output compare 1 interrupt enable bit 1 = interrupt is enabled 0 = interrupt is disabled register 8-6: iec0: interrupt enable control register 0 (continued)
? 2008 microchip technology inc. preliminary ds61143e-page 141 pic32mx3xx/4xx bit 5 ic1ie: input compare 1 interrupt enable bit 1 = interrupt is enabled 0 = interrupt is disabled bit 4 t1ie: timer1 interrupt enable bit 1 = interrupt is enabled 0 = interrupt is disabled bit 3 int0ie: external interrupt 0 enable bit 1 = interrupt is enabled 0 = interrupt is disabled bit 2 cs1ie: core software interrupt 1 enable bit 1 = interrupt is enabled 0 = interrupt is disabled bit 1 cs0ie: core software interrupt 0 enable bit 1 = interrupt is enabled 0 = interrupt is disabled bit 0 ctie: core timer interrupt enable bit 1 = interrupt is enabled 0 = interrupt is disabled register 8-6: iec0: interrupt enable control register 0 (continued)
pic32mx3xx/4xx ds61143e-page 142 preliminary ? 2008 microchip technology inc. register 8-7: iec1: interrupt enable control register 1 r-x r-x r-x r-x r-x r-x r-x r/w-0 ? ? ? ? ? ? usbie fceie bit 31 bit 24 r-x r-x r-x r-x r/w-0 r/w-0 r/w-0 r/w-0 ? ? ? ? dma3ie dma2ie dma1ie dma0ie bit 23 bit 16 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 rtccie fscmie i2c2mie i2c2sie i2c2bie u2txie u2rxie u2eie bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 spi2rxie spi2txie spi2eie cmp2ie cmp1ie pmpie ad1ie cnie bit 7 bit 0 legend: r = readable bit w = writable bit p = programmable bit r = reserved bit u = unimplemented bit -n = bit value at por (?0?, ?1?, x = unknown) bit 31-26 reserved: write ? 0 ?; ignore read bit 25 usbie: usb interrupt enable bit 1 = interrupt is enabled 0 = interrupt is disabled bit 24 fceie: flash control event interrupt enable bit 1 = interrupt is enabled 0 = interrupt is disabled bit 23-20 reserved: write ? 0 ?; ignore read bit 19 dma3ie: dma3 interrupt enable bit 1 = interrupt is enabled 0 = interrupt is disabled bit 18 dma2ie: dma2 interrupt enable bit 1 = interrupt is enabled 0 = interrupt is disabled bit 17 dma1ie: dma1 interrupt enable bit 1 = interrupt is enabled 0 = interrupt is disabled bit 16 dma0ie: dma0 interrupt enable bit 1 = interrupt is enabled 0 = interrupt is disabled bit 15 rtccie: real-time clock interrupt enable bit 1 = interrupt is enabled 0 = interrupt is disabled bit 14 fscmie: fail-safe clock monitor interrupt enable bit 1 = interrupt is enabled 0 = interrupt is disabled
? 2008 microchip technology inc. preliminary ds61143e-page 143 pic32mx3xx/4xx bit 13 i2c2mie: i2c2 master interrupt request bit 1 = interrupt is enabled 0 = interrupt is disabled bit 12 i2c2sie: i2c2 slave interrupt request bit 1 = interrupt is enabled 0 = interrupt is disabled bit 11 i2c2bie: i2c2 bus collision interrupt request bit 1 = interrupt is enabled 0 = interrupt is disabled bit 10 u2txie: uart2 transmitter interrupt request bit 1 = interrupt is enabled 0 = interrupt is disabled bit 9 u2rxie: uart2 receiver interrupt enable bit 1 = interrupt is enabled 0 = interrupt is disabled bit 8 u2eie: uart2 error interrupt enable bit 1 = interrupt is enabled 0 = interrupt is disabled bit 7 spi2rxie: spi2 receiver interrupt enable bit 1 = interrupt is enabled 0 = interrupt is disabled bit 6 spi2txie: spi2 transmitter interrupt enable bit 1 = interrupt is enabled 0 = interrupt is disabled bit 5 spi2eie: spi2 error interrupt enable bit 1 = interrupt is enabled 0 = interrupt is disabled bit 4 cmp2ie: comparator 2 interrupt enable bit 1 = interrupt is enabled 0 = interrupt is disabled bit 3 cmp1ie: comparator 1 interrupt enable bit 1 = interrupt is enabled 0 = interrupt is disabled bit 2 pmpie: parallel master port interrupt enable bit 1 = interrupt is enabled 0 = interrupt is disabled bit 1 ad1ie: analog-to-digital 1 interrupt enable bit 1 = interrupt is enabled 0 = interrupt is disabled bit 0 cnie: input change interrupt enable bit 1 = interrupt is enabled 0 = interrupt is disabled register 8-7: iec1: interrupt enable control register 1 (continued)
pic32mx3xx/4xx ds61143e-page 144 preliminary ? 2008 microchip technology inc. register 8-8: ipc0: interrupt pr iority control register 0 r-x r-x r-x r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ? int0ip<2:0> int0is<1:0> bit 31 bit 24 r-x r-x r-x r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ? cs1ip<2:0> cs1is<1:0> bit 23 bit 16 r-x r-x r-x r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ? cs0ip<2:0> cs0is<1:0> bit 15 bit 8 r-x r-x r-x r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ? ctip<2:0> ctis<1:0> bit 7 bit 0 legend: r = readable bit w = writable bit p = programmable bit r = reserved bit u = unimplemented bit -n = bit value at por: (?0?, ?1?, x = unknown) bit 31-29 reserved: write ? 0 ?; ignore read bit 28-26 int0ip<2:0>: external interrupt 0 priority bits 111 = interrupt priority is 7 110 = interrupt priority is 6 101 = interrupt priority is 5 100 = interrupt priority is 4 011 = interrupt priority is 3 010 = interrupt priority is 2 001 = interrupt priority is 1 000 = interrupt is disabled bit 25-24 int0is<1:0>: external interrupt 0 subpriority bits 11 = interrupt subpriority is 3 10 = interrupt subpriority is 2 01 = interrupt subpriority is 1 00 = interrupt subpriority is 0 bit 23-21 reserved: write ? 0 ?; ignore read bit 20-18 cs1ip<2:0>: core software 1 interrupt priority bits 111 = interrupt priority is 7 110 = interrupt priority is 6 101 = interrupt priority is 5 100 = interrupt priority is 4 011 = interrupt priority is 3 010 = interrupt priority is 2 001 = interrupt priority is 1 000 = interrupt is disabled bit 17-16 cs1is<1:0>: core software 1 interrupt subpriority bits 11 = interrupt subpriority is 3 10 = interrupt subpriority is 2 01 = interrupt subpriority is 1 00 = interrupt subpriority is 0
? 2008 microchip technology inc. preliminary ds61143e-page 145 pic32mx3xx/4xx bit 15-13 reserved: write ? 0 ?; ignore read bit 12-10 cs0ip<2:0>: core software 0 interrupt priority bits 111 = interrupt priority is 7 110 = interrupt priority is 6 101 = interrupt priority is 5 100 = interrupt priority is 4 011 = interrupt priority is 3 010 = interrupt priority is 2 001 = interrupt priority is 1 000 = interrupt is disabled bit 9-8 cs0is<1:0>: core software 0 interrupt subpriority bits 11 = interrupt subpriority is 3 10 = interrupt subpriority is 2 01 = interrupt subpriority is 1 00 = interrupt subpriority is 0 bit 7-5 reserved: write ? 0 ?; ignore read bit 4-2 ctip<2:0>: core timer interrupt priority bits 111 = interrupt priority is 7 110 = interrupt priority is 6 101 = interrupt priority is 5 100 = interrupt priority is 4 011 = interrupt priority is 3 010 = interrupt priority is 2 001 = interrupt priority is 1 000 = interrupt is disabled bit 1-0 ctis<1:0>: core timer interrupt subpriority bits 11 = interrupt subpriority is 3 10 = interrupt subpriority is 2 01 = interrupt subpriority is 1 00 = interrupt subpriority is 0 register 8-8: ipc0: interrupt priority control register 0 (continued)
pic32mx3xx/4xx ds61143e-page 146 preliminary ? 2008 microchip technology inc. register 8-9: ipc1: interrupt pr iority control register 1 r-x r-x r-x r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ? int1ip<2:0> int1is<1:0> bit 31 bit 24 r-x r-x r-x r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ? oc1ip<2:0> oc1is<1:0> bit 23 bit 16 r-x r-x r-x r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ? ic1ip<2:0> ic1is<1:0> bit 15 bit 8 r-x r-x r-x r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ? t1ip<2:0> t1is<1:0> bit 7 bit 0 legend: r = readable bit w = writable bit p = programmable bit r = reserved bit u = unimplemented bit -n = bit value at por: (?0?, ?1?, x = unknown) bit 31-29 reserved: write ? 0 ?; ignore read bit 28-26 int1ip<2:0>: external interrupt 1 priority bits 111 = interrupt priority is 7 110 = interrupt priority is 6 101 = interrupt priority is 5 100 = interrupt priority is 4 011 = interrupt priority is 3 010 = interrupt priority is 2 001 = interrupt priority is 1 000 = interrupt is disabled bit 25-24 int1is<1:0>: external interrupt 1 subpriority bits 11 = interrupt subpriority is 3 10 = interrupt subpriority is 2 01 = interrupt subpriority is 1 00 = interrupt subpriority is 0 bit 23-21 reserved: write ? 0 ?; ignore read bit 20-18 oc1ip<2:0>: output compare 1 interrupt priority bits 111 = interrupt priority is 7 110 = interrupt priority is 6 101 = interrupt priority is 5 100 = interrupt priority is 4 011 = interrupt priority is 3 010 = interrupt priority is 2 001 = interrupt priority is 1 000 = interrupt is disabled bit 17-16 oc1is<1:0>: output compare 1 interrupt subpriority bits 11 = interrupt subpriority is 3 10 = interrupt subpriority is 2 01 = interrupt subpriority is 1 00 = interrupt subpriority is 0
? 2008 microchip technology inc. preliminary ds61143e-page 147 pic32mx3xx/4xx bit 15-13 reserved: write ? 0 ?; ignore read bit 12-10 ic1ip<2:0>: input compare 1 interrupt priority bits 111 = interrupt priority is 7 110 = interrupt priority is 6 101 = interrupt priority is 5 100 = interrupt priority is 4 011 = interrupt priority is 3 010 = interrupt priority is 2 001 = interrupt priority is 1 000 = interrupt is disabled bit 9-8 ic1is<1:0>: input compare 1 interrupt subpriority bits 11 = interrupt subpriority is 3 10 = interrupt subpriority is 2 01 = interrupt subpriority is 1 00 = interrupt subpriority is 0 bit 7-5 reserved: write ? 0 ?; ignore read bit 4-2 t1ip<2:0>: timer1 interrupt priority bits 111 = interrupt priority is 7 110 = interrupt priority is 6 101 = interrupt priority is 5 100 = interrupt priority is 4 011 = interrupt priority is 3 010 = interrupt priority is 2 001 = interrupt priority is 1 000 = interrupt is disabled bit 1-0 t1is<1:0>: timer1 interrupt subpriority bits 11 = interrupt subpriority is 3 10 = interrupt subpriority is 2 01 = interrupt subpriority is 1 00 = interrupt subpriority is 0 register 8-9: ipc1: interrupt priority control register 1 (continued)
pic32mx3xx/4xx ds61143e-page 148 preliminary ? 2008 microchip technology inc. register 8-10: ipc2: interrupt pr iority control register 2 r-x r-x r-x r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ? int2ip<2:0> int2is<1:0> bit 31 bit 24 r-x r-x r-x r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ? oc2ip<2:0> oc2is<1:0> bit 23 bit 16 r-x r-x r-x r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ? ic2ip<2:0> ic2is<1:0> bit 15 bit 8 r-x r-x r-x r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ? t2ip<2:0> t2is<1:0> bit 7 bit 0 legend: r = readable bit w = writable bit p = programmable bit r = reserved bit u = unimplemented bit -n = bit value at por: (?0?, ?1?, x = unknown) bit 31-29 reserved: write ? 0 ?; ignore read bit 28-26 int2ip<2:0>: external interrupt 2 priority bits 111 = interrupt priority is 7 110 = interrupt priority is 6 101 = interrupt priority is 5 100 = interrupt priority is 4 011 = interrupt priority is 3 010 = interrupt priority is 2 001 = interrupt priority is 1 000 = interrupt is disabled bit 25-24 int2is<1:0>: external interrupt 2 subpriority bits 11 = interrupt subpriority is 3 10 = interrupt subpriority is 2 01 = interrupt subpriority is 1 00 = interrupt subpriority is 0 bit 23-21 reserved: write ? 0 ?; ignore read bit 20-18 oc2ip<2:0>: output compare 2 interrupt priority bits 111 = interrupt priority is 7 110 = interrupt priority is 6 101 = interrupt priority is 5 100 = interrupt priority is 4 011 = interrupt priority is 3 010 = interrupt priority is 2 001 = interrupt priority is 1 000 = interrupt is disabled bit 17-16 oc2is<1:0>: output compare 2 interrupt subpriority bits 11 = interrupt subpriority is 3 10 = interrupt subpriority is 2 01 = interrupt subpriority is 1 00 = interrupt subpriority is 0
? 2008 microchip technology inc. preliminary ds61143e-page 149 pic32mx3xx/4xx bit 15-13 reserved: write ? 0 ?; ignore read bit 12-10 ic2ip<2:0>: input compare 2 interrupt priority bits 111 = interrupt priority is 7 110 = interrupt priority is 6 101 = interrupt priority is 5 100 = interrupt priority is 4 011 = interrupt priority is 3 010 = interrupt priority is 2 001 = interrupt priority is 1 000 = interrupt is disabled bit 9-8 ic2is<1:0>: input compare 2 interrupt subpriority bits 11 = interrupt subpriority is 3 10 = interrupt subpriority is 2 01 = interrupt subpriority is 1 00 = interrupt subpriority is 0 bit 7-5 reserved: write ? 0 ?; ignore read bit 4-2 t2ip<2:0>: timer2 interrupt priority bits 111 = interrupt priority is 7 110 = interrupt priority is 6 101 = interrupt priority is 5 100 = interrupt priority is 4 011 = interrupt priority is 3 010 = interrupt priority is 2 001 = interrupt priority is 1 000 = interrupt is disabled bit 1-0 t2is<1:0>: timer2 interrupt subpriority bits 11 = interrupt subpriority is 3 10 = interrupt subpriority is 2 01 = interrupt subpriority is 1 00 = interrupt subpriority is 0 register 8-10: ipc2: interrupt priority control register 2 (continued)
pic32mx3xx/4xx ds61143e-page 150 preliminary ? 2008 microchip technology inc. register 8-11: ipc3: interrupt priority control register 3 r-x r-x r-x r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ? int3ip<2:0> int3is<1:0> bit 31 bit 24 r-x r-x r-x r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ? oc3ip<2:0> oc3is<1:0> bit 23 bit 16 r-x r-x r-x r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ? ic3ip<2:0> ic3is<1:0> bit 15 bit 8 r-x r-x r-x r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ? t3ip<2:0> t3is<1:0> bit 7 bit 0 legend: r = readable bit w = writable bit p = programmable bit r = reserved bit u = unimplemented bit -n = bit value at por: (?0?, ?1?, x = unknown) bit 31-29 reserved: write ? 0 ?; ignore read bit 28-26 int3ip<2:0>: external interrupt 3 priority bits 111 = interrupt priority is 7 110 = interrupt priority is 6 101 = interrupt priority is 5 100 = interrupt priority is 4 011 = interrupt priority is 3 010 = interrupt priority is 2 001 = interrupt priority is 1 000 = interrupt is disabled bit 25-24 int3is<1:0>: external interrupt 3 subpriority bits 11 = interrupt subpriority is 3 10 = interrupt subpriority is 2 01 = interrupt subpriority is 1 00 = interrupt subpriority is 0 bit 23-21 reserved: write ? 0 ?; ignore read bit 20-18 oc3ip<2:0>: output compare 3 interrupt priority bits 111 = interrupt priority is 7 110 = interrupt priority is 6 101 = interrupt priority is 5 100 = interrupt priority is 4 011 = interrupt priority is 3 010 = interrupt priority is 2 001 = interrupt priority is 1 000 = interrupt is disabled bit 17-16 oc3is<1:0>: output compare 3 interrupt subpriority bits 11 = interrupt subpriority is 3 10 = interrupt subpriority is 2 01 = interrupt subpriority is 1 00 = interrupt subpriority is 0
? 2008 microchip technology inc. preliminary ds61143e-page 151 pic32mx3xx/4xx bit 15-13 reserved: write ? 0 ?; ignore read bit 12-10 ic3ip<2:0>: input compare 3 interrupt priority bits 111 = interrupt priority is 7 110 = interrupt priority is 6 101 = interrupt priority is 5 100 = interrupt priority is 4 011 = interrupt priority is 3 010 = interrupt priority is 2 001 = interrupt priority is 1 000 = interrupt is disabled bit 9-8 ic3is<1:0>: input compare 3 interrupt subpriority bits 11 = interrupt subpriority is 3 10 = interrupt subpriority is 2 01 = interrupt subpriority is 1 00 = interrupt subpriority is 0 bit 7-5 reserved: write ? 0 ?; ignore read bit 4-2 t3ip<2:0>: timer3 interrupt priority bits 111 = interrupt priority is 7 110 = interrupt priority is 6 101 = interrupt priority is 5 100 = interrupt priority is 4 011 = interrupt priority is 3 010 = interrupt priority is 2 001 = interrupt priority is 1 000 = interrupt is disabled bit 1-0 t3is<1:0>: timer3 interrupt subpriority bits 11 = interrupt subpriority is 3 10 = interrupt subpriority is 2 01 = interrupt subpriority is 1 00 = interrupt subpriority is 0 register 8-11: ipc3: interrupt priori ty control register 3 (continued)
pic32mx3xx/4xx ds61143e-page 152 preliminary ? 2008 microchip technology inc. register 8-12: ipc4: interrupt pr iority control register 4 r-x r-x r-x r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ? int4ip<2:0> int4is<1:0> bit 31 bit 24 r-x r-x r-x r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ? oc4ip<2:0> oc4is<1:0> bit 23 bit 16 r-x r-x r-x r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ? ic4ip<2:0> ic4is<1:0> bit 15 bit 8 r-x r-x r-x r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ? t4ip<2:0> t4is<1:0> r-x r-x r-x r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 legend: r = readable bit w = writable bit p = programmable bit r = reserved bit u = unimplemented bit -n = bit value at por: (?0?, ?1?, x = unknown) bit 31-29 reserved: write ? 0 ?; ignore read bit 28-26 int4ip<2:0>: external interrupt 4 priority bits 111 = interrupt priority is 7 110 = interrupt priority is 6 101 = interrupt priority is 5 100 = interrupt priority is 4 011 = interrupt priority is 3 010 = interrupt priority is 2 001 = interrupt priority is 1 000 = interrupt is disabled bit 25-24 int4is<1:0>: external interrupt 4 subpriority bits 11 = interrupt subpriority is 3 10 = interrupt subpriority is 2 01 = interrupt subpriority is 1 00 = interrupt subpriority is 0 bit 23-21 reserved: write ? 0 ?; ignore read bit 20-18 oc4ip<2:0>: output compare 4 interrupt priority bits 111 = interrupt priority is 7 110 = interrupt priority is 6 101 = interrupt priority is 5 100 = interrupt priority is 4 011 = interrupt priority is 3 010 = interrupt priority is 2 001 = interrupt priority is 1 000 = interrupt is disabled bit 17-16 oc4is<1:0>: output compare 4 interrupt subpriority bits 11 = interrupt subpriority is 3 10 = interrupt subpriority is 2 01 = interrupt subpriority is 1 00 = interrupt subpriority is 0
? 2008 microchip technology inc. preliminary ds61143e-page 153 pic32mx3xx/4xx bit 15-13 reserved: write ? 0 ?; ignore read bit 12-10 ic4ip<2:0>: input compare 4 interrupt priority bits 111 = interrupt priority is 7 110 = interrupt priority is 6 101 = interrupt priority is 5 100 = interrupt priority is 4 011 = interrupt priority is 3 010 = interrupt priority is 2 001 = interrupt priority is 1 000 = interrupt is disabled bit 9-8 ic4is<1:0>: input compare 4 interrupt subpriority bits 11 = interrupt subpriority is 3 10 = interrupt subpriority is 2 01 = interrupt subpriority is 1 00 = interrupt subpriority is 0 bit 7-5 reserved: write ? 0 ?; ignore read bit 4-2 t4ip<2:0>: timer4 interrupt priority bits 111 = interrupt priority is 7 110 = interrupt priority is 6 101 = interrupt priority is 5 100 = interrupt priority is 4 011 = interrupt priority is 3 010 = interrupt priority is 2 001 = interrupt priority is 1 000 = interrupt is disabled bit 1-0 t4is<1:0>: timer4 interrupt subpriority bits 11 = interrupt subpriority is 3 10 = interrupt subpriority is 2 01 = interrupt subpriority is 1 00 = interrupt subpriority is 0 register 8-12: ipc4: interrupt priority control register 4 (continued)
pic32mx3xx/4xx ds61143e-page 154 preliminary ? 2008 microchip technology inc. register 8-13: ipc5: interrupt pr iority control register 5 r-x r-x r-x r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ? spi1ip<2:0> spi1is<1:0> bit 31 bit 24 r-x r-x r-x r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ? oc5ip<2:0> oc5is<1:0> bit 23 bit 16 r-x r-x r-x r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ? ic5ip<2:0> ic5is<1:0> bit 15 bit 8 r-x r-x r-x r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ? t5ip<2:0> t5is<1:0> bit 7 bit 0 legend: r = readable bit w = writable bit p = programmable bit r = reserved bit u = unimplemented bit -n = bit value at por: (?0?, ?1?, x = unknown) bit 31-29 reserved: write ? 0 ?; ignore read bit 28-26 spi1ip<2:0>: spi1 interrupt priority bits 111 = interrupt priority is 7 110 = interrupt priority is 6 101 = interrupt priority is 5 100 = interrupt priority is 4 011 = interrupt priority is 3 010 = interrupt priority is 2 001 = interrupt priority is 1 000 = interrupt is disabled bit 25-24 spi1is<1:0>: spi1 interrupt subpriority bits 11 = interrupt subpriority is 3 10 = interrupt subpriority is 2 01 = interrupt subpriority is 1 00 = interrupt subpriority is 0 bit 23-21 reserved: write ? 0 ?; ignore read bit 20-18 oc5ip<2:0>: output compare 5 interrupt priority bits 111 = interrupt priority is 7 110 = interrupt priority is 6 101 = interrupt priority is 5 100 = interrupt priority is 4 011 = interrupt priority is 3 010 = interrupt priority is 2 001 = interrupt priority is 1 000 = interrupt is disabled bit 17-16 oc5is<1:0>: output compare 5 interrupt subpriority bits 11 = interrupt subpriority is 3 10 = interrupt subpriority is 2 01 = interrupt subpriority is 1 00 = interrupt subpriority is 0
? 2008 microchip technology inc. preliminary ds61143e-page 155 pic32mx3xx/4xx bit 15-13 reserved: write ? 0 ?; ignore read bit 12-10 ic5ip<2:0>: input compare 5 interrupt priority bits 111 = interrupt priority is 7 110 = interrupt priority is 6 101 = interrupt priority is 5 100 = interrupt priority is 4 011 = interrupt priority is 3 010 = interrupt priority is 2 001 = interrupt priority is 1 000 = interrupt is disabled bit 9-8 ic5is<1:0>: input compare 5 interrupt subpriority bits 11 = interrupt subpriority is 3 10 = interrupt subpriority is 2 01 = interrupt subpriority is 1 00 = interrupt subpriority is 0 bit 7-5 reserved: write ? 0 ?; ignore read bit 4-2 t5ip<2:0>: timer5 interrupt priority bits 111 = interrupt priority is 7 110 = interrupt priority is 6 101 = interrupt priority is 5 100 = interrupt priority is 4 011 = interrupt priority is 3 010 = interrupt priority is 2 001 = interrupt priority is 1 000 = interrupt is disabled bit 1-0 t5is<1:0>: timer5 interrupt subpriority bits 11 = interrupt subpriority is 3 10 = interrupt subpriority is 2 01 = interrupt subpriority is 1 00 = interrupt subpriority is 0 register 8-13: ipc5: interrupt priority control register 5 (continued)
pic32mx3xx/4xx ds61143e-page 156 preliminary ? 2008 microchip technology inc. register 8-14: ipc6: interrupt pr iority control register 6 r-x r-x r-x r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ? ad1ip<2:0> ad1is<1:0> bit 31 bit 24 r-x r-x r-x r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ? cnip<2:0> cnis<1:0> bit 23 bit 16 r-x r-x r-x r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ? i2c1ip<2:0> i2c1is<1:0> bit 15 bit 8 r-x r-x r-x r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ? u1ip<2:0> u1is<1:0> bit 7 bit 0 legend: r = readable bit w = writable bit p = programmable bit r = reserved bit u = unimplemented bit -n = bit value at por: (?0?, ?1?, x = unknown) bit 31-29 reserved: write ? 0 ?; ignore read bit 28-26 ad1ip<2:0>: analog-to-digital 1 interrupt priority bits 111 = interrupt priority is 7 110 = interrupt priority is 6 101 = interrupt priority is 5 100 = interrupt priority is 4 011 = interrupt priority is 3 010 = interrupt priority is 2 001 = interrupt priority is 1 000 = interrupt is disabled bit 25-24 ad1is<1:0>: analog-to-digital 1 subpriority bits 11 = interrupt subpriority is 3 10 = interrupt subpriority is 2 01 = interrupt subpriority is 1 00 = interrupt subpriority is 0 bit 23-21 reserved: write ? 0 ?; ignore read bit 20-18 cnip<2:0>: input change interrupt priority bits 111 = interrupt priority is 7 110 = interrupt priority is 6 101 = interrupt priority is 5 100 = interrupt priority is 4 011 = interrupt priority is 3 010 = interrupt priority is 2 001 = interrupt priority is 1 000 = interrupt is disabled bit 17-16 cnis<1:0>: input change subpriority bits 11 = interrupt subpriority is 3 10 = interrupt subpriority is 2 01 = interrupt subpriority is 1 00 = interrupt subpriority is 0
? 2008 microchip technology inc. preliminary ds61143e-page 157 pic32mx3xx/4xx bit 15-13 reserved: write ? 0 ?; ignore read bit 12-10 i2c1ip<2:0>: i2c1 interrupt priority bits 111 = interrupt priority is 7 110 = interrupt priority is 6 101 = interrupt priority is 5 100 = interrupt priority is 4 011 = interrupt priority is 3 010 = interrupt priority is 2 001 = interrupt priority is 1 000 = interrupt is disabled bit 9-8 i2c1is<1:0>: i2c1 interrupt subpriority bits 11 = interrupt subpriority is 3 10 = interrupt subpriority is 2 01 = interrupt subpriority is 1 00 = interrupt subpriority is 0 bit 7-5 reserved: write ? 0 ?; ignore read bit 4-2 u1ip<2:0>: uart1 interrupt priority bits 111 = interrupt priority is 7 110 = interrupt priority is 6 101 = interrupt priority is 5 100 = interrupt priority is 4 011 = interrupt priority is 3 010 = interrupt priority is 2 001 = interrupt priority is 1 000 = interrupt is disabled bit 1-0 u1is<1:0>: uart1 interrupt subpriority bits 11 = interrupt subpriority is 3 10 = interrupt subpriority is 2 01 = interrupt subpriority is 1 00 = interrupt subpriority is 0 register 8-14: ipc6: interrupt priority control register 6 (continued)
pic32mx3xx/4xx ds61143e-page 158 preliminary ? 2008 microchip technology inc. register 8-15: ipc7: interrupt pr iority control register 7 r-x r-x r-x r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ? spi2ip<2:0> spi2is<1:0> bit 31 bit 24 r-x r-x r-x r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ? cmp2ip<2:0> cmp2is<1:0> bit 23 bit 16 r-x r-x r-x r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ? cmp1ip<2:0> cmp1is<1:0> bit 15 bit 8 r-x r-x r-x r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ? pmpip<2:0> pmpis<1:0> bit 7 bit 0 legend: r = readable bit w = writable bit p = programmable bit r = reserved bit u = unimplemented bit -n = bit value at por: (?0?, ?1?, x = unknown) bit 31-29 reserved: write ? 0 ?; ignore read bit 28-26 spi2ip<2:0>: spi2 interrupt priority bits 111 = interrupt priority is 7 110 = interrupt priority is 6 101 = interrupt priority is 5 100 = interrupt priority is 4 011 = interrupt priority is 3 010 = interrupt priority is 2 001 = interrupt priority is 1 000 = interrupt is disabled bit 25-24 spi2is<1:0>: spi2 interrupt subpriority bits 11 = interrupt subpriority is 3 10 = interrupt subpriority is 2 01 = interrupt subpriority is 1 00 = interrupt subpriority is 0 bit 23-21 reserved: write ? 0 ?; ignore read bit 20-18 cmp2ip<2:0>: compare 2 interrupt priority bits 111 = interrupt priority is 7 110 = interrupt priority is 6 101 = interrupt priority is 5 100 = interrupt priority is 4 011 = interrupt priority is 3 010 = interrupt priority is 2 001 = interrupt priority is 1 000 = interrupt is disabled bit 17-16 cmp2is<1:0>: compare 2 interrupt subpriority bits 11 = interrupt subpriority is 3 10 = interrupt subpriority is 2 01 = interrupt subpriority is 1 00 = interrupt subpriority is 0
? 2008 microchip technology inc. preliminary ds61143e-page 159 pic32mx3xx/4xx bit 15-13 reserved: write ? 0 ?; ignore read bit 12-10 cmp1ip<2:0>: compare 1 interrupt priority bits 111 = interrupt priority is 7 110 = interrupt priority is 6 101 = interrupt priority is 5 100 = interrupt priority is 4 011 = interrupt priority is 3 010 = interrupt priority is 2 001 = interrupt priority is 1 000 = interrupt is disabled bit 9-8 cmp1is<1:0>: compare 1 interrupt subpriority bits 11 = interrupt subpriority is 3 10 = interrupt subpriority is 2 01 = interrupt subpriority is 1 00 = interrupt subpriority is 0 bit 7-5 reserved: write ? 0 ?; ignore read bit 4-2 pmpip<2:0>: parallel master port interrupt priority bits 111 = interrupt priority is 7 110 = interrupt priority is 6 101 = interrupt priority is 5 100 = interrupt priority is 4 011 = interrupt priority is 3 010 = interrupt priority is 2 001 = interrupt priority is 1 000 = interrupt is disabled bit 1-0 pmpis<1:0>: parallel master port interrupt subpriority bits 11 = interrupt subpriority is 3 10 = interrupt subpriority is 2 01 = interrupt subpriority is 1 00 = interrupt subpriority is 0 register 8-15: ipc7: interrupt priority control register 7 (continued)
pic32mx3xx/4xx ds61143e-page 160 preliminary ? 2008 microchip technology inc. register 8-16: ipc8: interrupt pr iority control register 8 r-x r-x r-x r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ? rtccip<2:0> rtccis<1:0> bit 31 bit 24 r-x r-x r-x r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ? fscmip<2:0> fscmis<1:0> bit 23 bit 16 r-x r-x r-x r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ? i2c2ip<2:0> i2c2is<1:0> bit 15 bit 8 r-x r-x r-x r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ? u2ip<2:0> u2is<1:0> bit 7 bit 0 legend: r = readable bit w = writable bit p = programmable bit r = reserved bit u = unimplemented bit -n = bit value at por: (?0?, ?1?, x = unknown) bit 31-29 reserved: write ? 0 ?; ignore read bit 28-26 rtccip<2:0>: real-time clock interrupt priority bits 111 = interrupt priority is 7 110 = interrupt priority is 6 101 = interrupt priority is 5 100 = interrupt priority is 4 011 = interrupt priority is 3 010 = interrupt priority is 2 001 = interrupt priority is 1 000 = interrupt is disabled bit 25-24 rtccis<1:0>: real-time clock interrupt subpriority bits 11 = interrupt subpriority is 3 10 = interrupt subpriority is 2 01 = interrupt subpriority is 1 00 = interrupt subpriority is 0 bit 23-21 reserved: write ? 0 ?; ignore read bit 12-10 fscmip<2:0>: fail-safe clock monitor interrupt priority bits 111 = interrupt priority is 7 110 = interrupt priority is 6 101 = interrupt priority is 5 100 = interrupt priority is 4 011 = interrupt priority is 3 010 = interrupt priority is 2 001 = interrupt priority is 1 000 = interrupt is disabled bit 9-8 fscmis<1:0>: fail-safe clock monitor interrupt subpriority bits 11 = interrupt subpriority is 3 10 = interrupt subpriority is 2 01 = interrupt subpriority is 1 00 = interrupt subpriority is 0
? 2008 microchip technology inc. preliminary ds61143e-page 161 pic32mx3xx/4xx bit 15-13 reserved: write ? 0 ?; ignore read bit 12-10 i2c2ip<2:0>: i2c2 interrupt priority bits 111 = interrupt priority is 7 110 = interrupt priority is 6 101 = interrupt priority is 5 100 = interrupt priority is 4 011 = interrupt priority is 3 010 = interrupt priority is 2 001 = interrupt priority is 1 000 = interrupt is disabled bit 9-8 i2c2is<1:0>: i2c2 interrupt subpriority bits 11 = interrupt subpriority is 3 10 = interrupt subpriority is 2 01 = interrupt subpriority is 1 00 = interrupt subpriority is 0 bit 7-5 reserved: write ? 0 ?; ignore read bit 4-2 u2ip<2:0>: uart2 interrupt priority bits 111 = interrupt priority is 7 110 = interrupt priority is 6 101 = interrupt priority is 5 100 = interrupt priority is 4 011 = interrupt priority is 3 010 = interrupt priority is 2 001 = interrupt priority is 1 000 = interrupt is disabled bit 1-0 u2is<1:0>: uart2 subpriority bits 11 = interrupt subpriority is 3 10 = interrupt subpriority is 2 01 = interrupt subpriority is 1 00 = interrupt subpriority is 0 register 8-16: ipc8: interrupt priority control register 8 (continued)
pic32mx3xx/4xx ds61143e-page 162 preliminary ? 2008 microchip technology inc. register 8-17: ipc9: interrupt pr iority control register 9 r-x r-x r-x r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ? dma3ip<2:0> dma3is<1:0> bit 31 bit 24 r-x r-x r-x r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ? dma2ip<2:0> dma2is<1:0> bit 23 bit 16 r-x r-x r-x r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ? dma1ip<2:0> dma1is<1:0> bit 15 bit 8 r-x r-x r-x r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ? dma0ip<2:0> dma0is<1:0> bit 7 bit 0 legend: r = readable bit w = writable bit p = programmable bit r = reserved bit u = unimplemented bit -n = bit value at por: (?0?, ?1?, x = unknown) bit 31-29 reserved: write ? 0 ?; ignore read bit 28-26 dma3ip<2:0>: dma3 interrupt priority bits 111 = interrupt priority is 7 110 = interrupt priority is 6 101 = interrupt priority is 5 100 = interrupt priority is 4 011 = interrupt priority is 3 010 = interrupt priority is 2 001 = interrupt priority is 1 000 = interrupt is disabled bit 25-24 dma3is<1:0>: dma3 interrupt subpriority bits 11 = interrupt subpriority is 3 10 = interrupt subpriority is 2 01 = interrupt subpriority is 1 00 = interrupt subpriority is 0 bit 23-21 reserved: write ? 0 ?; ignore read bit 20-18 dma2ip<2:0>: dma2 interrupt priority bits 111 = interrupt priority is 7 110 = interrupt priority is 6 101 = interrupt priority is 5 100 = interrupt priority is 4 011 = interrupt priority is 3 010 = interrupt priority is 2 001 = interrupt priority is 1 000 = interrupt is disabled bit 17-16 dma2is<1:0>: dma2 interrupt subpriority bits 11 = interrupt subpriority is 3 10 = interrupt subpriority is 2 01 = interrupt subpriority is 1 00 = interrupt subpriority is 0
? 2008 microchip technology inc. preliminary ds61143e-page 163 pic32mx3xx/4xx bit 15-13 reserved: write ? 0 ?; ignore read bit 12-10 dma1ip<2:0>: dma1 interrupt priority bits 111 = interrupt priority is 7 110 = interrupt priority is 6 101 = interrupt priority is 5 100 = interrupt priority is 4 011 = interrupt priority is 3 010 = interrupt priority is 2 001 = interrupt priority is 1 000 = interrupt is disabled bit 9-8 dma1is<1:0>: dma1 interrupt subpriority bits 11 = interrupt subpriority is 3 10 = interrupt subpriority is 2 01 = interrupt subpriority is 1 00 = interrupt subpriority is 0 bit 7-5 reserved: write ? 0 ?; ignore read bit 4-2 dma0ip<2:0>: dma0 interrupt priority bits 111 = interrupt priority is 7 110 = interrupt priority is 6 101 = interrupt priority is 5 100 = interrupt priority is 4 011 = interrupt priority is 3 010 = interrupt priority is 2 001 = interrupt priority is 1 000 = interrupt is disabled bit 1-0 dma0is<1:0>: dma0 subpriority bits 11 = interrupt subpriority is 3 10 = interrupt subpriority is 2 01 = interrupt subpriority is 1 00 = interrupt subpriority is 0 register 8-17: ipc9: interrupt priority control register 9 (continued)
pic32mx3xx/4xx ds61143e-page 164 preliminary ? 2008 microchip technology inc. register 8-18: ipc11: interrupt priority control register 11 r-x r-x r-x r-x r-x r-x r-x r-x ? ? ? ? ? ? ? ? bit 31 bit 24 r-x r-x r-x r-x r-x r-x r-x r-x ? ? ? ? ? ? ? ? bit 23 bit 16 r-x r-x r-x r-x r-x r-x r-x r-x ? ? ? usbip<2:0> usbis<1:0> bit 15 bit 8 r-x r-x r-x r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ? fceip<2:0> fceis<1:0> bit 7 bit 0 legend: r = readable bit w = writable bit p = programmable bit r = reserved bit u = unimplemented bit -n = bit value at por: (?0?, ?1?, x = unknown) bit 31-13 reserved: write ? 0 ?; ignore read bit 12-10 usbip<2:0>: usb interrupt priority bits 111 = interrupt priority is 7 110 = interrupt priority is 6 101 = interrupt priority is 5 100 = interrupt priority is 4 011 = interrupt priority is 3 010 = interrupt priority is 2 001 = interrupt priority is 1 000 = interrupt is disabled bit 9-8 usbis<1:0>: usb sub-priority bits 11 = interrupt sub-priority is 3 10 = interrupt sub-priority is 2 01 = interrupt sub-priority is 1 00 = interrupt sub-priority is 0 bit 7-5 reserved: write ? 0 ?; ignore read bit 4-2 fceip<2:0>: flash control event interrupt priority bits 111 = interrupt priority is 7 110 = interrupt priority is 6 101 = interrupt priority is 5 100 = interrupt priority is 4 011 = interrupt priority is 3 010 = interrupt priority is 2 001 = interrupt priority is 1 000 = interrupt is disabled bit 1-0 fceis<1:0>: flash control event interrupt subpriority bits 11 = interrupt subpriority is 3 10 = interrupt subpriority is 2 01 = interrupt subpriority is 1 00 = interrupt subpriority is 0
? 2008 microchip technology inc. preliminary ds61143e-page 165 pic32mx3xx/4xx table 8-2: interrupt irq and vector location interrupt source irq (1) vector number highest natural order priority ct ? core timer interrupt 0 0 cs0 ? core software interrupt 0 1 1 cs1 ? core software interrupt 1 2 2 int0 ? external interrupt 0 3 3 t1 ? timer1 4 4 ic1 ? input capture 1 5 5 oc1 ? output compare 1 6 6 int1 ? external interrupt 1 7 7 t2 ? timer2 8 8 ic2 ? input capture 2 9 9 oc2 ? output compare 2 10 10 int2 ? external interrupt 2 11 11 t3 ? timer3 12 12 ic3 ? input capture 3 13 13 oc3 ? output compare 3 14 14 int3 ? external interrupt 3 15 15 t4 ? timer4 16 16 ic4 ? input capture 4 17 17 oc4 ? output compare 4 18 18 int4 ? external interrupt 4 19 19 t5 ? timer5 20 20 ic5 ? input capture 5 21 21 oc5 ? output compare 5 22 22 spi1e ? spi1 fault 23 23 spi1tx ? spi1 transfer done 24 23 spi1rx ? spi1 receive done 25 23 u1e ? uart1 error 26 24 u1rx ? uart1 receiver 27 24 u1tx ? uart1 transmitter 28 24 i2c1b ? i2c1 bus collision event 29 25 i2c1s ? i2c1 slave event 30 25 i2c1m ? i2c1 master event 31 25 cn ? input change interrupt 32 26 ad1 ? adc1 convert done 33 27 pmp ? parallel master port 34 28 cmp1 ? comparator interrupt 35 29 cmp2 ? comparator interrupt 36 30 spi2e ? spi2 fault 37 31 spi2tx ? spi2 transfer done 38 31 note 1: the ?irq number? in table 8-2 is also the ?interrupt number? listed in the ifsx, iecx and ipsx register definitions.
pic32mx3xx/4xx ds61143e-page 166 preliminary ? 2008 microchip technology inc. spi2rx ? spi2 receive done 39 31 u2e ? uart2 error 40 32 u2rx ? uart2 receiver 41 32 u2tx ? uart2 transmitter 42 32 i2c2b ? i2c2 bus collision event 43 33 i2c2s ? i2c2 slave event 44 33 i2c2m ? i2c2 master event 45 33 fscm ? fail-safe clock monitor 46 34 rtcc ? real-time clock 47 35 dma0 ? dma channel 0 48 36 dma1 ? dma channel 1 49 37 dma2 ? dma channel 2 50 38 dma3 ? dma channel 3 51 39 fce ? flash control event 56 44 usb 57 45 (reserved) lowest natural order priority table 8-2: interrupt irq and vector location (continued) interrupt source irq (1) vector number note 1: the ?irq number? in table 8-2 is also the ?interrupt number? listed in the ifsx, iecx and ipsx register definitions.
? 2008 microchip technology inc. preliminary ds61143e-page 167 pic32mx3xx/4xx 8.2 operation the interrupt controller is responsible for pre- processing interrupt requests (irq) from a number of on-chip peripherals and presenting them in the appropriate order to the processor. figure 8-2 depicts the process within the interrupt con- troller module. the interrupt controller is designed to receive up to 96 irqs from the processor core and from on-chip peripherals capable of generating inter- rupts. all irqs are sampled on the rising edge of the sysclk and latched in associated ifsx registers. a pending irq is indicated by the flag bit being equal to ? 1 ? in an ifsx register. the pending irq will not cause further processing if the corresponding bit in the inter- rupt enable (iecx) register is clear. the iecx bits act to gate the interrupt flag. if the interrupt is enabled, all irqs are encoded into a 5-bit wide vector number. the 5-bit vector results in 0 to 63 unique interrupt vector numbers. since there are more irqs than available vector numbers, some irqs share common vector numbers. each vector number is assigned an interrupt priority level and shadow set number. the priority level is determined by the ipcx register setting of the asso- ciated vector. in multi-vector mode, all priority level 7 interrupts use a dedicated register set, while in single vector mode, all interrupts may receive a dedicated shadow set. the interrupt controller selects the highest priority irq among all pending irqs and presents the associated vector number, priority level and shadow set number to the processor core. the processor core samples the presented vector information between the ?e? and ?m? stage of the pipe- line. if the vector?s priority level presented to the core is greater than the current priority indicated by the cpu interrupt priority bits iplx (status<15:10>), the inter- rupt is serviced; otherwise, it will remain pending until the current priority is less than the interrupt?s priority. when servicing an interrupt, the processor core pushes the program counter into the exception program coun- ter (epc) register in the cpu and sets exception level bit exl (status<1>) in the cpu. the exl bit disables further interrupts until the application explicitly re- enables them by clearing the exl bit. next, it branches to the vector address calculated from the presented vector number. the intstat register contains the interrupt vector number bits, vec (intstat<5:0>), and requested interrupt priority bits, riplx (intstat<10:8>), of the current pending interrupt. this may not be the same as the interrupt which caused the core to diverge from normal execution. the processor returns to the previous state when the eret (exception return) instruction is executed. eret clears the exl bit, restores the program counter and reverts the current shadow set to the previous one. the pic32mx3xx/4xx interrupt controller can be con- figured to operate in one of two modes: ? single vector mode ? all interrupt requests will be serviced at one vector address (mode out of reset). ? multi-vector mode ? interrupt requests will be serviced at the calculated vector address. notes: while the user can, during run time, reconfigure the interrupt controller from single vector to multi-vector mode (or vice versa), such action is strongly dis- couraged. changing interrupt controller modes after initialization may result in undefined behavior. the m4k core supports several different interrupt processing modes. the interrupt controller is designed to work in external interrupt controller mode.
pic32mx3xx/4xx ds61143e-page 168 preliminary ? 2008 microchip technology inc. figure 8-2: interrupt process encode latch compare generate status ie status ipl ripl > ipl interrupt request any request shadow set number interrupt exception requested ipl interrupt sources interrupt module load vector number offset exception vector offset fields generator srsctl eicss cause ripl intctl vs ? shadow set number note: srsctl, cause, status, and intctl registers are cpu registers and are described in section 2. ?cpu? .
? 2008 microchip technology inc. preliminary ds61143e-page 169 pic32mx3xx/4xx 8.3 single vector mode on any form of reset, the interrupt controller initializes to single vector mode. when the mvec (int- con<12>) bit is ? 0 ?, the interrupt controller operates in single vector mode. in this mode, the cpu always vec- tors to the same address. to configure the cpu in single vector mode, the follow- ing cpu registers (intctl, cause, and status) and int- con register must be configured as follows: ? ebase 00000 ? vs (intctl<9:5>) 00000 ? iv (cause<23>) = 1 ? exl (status<1>) = 0 ? bev (status<22>) = 0 ? mvec (intcon<12>) = 0 ?ie (status<0>)= 1 example 8-1: single vector mode initialization note: users familiar with mips32 architecture must note that the m4k core in pic32mx3xx/4xx is still operating in external interrupt controller (eic) mode. the pic32mx3xx/4xx achieves single vector mode by forcing all irqs to use a vector number of 0x00. because the m4k core in pic32mx3xx/4xx always oper- ates in eic mode, the single vector behav- ior through ?interrupt compatibility mode,? as defined by mips32 architecture, is not recommended. /* set the cp0 registers for multi-vector interrupt place ebase at 0xbd000000 this code example uses mplab c32 intrinsic functions to access cp0 registers. check your compiler documentation to find equivalent functions or use inline assembly */ unsigned int temp; asm volatile(?di?); // disable all interrupts temp = _cp0_get_status(); // get status temp |= 0x00400000; // set bev bit _cp0_set_status(temp); // update status _cp0_set_ebase(0xbd000000); // set an ebase value of 0xbd000000 _cp0_set_intctl(0x00000020); // set the vector spacing to non-zero value temp = _cp0_get_cause(); // get cause temp |= 0x00800000; // set iv _cp0_set_cause(temp); // update cause temp = _cp0_get_status(); // get status temp &= 0xffbffffd; // clear bev and exl _cp0_set_status(temp); // update status intconclr = 0x1000; // clear mvec bit asm volatile(?ei?); // enable all interrupts
pic32mx3xx/4xx ds61143e-page 170 preliminary ? 2008 microchip technology inc. 8.4 multi-vector mode when the mvec (intcon<12>) bit is ? 1 ?, the interrupt controller operates in multi-vector mode. in this mode, the cpu vectors to the unique address for each vector number. each vector is located at a specific offset, with respect to a base address specified by the ebase reg- ister in the cpu. the individual vector address offset is determined by the vector space that is specified by the vs bits in the intctl register. (the intctl register is located in the cpu; refer to section 2.0 "pic32mx mcu" of this manual for more information.) to configure the cpu in multi-vector mode, the follow- ing cpu registers (intctl, cause, and status) and the intcon register must be configured as follows: ? ebase 00000 ? vs (intctl<9:5>) 00000 ? iv (cause<23>) = 1 ? exl (status<1>) = 0 ? bev (status<22>) = 0 ? mvec (intcon<12>) = 1 ?ie (status<0>)= 1 example 8-2: multi-vector mode initialization /* set the cp0 registers for multi-vector interrupt place ebase at 0xbd000000 and vector spacing to 32 bytes this code example uses mplab c32 intrinsic functions to access cp0 registers. check your compiler documentation to find equivalent functions or use inline assembly */ unsigned int temp; asm volatile(?di?); // disable all interrupts temp = _cp0_get_status(); // get the cpo status register temp |= _cpo_status_bev_mask; // set the bev bit _cp0_set_status(temp); // update the status register _cp0_set_ebase(0xbd000000); // set an ebase value (kseg0 or kseg1) _cp0_set_intctl(0x20); // set the vector spacing temp = _cp0_get_cause(); // get the cpo cause register temp |= _cpo_cause_iv_mask; // set the iv bit _cp0_set_cause(temp); // update the cause register temp = _cp0_get_status(); // get the cpo status register temp &= ~(_cpo_status_exl_mask| // clear exl and bev bits _cpo_status_bev_mask; _cp0_set_status(temp); // update the status register intconset = _intcon_mvec_mask; // set the interrupt controller to multi-vectored mode asm volatile(?ei?); // enable all interrupts asm volatile(?ie?); // enable all interrupts
? 2008 microchip technology inc. preliminary ds61143e-page 171 pic32mx3xx/4xx 8.5 interrupt priorities 8.5.1 interrupt group priority the user is able to assign a group priority to each of the interrupt vectors. the groups? priority level bits are located in the ipcx register. each ipcx register con- tains group priority bits for four interrupt vectors. the user-selectable priority levels range from 1 (the lowest priority) to 7 (the highest). if an interrupt priority is set to zero, the interrupt vector is disabled for both interrupt and wake-up purposes. interrupt vectors with a higher priority level preempt lower priority interrupts. the user must move the requested interrupt priority bit of the cause register, riplx (cause<15:10>), into the status register?s interrupt priority bits, iplx (status<15:10>), before re-enabling interrupts. (the cause and status registers are located in the cpu; refer to section 2.0 "pic32mx mcu" of this manual for more information.) this action will disable all lower priority interrupts until the completion of the interrupt service routine. example 8-3: setting group priority level 8.5.2 interrupt subpriority the user can assign a subpriority level within each group priority. the subpriority will not cause preemption of an interrupt in the same priority; rather, if two inter- rupts with the same priority are pending, the interrupt with the highest subpriority will be handled first. the subpriority bits are located in the ipcx register. each ipcx register contains subpriority bits for four of the interrupt vectors. these bits define the subpriority within the priority level of the vector. the user- selectable subpriority levels range from 0 (the lowest subpriority) to 3 (the highest). example 8-4: setting subpriority level note: the interrupt service routine (isr) must clear the associated interrupt flag in the ifsx register before lowering the interrupt priority level to avoid recursive interrupts. /* the following code example will set the priority to level 2. multi-vector initialization must be performed (see example 8-2) */ ipc0clr = 0x0000001c; // clear the priority level ipc0set = 0x00000008; // set priority level to 2 /* the following code example will set the subpriority to level 2. multi-vector initialization must be performed (see example 8-2) */ ipc0clr = 0x00000003; // clear the subpriority level ipc0set = 0x00000002; // set the subpriority to 2
pic32mx3xx/4xx ds61143e-page 172 preliminary ? 2008 microchip technology inc. 8.6 interrupt processing when the priority of a requested interrupt is greater than the current cpu priority, the interrupt request is taken and the cpu branches to the vector address associated with the requested interrupt. depending on the priority of the interrupt, the prologue and epilogue of the interrupt handler must perform certain tasks before executing any useful code. the following examples provide recommended prologues and epilogues. 8.6.1 interrupt processing in single vector mode when the interrupt controller is configured in single vector mode, all of the interrupt requests are serviced at the same vector address. the interrupt handler routine must generate a prologue and an epilogue to properly configure, save and restore all of the core reg- isters, along with general purpose registers. at a worst case, all of the modifiable general purpose reg- isters must be saved and restored by the prologue and epilogue. 8.6.1.1 single vector mode prologue when entering the interrupt handler routine, the inter- rupt controller must first save the current priority and exception pc counter from interrupt priority bits, iplx (status<15:10>), and the errorepc register, respec- tively, on the stack. (status and errorepc are cpu reg- isters.) if the routine is presented a new register set, the previous register set?s stack register must be copied to the current set?s stack register. then, the requested pri- ority may be stored in the iplx from the requested interrupt priority bits, riplx (cause<15:10>), excep- tion level bit, exl, and error level bit, erl, in the sta- tus register (status<1> and status<2>) are cleared and the master interrupt enable bit (status<0>) is set. finally, the general purpose registers will be saved on the stack. (the cause and status registers are located in the cpu.) example 8-5: single vector interrupt handler prologue in assembly code rdpgpr sp, sp mfc0 k0, cause mfc0 k1, epc srl k0, k0, 0xa addiu sp, sp, -76 sw k1, 0(sp) mfc0 k1, status sw k1, 4(sp) ins k1, k0, 10, 6 ins k1,zero, 1, 4 mtc0 k1, status sw s8, 8(sp) sw a0, 12(sp) sw a1, 16(sp) sw a2, 20(sp) sw a3, 24(sp) sw v0, 28(sp) sw v1, 32(sp) sw t0, 36(sp) sw t1, 40(sp) sw t2, 44(sp) sw t3, 48(sp) sw t4, 52(sp) sw t5, 56(sp) sw t6, 60(sp) sw t7, 64(sp) sw t8, 68(sp) sw t9, 72(sp) addu s8, sp, zero // start interrupt handler code here
? 2008 microchip technology inc. preliminary ds61143e-page 173 pic32mx3xx/4xx 8.6.1.2 single vector mode epilogue after completing all useful code of the interrupt handler routine, the original state of the status and epc regis- ters, along with the general purpose registers saved on the stack, must be restored. example 8-6: single vector interrupt handler epilogue in assembly code 8.6.2 interrupt processing in multi-vector mode when the interrupt controller is configured in multi- vector mode, the interrupt requests are serviced at the calculated vector addresses. the interrupt handler routine must generate a prologue and an epilogue to properly configure, save and restore all of the core reg- isters, along with general purpose registers. at a worst case, all of the modifiable general purpose reg- isters must be saved and restored by the prologue and epilogue. if the interrupt priority is set to receive its own general purpose register set, the prologue and epi- logue will not need to save or restore any of the modi- fiable general purpose registers, thus providing the lowest latency. 8.6.2.1 multi-vector mode prologue when entering the interrupt handler routine, the inter- rupt service routine (isr) must first save the current priority and exception pc counter from interrupt priority bits, ipl (status<15:10>), and the errorepc register, respectively, on the stack. if the routine is presented a new register set, the previous register set?s stack regis- ter must be copied to the current set?s stack register. then, the requested priority may be stored in the iplx from requested interrupt priority bits, riplx (cause<15:10>), exception level bit, exl, and error level bit, erl, in the status register (status<1> and status<2>) are cleared, and the master interrupt enable bit (status<0>) is set. if the interrupt handler is not presented a new general purpose register set, these resisters will be saved on the stack. (cause and status are cpu registers; refer to section 2.0 "pic32mx mcu" of this manual for more information.) example 8-7: prologue without a dedicated general purpose register set in assembly code // end of interrupt handler code addu sp, s8, zero lw t9, 72(sp) lw t8, 68(sp) lw t7, 64(sp) lw t6, 60(sp) lw t5, 56(sp) lw t4, 52(sp) lw t3, 48(sp) lw t2, 44(sp) lw t1, 40(sp) lw t0, 36(sp) lw v1, 32(sp) lw v0, 28(sp) lw a3, 24(sp) lw a2, 20(sp) lw a1, 16(sp) lw a0, 12(sp) lw s8, 8(sp) di lw k0, 0(sp) mtc0 k0, epc lw k0, 4(sp) mtc0 k0, status eret rdpgpr sp, sp mfc0 k0, cause mfc0 k1, epc srl k0, k0, 0xa addiu sp, sp, -76 sw k1, 0(sp) mfc0 k1, status sw k1, 4(sp) ins k1, k0, 10, 6 ins k1,zero, 1, 4 mtc0 k1, status sw s8, 8(sp) sw a0, 12(sp) sw a1, 16(sp) sw a2, 20(sp) sw a3, 24(sp) sw v0, 28(sp) sw v1, 32(sp) sw t0, 36(sp) sw t1, 40(sp) sw t2, 44(sp) sw t3, 48(sp) sw t4, 52(sp) sw t5, 56(sp) sw t6, 60(sp) sw t7, 64(sp) sw t8, 68(sp) sw t9, 72(sp) addu s8, sp, zero // start interrupt handler code here
pic32mx3xx/4xx ds61143e-page 174 preliminary ? 2008 microchip technology inc. example 8-8: prologue with a dedicated general purpose register set in assembly code 8.6.2.2 multi-vector mode epilogue after completing all useful code of the interrupt handler routine, the original state of the status and errorepc registers, along with the general purpose registers saved on the stack, must be restored. (the status and errorepc registers are located in the cpu; refer to section 2.0 "pic32mx mcu" of this manual for more information.) example 8-9: epilogue without a dedicated general purpose register set in assembly code example 8-10: epilogue with a dedicated general purpose register set in assembly code rdpgpr sp, sp mfc0 k0, cause mfc0 k1, epc srl k0, k0, 0xa addiu sp, sp, -76 sw k1, 0(sp) mfc0 k1, status sw k1, 4(sp) ins k1, k0, 10, 6 ins k1,zero, 1, 4 mtc0 k1, status addu s8, sp, zero // start interrupt handler code here // end of interrupt handler code addu sp, s8, zero lw t9, 72(sp) lw t8, 68(sp) lw t7, 64(sp) lw t6, 60(sp) lw t5, 56(sp) lw t4, 52(sp) lw t3, 48(sp) lw t2, 44(sp) lw t1, 40(sp) lw t0, 36(sp) lw v1, 32(sp) lw v0, 28(sp) lw a3, 24(sp) lw a2, 20(sp) lw a1, 16(sp) lw a0, 12(sp) lw s8, 8(sp) di lw k0, 0(sp) mtc0 k0, epc lw k0, 4(sp) mtc0 k0, status eret // end of interrupt handler code addu sp, s8, zero di lw k0, 0(sp) mtc0 k0, epc lw k0, 4(sp) mtc0 k0, status eret
? 2008 microchip technology inc. preliminary ds61143e-page 175 pic32mx3xx/4xx 8.7 external interrupts the interrupt controller supports five external interrupt- request signals (int4-int0). these inputs are edge sensitive; they require a low-to-high or a high-to-low transition to create an interrupt request. the intcon register has five bits that select the polarity of the edge detection circuitry: int4ep (intcon<4>), int3ep (intcon<3>), int2ep (intcon<2>), int1ep (int- con<1>) and int0ep (intcon<0>). example 8-11: setting external interrupt polarity 8.8 temporal proximity interrupt coalescing the pic32mx3xx/4xx cpu responds to interrupt events as if they are all immediately critical because the interrupt controller asserts the interrupt request to the cpu when the interrupt request occurs. the cpu immediately recognizes the interrupt if the current cpu priority is lower than the pending priority. entering and exiting an isr consumes clock cycles for saving and restoring context. events are asynchronous with respect to the main program and have a limited possibility of occurring simultaneously or close together in time. this prevents the ability of a shared isr to process multiple interrupts at one time. interrupt proximity interrupt uses the interrupt proximity timer, iptmr, to create a temporal window in which a group of interrupts of the same, or lower, priority will be held off. the user can activate temporal proximity inter- rupt coalescing by performing the following steps: ? set the tpc<2:0> intcon<10:8> bit to the pre- ferred priority level. (setting tpc to zero will dis- able the proximity timer.) ? load the preferred 32-bit value to iptmr. the interrupt proximity timer will trigger when an inter- rupt request of a priority equal, or lower, matches the tpc value. example 8-12: interrupt proximity interrupt coalescing example note: changing the external interrupt polarity may trigger an interrupt request. it is rec- ommended that before changing the polarity, the user disables that interrupt, changes the polarity, clears the interrupt flag and re-enables the interrupt. /* the following code example will set int3 to trigger on a high to low transition edge. the cpu must be set up for either multi or single vector interrupts to handle external interrupts */ iec0clr = 0x00008000; // disable int3 intconclr = 0x00000008; // clear the bit for falling edge trigger ifs0clr = 0x00008000; // clear the interrupt flag iec0set = 0x00008000; // enable int3 /* the following code example will set the interrupt proximity coalescing to trigger on interrupt priority level of 3 or below and the interrupt timer to be set to 0x12345678. */ intconclr = 0x00000700; // clear tpc iptmpclr = 0xffffffff; // clear the timer intconset = 0x00000300; // set tpc->3 iptmr = 0x12345678; // set the timer to 0x12345678
pic32mx3xx/4xx ds61143e-page 176 preliminary ? 2008 microchip technology inc. notes:
? 2008 microchip technology inc. preliminary ds61143e-page 177 pic32mx3xx/4xx 9.0 prefetch cache the prefetch cache increases performance for appli- cations executing out of the cacheable program flash memory region by implementing instruction caching, data caching and instruction prefetching. 9.1 features ? 16 fully associative lockable cache lines ? 16-byte cache lines ? up to 4 cache lines allocated to data ? 2 cache lines with address mask to hold repeated instructions ? pseudo lru replacement policy ? all cache lines are software writable ? 16-byte parallel memory fetch ? predictive instruction prefetch figure 9-1: prefetch module block diagram note: this data sheet summarizes the features of the pic32mx3xx/4xx family of devices. it is not intended to be a comprehensive refer- ence source. refer to the ?pic32mx family reference manual? (ds61132) for a detailed description of this peripheral. hit logic tag logic cache line cache line address encode fsm bus ctrl cache ctrl prefetch ctrl hit lru miss lru rdata rdata ctrl ctrl ctrl pfm bmx/cpu bmx/cpu prefetch prefetch tag pre-fetch pre-fetch
pic32mx3xx/4xx ds61143e-page 178 preliminary ? 2008 microchip technology inc. table 9-1: prefetch sfr summary virtual address name bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 bf88_4000 checon 31:24 ? ? ? ? ? ? ? ? 23:16 ? ? ? ? ? ? ? checoh 15:8 ? ? ? ? ? ? dcsz<1:0> 7:0 ? ? prefen<1:0> ?pfmws<2:0> bf88_4004 checonclr 31:0 clears selected bits in checon, read yields undefined value bf88_4008 checonset 31:0 sets selected bits in checon, read yields undefined value bf88_400c checoninv 31:0 inverts selected bits in checon, read yields undefined value bf88_4010 cheacc 31:24 chewen ? ? ? ? ? ? ? 23:16 ? ? ? ? ? ? ? ? 15:8 ? ? ? ? ? ? ? ? 7:0 ? ? ? ? cheidx<3:0> bf88_4014 cheaccclr 31:0 clears selected bits in cheacc, read yields undefined value bf88_4018 cheaccset 31:0 sets selected bits in cheacc, read yields undefined value bf88_401c cheaccinv 31:0 inverts selected bits cheacc, read yields undefined value bf88_4020 chetag 31:24 ltagboot ? ? ? ? ? ? ? 23:16 ltag<23:16> 15:8 ltag<15:8> 7:0 ltag<7:4> lvalid llock ltype ? bf88_4024 chetagclr 31:0 clears selected bits in chetag, read yields undefined value bf88_4028 chetagset 31:0 sets selected bits in chetag, read yields undefined value bf88_402c chetaginv 31:0 inverts selected bits chetag, read yields undefined value bf88_4030 chemsk 31:24 ? ? ? ? ? ? ? ? 23:16 ? ? ? ? ? ? ? ? 15:8 lmask<15:8> 7:0 lmask<7:5> ? ? ? ? ? bf88_4034 chemskclr 31:0 clears selected bits in chemsk, read yields undefined value bf88_4038 chemskset 31:0 sets selected bits in chemsk, read yields undefined value bf88_403c chemskinv 31:0 inverts selected bits chemsk, read yields undefined value bf88_4040 chew0 31:24 chew0<31:24> 23:16 chew0<23:16> 15:8 chew0<15:8> 7:0 chew0<7:0> bf88_4050 chew1 31:24 chew1<31:24> 23:16 chew1<23:16> 15:8 chew1<15:8> 7:0 chew1<7:0> bf88_4060 chew2 31:24 chew2<31:24> 23:16 chew2<23:16> 15:8 chew2<15:8> 7:0 chew2<7:0> bf88_4070 chew3 31:24 chew3<31:24> 23:16 chew3<23:16> 15:8 chew3<15:8> 7:0 chew3<7:0> bf88_4080 chelru 31:24 ? ? ? ? ? ? ? chelru<24> 23:16 chelru<23:16> 15:8 chelru<15:8> 7:0 chelru<7:0>> bf88_4090 chehit 31:24 chehit<31:24> 23:16 chehit<23:16> 15:8 chehit<15:8> 7:0 chenit<7:0> bf88_40a0 chemis 31:24 chemis<31:24> 23:16 chemis<23:16> 15:8 chemis<15:8> 7:0 chemis<7:0>
? 2008 microchip technology inc. preliminary ds61143e-page 179 pic32mx3xx/4xx bf88_40c0 chepfabt 31:24 chepfabt<31:24> 23:16 chepfabt<23:16> 15:8 chepfabt<15:8> 7:0 chepfabt<7:0> table 9-1: prefetch sfr summary (continued) virtual address name bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0
pic32mx3xx/4xx ds61143e-page 180 preliminary ? 2008 microchip technology inc. 9.2 prefetch registers register 9-1: checon: cache control register r-x r-x r-x r-x r-x r-x r-x r-x ? ? ? ? ? ? ? ? bit 31 bit 24 r-x r-x r-x r-x r-x r-x r-x r/w-0 ? ? ? ? ? ? ? checoh bit 23 bit 16 r-x r-x r-0 r-0 r-x r-x r/w-0 r/w-0 ? ? ? ? ? ? dcsz<1:0> bit 15 bit 8 r-x r-x r/w-0 r/w-0 r-x r/w-1 r/w-1 r/w-1 ? ? prefen<1:0> ? pfmws<2:0> bit 7 bit 0 legend: r = readable bit w = writable bit p = programmable bit r = reserved bit u = unimplemented bit -n = bit value at por: (?0?, ?1?, x = unknown) bit 31-17 reserved: write ? 0 ?; ignore read bit 16 checoh: cache coherency setting on a pfm program cycle bit 1 = invalidate all data and instruction lines 0 = invalidate all data lines and instruction lines that are not locked bit 15-14 reserved: write ? 0 ?; ignore read bit 13-12 reserved: must be written with zeros bit 11-10 reserved: write ? 0 ?; ignore read bit 9-8 dcsz<1:0>: data cache size in lines bits 11 = enable data caching with a size of 4 lines 10 = enable data caching with a size of 2 lines 01 = enable data caching with a size of 1 line 00 = disable data caching changing this field causes all lines to be re-initialized to the ?invalid? state. bit 7-6 reserved: write ? 0 ?; ignore read bit 5-4 prefen<1:0>: predictive prefetch cache enable bits 11 = enable predictive prefetch cache for both cacheable and non-cacheable regions 10 = enable predictive prefetch cache for non-cacheable regions only 01 = enable predictive prefetch cache for cacheable regions only 00 = disable predictive prefetch cache bit 3 reserved: write ? 0 ?; ignore read
? 2008 microchip technology inc. preliminary ds61143e-page 181 pic32mx3xx/4xx bit 2-0 pfmws<2:0>: pfm access time defined in terms of syslk wait states bits 111 = seven wait states 110 = six wait states 101 = five wait state 100 = four wait states 011 = three wait states 010 = two wait states 001 = one wait state 000 = zero wait states register 9-1: checon: cache co ntrol register (continued)
pic32mx3xx/4xx ds61143e-page 182 preliminary ? 2008 microchip technology inc. register 9-2: cheacc: cache access r/w-0 r-x r-x r-x r-x r-x r-x r-x chewen ? ? ? ? ? ? ? bit 31 bit 24 r-x r-x r-x r-x r-x r-x r-x r-x ? ? ? ? ? ? ? ? bit 23 bit 16 r-x r-x r-x r-x r-x r-x r-x r-x ? ? ? ? ? ? ? ? bit 15 bit 8 r-x r-x r-x r-x r/w-0 r/w-0 r/w-0 r/w-0 ? ? ? ? cheidx<3:0> bit 7 bit 0 legend: r = readable bit w = writable bit p = programmable bit r = reserved bit u = unimplemented bit -n = bit value at por: (?0?, ?1?, x = unknown) bit 31 chewen: cache access enable bits for registers chetag, chemsk, chew0, chew1, chew2, and chew3 1 = the cache line selected by cheidx is writable 0 = the cache line selected by cheidx is not writable bit 30-4 reserved: write ? 0 ?; ignore read bit 3-0 cheidx<3:0>: cache line index bits the value selects the cache line for reading or writing.
? 2008 microchip technology inc. preliminary ds61143e-page 183 pic32mx3xx/4xx register 9-3: chetag (1) : cache tag register r/w-0 r-x r-x r-x r-x r-x r-x r-x ltagboot ? ? ? ? ? ? ? bit 31 bit 24 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x ltag<23:16> bit 23 bit 16 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x ltag<15:8> bit 15 bit 8 r/w-x r/w-x r/w-x r/w-x r/w-0 r/w-0 r/w-1 r-0 ltag<7:4> lvalid llock ltype ? bit 7 bit 0 legend: r = readable bit w = writable bit p = programmable bit r = reserved bit u = unimplemented bit -n = bit value at por: (?0?, ?1?, x = unknown) bit 31 ltagboot: line tag address boot 1 = the line is in the 0x1d000000 (physical) area of memory 0 = the line is in the 0x1fc00000 (physical) area of memory bit 30-24 reserved: write ? 0 ?; ignore read bit 23-4 ltag<23:4>: line tag address bits ltag bits are compared against physical address <23:4> to determine a hit. because its address range and position of flash in kernel space and user space, the ltag flash address is identical for virtual addresses, (system) physical addresses, and flash physical addresses. bit 3 lvalid: line valid bit 1 = the line is valid and is compared to the physical address for hit detection 0 = the line is not valid and is not compared to the physical address for hit detection bit 2 llock: line lock bit 1 = the line is locked and will not be replaced 0 = the line is not locked and can be replaced bit 1 ltype: line type bit 1 = the line caches instruction words 0 = the line caches data words bit 0 reserved: note 1: the tag and status of the line pointed to by cheidx (cheacc<3:0>).
pic32mx3xx/4xx ds61143e-page 184 preliminary ? 2008 microchip technology inc. register 9-4: chemsk (1) : cache tag mask register r-x r-x r-x r-x r-x r-x r-x r-x ? ? ? ? ? ? ? ? bit 31 bit 24 r-x r-x r-x r-x r-x r-x r-x r-x ? ? ? ? ? ? ? ? bit 23 bit 16 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 lmask<15:8> bit 15 bit 8 r/w-0 r/w-0 r/w-0 r-x r-x r-x r-x r-x lmask<7:5> ? ? ? ? ? bit 7 bit 0 legend: r = readable bit w = writable bit p = programmable bit r = reserved bit u = unimplemented bit -n = bit value at por: (?0?, ?1?, x = unknown) bit 31-16 reserved: write ? 0 ?; ignore read bit 15-5 lmask<15:5>: line mask bits 1 = enables mask logic to force a match on the corresponding bit position in ltag (chetag<23:4>) and the physical address. 0 = only writable for values of cheidx (cheacc<3:0>) equal to oxoa and oxob. disables mask logic. bit 4-0 reserved: write ? 0 ?; ignore read note 1: the tag mask of the line pointed to by cheidx (cheacc<3:07>).
? 2008 microchip technology inc. preliminary ds61143e-page 185 pic32mx3xx/4xx register 9-5: chew0: cache word 0 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x chew0<31:24> bit 31 bit 24 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x chew0<23:16> bit 23 bit 16 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x chew0<15:8> bit 15 bit 8 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x chew0<7:0> bit 7 bit 0 legend: r = readable bit w = writable bit p = programmable bit r = reserved bit u = unimplemented bit -n = bit value at por: (?0?, ?1?, x = unknown) bit 31-0 chew0<31:0>: word 0 of the cache line selected by cheacc.cheidx readable only if the device is not code-protected.
pic32mx3xx/4xx ds61143e-page 186 preliminary ? 2008 microchip technology inc. register 9-6: chew1: cache word 1 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x chew1<31:24> bit 31 bit 24 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x chew1<23:16> bit 23 bit 16 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x chew1<15:8> bit 15 bit 8 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x chew1<7:0> bit 7 bit 0 legend: r = readable bit w = writable bit p = programmable bit r = reserved bit u = unimplemented bit -n = bit value at por: (?0?, ?1?, x = unknown) bit 31-0 chew1<31:0>: word 1 of the cache line selected by cheacc.cheidx readable only if the device is not code-protected.
? 2008 microchip technology inc. preliminary ds61143e-page 187 pic32mx3xx/4xx register 9-7: chew2 cache word 2 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x chew2<31:24> bit 31 bit 24 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x chew2<23:16> bit 23 bit 16 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x chew2<15:8> bit 15 bit 8 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x chew2<7:0> bit 7 bit 0 legend: r = readable bit w = writable bit p = programmable bit r = reserved bit u = unimplemented bit -n = bit value at por: (?0?, ?1?, x = unknown) bit 31-0 chew2<31:0>: word 2 of the cache line selected by cheacc.cheidx readable only if the device is not code-protected.
pic32mx3xx/4xx ds61143e-page 188 preliminary ? 2008 microchip technology inc. register 9-8: chew3 (1) : cache word 3 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x chew3<31:24> bit 31 bit 24 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x chew3<23:16> bit 23 bit 16 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x chew3<15:8> bit 15 bit 8 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x chew3<7:0> bit 7 bit 0 legend: r = readable bit w = writable bit p = programmable bit r = reserved bit u = unimplemented bit -n = bit value at por: (?0?, ?1?, x = unknown) bit 31-0 chew3<31:0>: word 3 of the cache line selected by cheacc.cheidx readable only if the device is not code-protected. note 1: this register is a window into the cache data array and is readable only if the device is not code-protected.
? 2008 microchip technology inc. preliminary ds61143e-page 189 pic32mx3xx/4xx register 9-9: chelru: cache lru register r-x r-x r-x r-x r-x r-x r-x r-0 ? ? ? ? ? ? ? chelru<24> bit 31 bit 24 r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 chelru<23-16> bit 23 bit 16 r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 chelru<15-8> bit 15 bit 8 r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 chelru<7-0> bit 7 bit 0 legend: r = readable bit w = writable bit p = programmable bit r = reserved bit u = unimplemented bit -n = bit value at por: (?0?, ?1?, x = unknown) bit 31-25 reserved: write ? 0 ?; ignore read bit 24-0 chelru<24:0>: cache least recently used state encoding bits chelru indicates the pseudo-lru state of the cache.
pic32mx3xx/4xx ds61143e-page 190 preliminary ? 2008 microchip technology inc. register 9-10: chehit: cache hit statistics register r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x chehit<31:24> bit 31 bit 24 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x chehit<23:16> bit 23 bit 16 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x chehit<15:8> bit 15 bit 8 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x chehit<7:0> bit 7 bit 0 legend: r = readable bit w = writable bit p = programmable bit r = reserved bit u = unimplemented bit -n = bit value at por: (?0?, ?1?, x = unknown) bit 31-0 chehit<31:0>: cache hit count bits incremented each time the processor issues an instruction fetch or load that hits the prefetch cache from a cacheable region. non-cacheable accesses do not modify this value.
? 2008 microchip technology inc. preliminary ds61143e-page 191 pic32mx3xx/4xx register 9-11: chemis: cache miss statistics register r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x chemis<31:24> bit 31 bit 24 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x chemis<23:16> bit 23 bit 16 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x chemis<15:8> bit 15 bit 8 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x chemis<7:0> bit 7 bit 0 legend: r = readable bit w = writable bit p = programmable bit r = reserved bit u = unimplemented bit -n = bit value at por: (?0?, ?1?, x = unknown) bit 31-0 chemis<31:0>: cache miss count bits incremented each time the processor issues an instruction fetch from a cacheable region that misses the prefetch cache. non-cacheable accesses do not modify this value.
pic32mx3xx/4xx ds61143e-page 192 preliminary ? 2008 microchip technology inc. register 9-12: chepfabt: prefetch cache abort statistics register r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x chepfabt<31:24> bit 31 bit 24 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x chepfabt<23:16> bit 23 bit 16 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x che pfabt<15:8> bit 15 bit 8 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x chepfabt<7:0> bit 7 bit 0 legend: r = readable bit w = writable bit p = programmable bit r = reserved bit u = unimplemented bit -n = bit value at por: (?0?, ?1?, x = unknown) bit 31-0 chepfabt<31:0>: prefab abort count bits incremented each time an automatic prefetch cache is aborted due to a non-sequential instruction fetch, load or store.
? 2008 microchip technology inc. preliminary ds61143e-page 193 pic32mx3xx/4xx 9.3 prefetch configuration the checon register controls the configurations available for instruction and data caching of program flash memory. in addition to normal instruction caching, the prefetch cache has the ability to cache lines specifically for flash memory data. the checon.dcsz field controls the number of lines allocated to program data caching. table 9-2 shows the cache line relationship for values of dcsz. the data caching capability is for read only data such as constants, parameters, table data, etc., that are not modified. table 9-2: program data cache the checon.prefen field controls predictive prefetching, which allows the prefetch module to spec- ulatively fetch the next 16-byte aligned set of instruc- tions. the prefetch module loads data into the data array only on accesses to cacheable regions (cca bits = 3). example 9-1: example code: initialization code for prefetch module 9.3.1 line locking each line in the cache can be locked to hold its con- tents. a line is locked if both lvalid = 1 and llock = 1 . if lvalid = 0 and llock = 1 , the prefetch module issues a preload request (see below). locking cache lines may reduce the performance of general program flow. however, if one or two functions calls consume a significant percent of overall process- ing, locking their address can provide improved perfor- mance. though any number of lines can be locked, the cache works most efficiently when locking either 1 or 4 lines. if locking 4 lines, choose lines whose line number divide by 4 have the same quotient. this locks an entire lru group which benefits the lru algorithm. for example, lines 8, 9, a, and b each have a quotient of 2 when divided by 4. if cache lines are manually filled, it is recommended that the following sequence be used: 1. choose a cache line to fill. 2. set the lock and valid bits of the cache line by writing to chetag. 3. write to each word of the cache line by writing to chew0, chew1, chew2, and chew3. example 9-2: example code: locking a line in prefetch module dcsz<1:0> lines allocated to program data 00 none 01 cache line number 15 10 cache line number 14 and 15 11 cache line number 12 through 15 /* prefetch cache initialization */ tmp = _cp0_get_config(); // read config register tmp |= 1; // kseg0 cacheable _cp0_set_config(tmp); // write config register checon = (1<<4) | 3; // 3 wait-states, // prefetching enabled for cached memory #define locked_line_num 3 /* lock first line of func1() in cache */ cheacc = (1<<31) | locked_line_num; tmp = (unsigned long)func1; ltagboot = (tmp & 0x00c00000) ? 0 : 1; chetag = (ltagboot<<31) | (tmp & 0x0007fff0) | 6; // locked and invalid
pic32mx3xx/4xx ds61143e-page 194 preliminary ? 2008 microchip technology inc. 9.3.2 preload behavior application code can direct the prefetch module to pre- form a preload of a cache line and lock it with instruc- tions or data from the flash. the preload function uses the cheacc.cheidx register field to select the cache line into which the load is directed. setting cheacc.chewen to a ? 1 ? enables writes to the chetag register. writing chetag.lvalid = 0 and chetag.llock = 1 causes a preload request to the prefetch module. the controller acknowledges the request in the cycle after the write and if possible stops any outstanding flash access and stalls any cpu load from the cache or flash. when it has finished or stalled the previous transac- tion, it initiates a flash read to fetch the instructions or data requested using the address in chetag.ltag. after the programmed number of wait states as defined by checon.pfmws, the controller updates the data array with the values read from flash. on the update it sets chetag.lvalid = 1 . the lru state of the line is not affected. once the controller finishes updating the cache, it allows cpu requests to complete. if this request misses the cache, the controller initiates a flash read which incurs the full flash access time. 9.3.3 address mask cache lines 10 and 11 allow masking of the cpu address and tag address to force a match on corre- sponding bits. the chemsk.lmask field is set up to compliment the interrupt vector spacing field in the cpu. this feature allows boot code to lock the first four instruction of a vector in the cache. if all vectors contain identical instructions in their first four locations, then setting the chemsk.lmask to match the vector spacing and the ltag to match the vector base address causes all the vector addresses to hit the cache. the prefetch module responds with zero wait states and immediately initiates a fetch of the next set of four instruction for the requesting vector if prefetch is enabled. using chemsk.lmask is restricted to aligned address ranges. its size allows for a max range of 32kb and a minimum spacing of 32b. using the two lines, in conjunction provides the ability to have differ- ent ranges and different spacing. setting up the address mask such that more than one line will match an address causes undefined results. therefore, it is highly recommended to set up masking before entering cacheable code. example 9-3: example code: duplication of code using mask registers #define int_line_num 10 cheacc = (1<<31) | int_line_num; tmp = (unsigned long)intbase; ltagboot = (tmp & 0x00c00000) ? 0 : 1; chetag = (ltagboot<<31) | (tmp & 0x0007fff0) | 6; // locked and invalid chemsk = 0xe0; // first 4 instructions of intbase() replicated 8 times on 32-byte boundaries
? 2008 microchip technology inc. preliminary ds61143e-page 195 pic32mx3xx/4xx 9.3.4 predictive prefetch behavior when configured for predictive prefetch on cacheable addresses, the module predicts the next line address and returns it into the pseudo lru line of the cache. if enabled, the prefetch function starts predicting based on the first cpu instruction fetch. when the first line is placed in the cache, the module simply increments the address to the next 16-byte aligned address and starts a flash access. when running linear code (i.e. no jumps), the flash returns the next set of instructions into the prefetch buffer on or before all instructions can be executed from the previous line. if at any time during a predicted flash access, a new cpu address does not match the predicted one, the flash access will be changed to the correct address. this behavior does not cause the cpu access to take any longer than without prediction. if an access that misses the cache hits the prefetch buffer, the instructions are placed in the pseudo lru line along with its address tag. the pseudo lru value is marked as the most recently used line and other lines are updated accordingly. if an access misses both the cache and the prefetch buffer, the access passes to the flash and those returning instructions are placed in the pseudo lru line. when configured for predictive prefetch on non- cacheable addresses, the controller only uses the prefetch buffer. the lru cache line is not updated for hits or fills so the cache remains intact. for linear code, enabling predictive prefetch for non-cacheable addresses allows the cpu to fetch instructions in zero wait states. it is not useful to use non-cacheable predictive prefetching when accesses to the flash are set for zero wait states. the controller holds prefetched instruc- tions on the output of the flash for up to 3 clock cycles (while the cpu is fetching from the buffer). this con- sumes more power without any benefit for zero wait state flash accesses. predictive data prefetching is not supported. however, a data access in the middle of a predictive instruction fetch causes the prefetch controller to stop the flash access for the instruction fetch and to start the data load from flash. the predictive prefetch does not resume, but instead waits for another instruction fetch. at which time, it either fills the buffer because of a miss, or starts a prefetch because of a hit. 9.3.5 coherency support it is not possible to execute out of cache while pro- gramming the flash memory. the flash controller stalls the cache during the programming sequence. there- fore, user code that initiates a programming sequence must not be located in a cacheable address region. if checon.checoh = 1, then coherency is strictly supported by invalidating, unlocking, and clearing masks for all lines whenever the flash program memory is written or programmed. if checon.checoh = 0, then only lines that are not locked are forced invalid. lines that are locked are retained. 9.4 prefetch module interrupts and exceptions the prefetch module does not generate any interrupts. exceptions can occur if cache lines are marked as valid manually by writing to individual chetag registers then executing code that hits one of these lines contain- ing invalid instructions. also manually placing data into an un-locked cache line may cause a coherency prob- lem from an eviction due to a cache miss in the middle of the loading algorithm. 9.5 i/o pin configuration the prefetch module does not use any external pins.
pic32mx3xx/4xx ds61143e-page 196 preliminary ? 2008 microchip technology inc. notes:
? 2008 microchip technology inc. preliminary ds61143e-page 197 pic32mx3xx/4xx 10.0 direct memory access (dma) controller the pic32mx direct memory access (dma) controller is a bus master module useful for data transfers between different devices without the cpu interven- tion. the source and destination of a dma transfer can be any of the memory mapped modules existent in the pic32mx (such as peripheral bus (pbus) devices: spi, uart, i 2 c?, etc.) or memory itself. following are some of the key features of the dma controller module: ? four identical channels, each featuring: - auto-increment source and destination address registers - source and destination pointers ? automatic word-size detection: - transfer granularity, down to byte level - bytes need not be word-aligned at source and destination ? fixed priority channel arbitration ? flexible dma channel operating modes: - manual (software) or automatic (interrupt) dma requests - one-shot or auto-repeat block transfer modes - channel-to-channel chaining ? flexible dma requests: - a dma request can be selected from any of the peripheral interrupt sources - each channel can select any (appropriate) observable interrupt as its dma request source - a dma transfer abort can be selected from any of the peripheral interrupt sources - pattern (data) match transfer termination ? multiple dma channel status interrupts: - dma channel block transfer complete - source empty or half empty - destination full or half-full - dma transfer aborted due to an external event - invalid dma address generated ? dma debug support features: - most recent address accessed by a dma channel - most recent dma channel to transfer data ? crc generation module: - crc module can be assigned to any of the available channels - crc module is highly configurable note: this data sheet summarizes the features of the pic32mx3xx/4xx family of devices. it is not intended to be a comprehensive refer- ence source. refer to the ?pic32mx family reference manual? (ds61132) for a detailed description of this peripheral. table 10-1: dma controller features transfer length unaligned transfers different source and destination sizes memory to memory transfers memory to peripheral transfers channel auto-enable events start/stop pattern match detection channel chaining crc calculation <= 256b yes yes yes yes yes yes yes yes yes
pic32mx3xx/4xx ds61143e-page 198 preliminary ? 2008 microchip technology inc. figure 10-1: dma cont roller block diagram 10.1 dma controller registers table 10-2: dma global sfr summary peripheral bus address decoder channel 0 control channel 1 control channel n control global control (dmacon) bus interface channel priority arbitration s e l s e l y i 0 i 1 i 2 i n system irq device bus + bus arbitration int controller virtual address name bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 bf88_3000 dmacon 31:24 ? ? ? ? ? ? ? ? 23:16 ? ? ? ? ? ? ? ? 15:8 on frz sidl suspend ? ? ? ? 7:0 ? ? ? ? ? ? ? bf88_3004 dmaconclr 31:0 write clears selected bits in dmacon, read yields undefined value bf88_3008 dmaconset 31:0 write sets selected bits in dmacon, read yields undefined value bf88_300c dmaconinv 31:0 write inverts selected bits in dmacon, read yields undefined value bf88_3010 dmastat 31:24 ? ? ? ? ? ? ? ? 23:16 ? ? ? ? ? ? ? ? 15:8 ? ? ? ? ? ? ? ? 7:0 ? ? ? ? rdwr ? dmach<1:0> bf88_3020 dmaaddr 31:24 dmaaddr<31:24> 23:16 dmaaddr<23:16> 15:8 dmaaddr<15:8> 7:0 dmaaddr<7:0>
? 2008 microchip technology inc. preliminary ds61143e-page 199 pic32mx3xx/4xx table 10-3: dma crc sfr summary virtual address name bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 bf88_3030 dcrccon 31:24 ? ? ? ? ? ? ? ? 23:16 ? ? ? ? ? ? ? ? 15:8 ? ? ? ? plen<3:0> 7:0 crcen crcapp ? ? ? ? crcch<1:0> bf88_3034 dcrcconclr 31:0 write clears selected bits in dcrccon, read yields undefined value bf88_3038 dcrcconset 31:0 write sets selected bits in dcrccon, read yields undefined value bf88_303c dcrcconinv 31:0 write inverts selected bits in dcrccon, read yields undefined value bf88_3040 dcrcdata 31:24 ? ? ? ? ? ? ? ? 23:16 ? ? ? ? ? ? ? ? 15:8 dcrcdata<15:8> 7:0 dcrcdata<7:0> bf88_3044 dcrcdataclr 31:0 write clears selected bits in dcrcdata, read yields undefined value bf88_3048 dcrcdataset 31:0 write sets selected bits in dcrcdata, read yields undefined value bf88_304c dcrcdatainv 31:0 write inverts selected bits in dcrcdata, read yields undefined value bf88_3050 dcrcxor 31:24 ? ? ? ? ? ? ? ? 23:16 ? ? ? ? ? ? ? ? 15:8 dcrcxor<15:8> 7:0 dcrcxor<7:0> bf88_3054 dcrcxorclr 31:0 write clears selected bits in dcrcxor, read yields undefined value bf88_3058 dcrcxorset 31:0 write sets selected bits in dcrcxor, read yields undefined value bf88_305c dcrcxorinv 31:0 write inverts selected bits in dcrcxor, read yields undefined value table 10-4: dma channel 0 sfr summary virtual address (1) name bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 bf88_3060 dch0con 31:24 ? ? ? ? ? ? ? ? 23:16 ? ? ? ? ? ? ? ? 15:8 ? ? ? ? ? ? ? chchns 7:0 chen chaed chchn chaen ? chedet chpri<1:0> bf88_3064 dch0conclr 31:0 write clears selected bits in dch0con, read yields undefined value bf88_3068 dch0conset 31:0 write sets selected bits in dch0con, read yields undefined value bf88_306c dch0coninv 31:0 write inverts selected bits in dch0con, read yields undefined value bf88_3070 dch0econ 31:24 ? ? ? ? ? ? ? ? 23:16 chairq<7:0> 15:8 chsirq<7:0> 7:0 cforce cabort paten sirqen airqen ? ? ? bf88_3074 dch0econclr 31:0 write clears selected bits in dch0econ, read yields undefined value bf88_3078 dch0econset 31:0 write sets selected bits in dch0econ, read yields undefined value bf88_307c dch0econinv 31:0 write inverts selected bits in dch0econ, read yields undefined value bf88_3080 dch0int 31:24 ? ? ? ? ? ? ? ? 23:16 chsdie chshie chddie chdhie chbcie chccie chtaie cherie 15:8 ? ? ? ? ? ? ? ? 7:0 chsdif chshif chddif chdhif chbcif chccif chtaif cherif bf88_3084 dch0intclr 31:0 write clears selected bits in dch0int, read yields undefined value bf88_3088 dch0intset 31:0 write sets selected bits in dch0int, read yields undefined value bf88_308c dch0intinv 31:0 write inverts selected bits in dch0int, read yields undefined value bf88_3090 dch0ssa 31:24 chssa<31:24> 23:16 chssa<23:16> 15:8 chssa<15:8> 7:0 chssa<7:0> bf88_3094 dch0ssaclr 31:0 write clears selected bits in dch0ssa, read yields undefined value bf88_3098 dch0ssaset 31:0 write sets selected bits in dch0ssa, read yields undefined value bf88_309c dch0ssainv 31:0 write inverts selected bits in dch0ssa, read yields undefined value note 1: the starting address of the registers for dma channel n is 0xbf883060 + 0xc0*n.
pic32mx3xx/4xx ds61143e-page 200 preliminary ? 2008 microchip technology inc. bf88_30a0 dch0dsa 31:24 chdsa<31:24> 23:16 chdsa<23:16> 15:8 chdsa<15:8> 7:0 chdsa<7:0> bf88_30a4 dch0dsaclr 31:0 write clears selected bits in dch0dsa, read yields undefined value bf88_30a8 dch0dsaset 31:0 write sets selected bits in dch0dsa, read yields undefined value bf88_30ac dch0dsainv 31:0 write inverts selected bits in dch0dsa, read yields undefined value bf88_30b0 dch0ssiz 31:24 ? ? ? ? ? ? ? ? 23:16 ? ? ? ? ? ? ? ? 15:8 ? ? ? ? ? ? ? ? 7:0 chssiz<7:0> bf88_30b4 dch0ssizclr 31:0 write clears selected bits in dch0ssiz, read yields undefined value bf88_30b8 dch0ssizset 31:0 write sets selected bits in dch0ssiz, read yields undefined value bf88_30bc dch0ssizinv 31:0 write inverts selected bits in dch0ssiz, read yields undefined value bf88_30c0 dch0dsiz 31:24 ? ? ? ? ? ? ? ? 23:16 ? ? ? ? ? ? ? ? 15:8 ? ? ? ? ? ? ? ? 7:0 chdsiz<7:0> bf88_30c4 dch0dsizclr 31:0 write clears selected bits in dch0dsiz, read yields undefined value bf88_30c8 dch0dsizset 31:0 write sets selected bits in dch0dsiz, read yields undefined value bf88_30cc dch0dsizinv 31:0 write inverts selected bits in dch0dsiz, read yields undefined value bf88_30d0 dch0sptr 31:24 ? ? ? ? ? ? ? ? 23:16 ? ? ? ? ? ? ? ? 15:8 ? ? ? ? ? ? ? ? 7:0 chstr<7:0> bf88_30e0 dch0dptr 31:24 ? ? ? ? ? ? ? ? 23:16 ? ? ? ? ? ? ? ? 15:8 ? ? ? ? ? ? ? ? 7:0 chdptr<7:0> bf88_30f0 dch0csiz 31:24 ? ? ? ? ? ? ? ? 23:16 ? ? ? ? ? ? ? ? 15:8 ? ? ? ? ? ? ? ? 7:0 chcsiz<7:0> bf88_30f4 dch0csizclr 31:0 write clears selected bits in dch0csiz, read yields undefined value bf88_30f8 dch0csizset 31:0 write sets selected bits in dch0csiz, read yields undefined value bf88_30fc dch0csizinv 31:0 write inverts selected bits in dch0csiz, read yields undefined value bf88_3100 dch0cptr 31:24 ? ? ? ? ? ? ? ? 23:16 ? ? ? ? ? ? ? ? 15:8 ? ? ? ? ? ? ? ? 7:0 chcptr<7:0> bf88_3110 dch0dat 31:24 ? ? ? ? ? ? ? ? 23:16 ? ? ? ? ? ? ? ? 15:8 ? ? ? ? ? ? ? ? 7:0 chpdat<7:0> bf88_3114 dch0datclr 31:0 write clears selected bits in dch0dat, read yields undefined value bf88_3118 dch0datset 31:0 write sets selected bits in dch0dat, read yields undefined value bf88_311c dch0datinv 31:0 write inverts selected bits in dch0dat, read yields undefined value table 10-4: dma channel 0 sfr summary (continued) virtual address (1) name bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 note 1: the starting address of the registers for dma channel n is 0xbf883060 + 0xc0*n.
? 2008 microchip technology inc. preliminary ds61143e-page 201 pic32mx3xx/4xx table 10-5: dma channel 0 interrupt register summary (1) virtual address name bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 bf88_1070 iec1 23:16 ? ? ? ? dma3ie dma2ie dma1ie dma0ie bf88_1040 ifs1 23:16 ? ? ? ? dma3if dma2if dma1if dma0if bf88_1120 ipc9 7:0 ? ? ? dma0ip<2:0> dma0is<1:0> note 1: this summary table contains partial register definitions that only pertain to the dma peripheral. refer to the pic32mx family r eference manual (ds61132) for a detailed description of these registers. table 10-6: dma channel 1 sfr summary virtual address name bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 bf88_3120 dch1con 31:24 ? ? ? ? ? ? ? ? 23:16 ? ? ? ? ? ? ? ? 15:8 ? ? ? ? ? ? ? chchns 7:0 chen chaed chchn chaen ? chedet chpri<1:0> bf88_3124 dch1conclr 31:0 write clears selected bits in dch1con, read yields undefined value bf88_3128 dch1conset 31:0 write sets selected bits in dch1con, read yields undefined value bf88_312c dch1coninv 31:0 write inverts selected bits in dch1con, read yields undefined value bf88_3130 dch1econ 31:24 ? ? ? ? ? ? ? ? 23:16 chairq<7:0> 15:8 chsirq<7:0> 7:0 cforce cabort paten sirqen airqen - ? ? bf88_3134 dch1econclr 31:0 write clears selected bits in dch1econ, read yields undefined value bf88_3138 dch1econset 31:0 write sets selected bits in dch1econ, read yields undefined value bf88_313c dch1econinv 31:0 write inverts selected bits in dch1econ, read yields undefined value bf88_3140 dch1int 31:24 ? ? ? ? ? ? ? ? 23:16 chsdie chshie chddie chdhie chbcie chccie chtaie cherie 15:8 ? ? ? ? ? ? ? ? 7:0 chsdif chshif chddif chdhif chbcif chccif chtaif cherif bf88_3144 dch1intclr 31:0 write clears selected bits in dch1int, read yields undefined value bf88_3148 dch1intset 31:0 write sets selected bits in dch1int, read yields undefined value bf88_314c dch1intinv 31:0 write inverts selected bits in dch1int, read yields undefined value bf88_3150 dch1ssa 31:24 chssa<31:24> 23:16 chssa<23:16> 15:8 chssa<15:8> 7:0 chssa<7:0> bf88_3154 dch1ssaclr 31:0 write clears selected bits in dch1ssa, read yields undefined value bf88_3158 dch1ssaset 31:0 write sets selected bits in dch1ssa, read yields undefined value bf88_315c dch1ssainv 31:0 write inverts selected bits in dch1ssa, read yields undefined value bf88_3160 dch1dsa 31:24 chdsa<31:24> 23:16 chdsa<23:16> 15:8 chdsa<15:8> 7:0 chdsa<7:0> bf88_3164 dch1dsaclr 31:0 write clears selected bits in dch1dsa, read yields undefined value bf88_3168 dch1dsaset 31:0 write sets selected bits in dch1dsa, read yields undefined value bf88_316c dch1dsainv 31:0 write inverts selected bits in dch1dsa, read yields undefined value bf88_3170 dch1ssiz 31:24 ? ? ? ? ? ? ? ? 23:16 ? ? ? ? ? ? ? ? 15:8 ? ? ? ? ? ? ? ? 7:0 chssiz<7:0> bf88_3174 dch1ssizclr 31:0 write clears selected bits in dch1ssiz, read yields undefined value bf88_3178 dch1ssizset 31:0 write sets selected bits in dch1ssiz, read yields undefined value bf88_317c dch1ssizinv 31:0 write inverts selected bits in dch1ssiz, read yields undefined value note 1: the starting address of the registers for dma channel n is 0xbf883060 + 0xc0*n.
pic32mx3xx/4xx ds61143e-page 202 preliminary ? 2008 microchip technology inc. table 10-7: dma channel 1 interrupt register summary (1) bf88_3180 dch1dsiz 31:24 ? ? ? ? ? ? ? ? 23:16 ? ? ? ? ? ? ? ? 15:8 ? ? ? ? ? ? ? ? 7:0 chdsiz<7:0> bf88_3184 dch1dsizclr 31:0 write clears selected bits in dch1dsiz, read yields undefined value bf88_3188 dch1dsizset 31:0 write sets selected bits in dch1dsiz, read yields undefined value bf88_318c dch1dsizinv 31:0 write inverts selected bits in dch1dsiz, read yields undefined value bf88_3190 dch1sptr 31:24 ? ? ? ? ? ? ? ? 23:16 ? ? ? ? ? ? ? ? 15:8 ? ? ? ? ? ? ? ? 7:0 chsptr<7:0> bf88_31a0 dch1dptr 31:24 ? ? ? ? ? ? ? ? 23:16 ? ? ? ? ? ? ? ? 15:8 ? ? ? ? ? ? ? ? 7:0 chdptr<7:0> bf88_31b0 dch1csiz 31:24 ? ? ? ? ? ? ? ? 23:16 ? ? ? ? ? ? ? ? 15:8 ? ? ? ? ? ? ? ? 7:0 chcsiz<7:0> bf88_31b4 dch1csizclr 31:0 write clears selected bits in dch1csiz, read yields undefined value bf88_31b8 dch1csizset 31:0 write sets selected bits in dch1csiz, read yields undefined value bf88_31bc dch1csizinv 31:0 write inverts selected bits in dch1csiz, read yields undefined value bf88_31c0 dch1cptr 31:24 ? ? ? ? ? ? ? ? 23:16 ? ? ? ? ? ? ? ? 15:8 ? ? ? ? ? ? ? ? 7:0 chcptr<7:0> bf88_31d0 dch1dat 31:24 ? ? ? ? ? ? ? ? 23:16 ? ? ? ? ? ? ? ? 15:8 ? ? ? ? ? ? ? ? 7:0 chpdat<7:0> bf88_31d4 dch1datclr 31:0 write clears selected bits in dch1dat, read yields undefined value bf88_31d8 dch1datset 31:0 write sets selected bits in dch1dat, read yields undefined value bf88_31dc dch1datinv 31:0 write inverts selected bits in dch1dat, read yields undefined value table 10-6: dma channel 1 sfr summary (continued) virtual address name bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 note 1: the starting address of the registers for dma channel n is 0xbf883060 + 0xc0*n. virtual address name bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 bf88_1070 iec1 23:16 ? ? ? ? dma3ie dma2ie dma1ie dma0ie bf88_1040 ifs1 23:16 ? ? ? ? dma3if dma2if dma1if dma0if bf88_1120 ipc9 15:8 ? ? ? dma1ip<2:0> dma1is<1:0> note 1: this summary table contains partial register definitions that only pertain to the dma peripheral. refer to the ? pic32mx family reference manual ? (ds61132) for a detailed description of these registers.
? 2008 microchip technology inc. preliminary ds61143e-page 203 pic32mx3xx/4xx table 10-8: dma channel 2 sfr summary virtual address (1) name bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 bf88_31e0 dch2con 31:24 ? ? ? ? ? ? ? ? 23:16 ? ? ? ? ? ? ? ? 15:8 ? ? ? ? ? ? ? chchns 7:0 chen chaed chchn chaen ? chedet chpri<1:0> bf88_31e4 dch2conclr 31:0 write clears selected bits in dch2con, read yields undefined value bf88_31e8 dch2conset 31:0 write sets selected bits in dch2con, read yields undefined value bf88_31ec dch2coninv 31:0 write inverts selected bits in dch2con, read yields undefined value bf88_31f0 dch2econ 31:24 ? ? ? ? ? ? ? ? 23:16 chairq<7:0> 15:8 chsirq<7:0> 7:0 cforce cabort paten sirqen airqen ? ? ? bf88_31f4 dch2econclr 31:0 write clears selected bits in dch2econ, read yields undefined value bf88_31f8 dch2econset 31:0 write sets selected bits in dch2econ, read yields undefined value bf88_31fc dch2econinv 31:0 write inverts selected bits in dch2econ, read yields undefined value bf88_3200 dch2int 31:24 ? ? ? ? ? ? ? ? 23:16 chsdie chshie chddie chdhie chbcie chccie chtaie cherie 15:8 ? ? ? ? ? ? ? ? 7:0 chsdif chshif chddif chdhif chbcif chccif chtaif cherif bf88_3204 dch2intclr 31:0 write clears selected bits in dch2int, read yields undefined value bf88_3208 dch2intset 31:0 write sets selected bits in dch2int, read yields undefined value bf88_320c dch2intinv 31:0 write inverts selected bits in dch2int, read yields undefined value bf88_3210 dch2ssa 31:24 chssa<31:24> 23:16 chssa<23:16> 15:8 chssa<15:8> 7:0 chssa<7:0> bf88_3214 dch2ssaclr 31:0 write clears selected bits in dch2ssa, read yields undefined value bf88_3218 dch2ssaset 31:0 write sets selected bits in dch2ssa, read yields undefined value bf88_321c dch2ssainv 31:0 write inverts selected bits in dch2ssa, read yields undefined value bf88_3220 dch2dsa 31:24 chdsa<31:24> 23:16 chdsa<23:16> 15:8 chdsa<15:8> 7:0 chdsa<7:0> bf88_3224 dch2dsaclr 31:0 write clears selected bits in dch2dsa, read yields undefined value bf88_3228 dch2dsaset 31:0 write sets selected bits in dch2dsa, read yields undefined value bf88_322c dch2dsainv 31:0 write inverts selected bits in dch2dsa, read yields undefined value bf88_3230 dch2ssiz 31:24 ? ? ? ? ? ? ? ? 23:16 ? ? ? ? ? ? ? ? 15:8 ? ? ? ? ? ? ? ? 7:0 chssiz<7:0> bf88_3234 dch2ssizclr 31:0 write clears selected bits in dch2ssiz, read yields undefined value bf88_3238 dch2ssizset 31:0 write sets selected bits in dch2ssiz, read yields undefined value bf88_323c dch2ssizinv 31:0 write inverts selected bits in dch2ssiz, read yields undefined value bf88_3240 dch2dsiz 31:24 ? ? ? ? ? ? ? ? 23:16 ? ? ? ? ? ? ? ? 15:8 ? ? ? ? ? ? ? ? 7:0 chdsiz<7:0> bf88_3244 dch2dsizclr 31:0 write clears selected bits in dch2dsiz, read yields undefined value bf88_3248 dch2dsizset 31:0 write sets selected bits in dch2dsiz, read yields undefined value bf88_324c dch2dsizinv 31:0 write inverts selected bits in dch2dsiz, read yields undefined value note 1: the starting address of the registers for dma channel n is 0xbf883060 + 0xc0*n.
pic32mx3xx/4xx ds61143e-page 204 preliminary ? 2008 microchip technology inc. table 10-9: dma channel 2 interrupt register summary (1) bf88_3250 dch2sptr 31:24 ? ? ? ? ? ? ? ? 23:16 ? ? ? ? ? ? ? ? 15:8 ? ? ? ? ? ? ? ? 7:0 chsptr<7:0> bf88_3260 dch2dptr 31:24 ? ? ? ? ? ? ? ? 23:16 ? ? ? ? ? ? ? ? 15:8 ? ? ? ? ? ? ? ? 7:0 chdptr<7:0> bf88_3270 dch2csiz 31:24 ? ? ? ? ? ? ? ? 23:16 ? ? ? ? ? ? ? ? 15:8 ? ? ? ? ? ? ? ? 7:0 chcsiz<7:0> bf88_3274 dch2csizclr 31:0 write clears selected bits in dch2csiz, read yields undefined value bf88_3278 dch2csizset 31:0 write sets selected bits in dch2csiz, read yields undefined value bf88_327c dch2csizinv 31:0 write inverts selected bits in dch2csiz, read yields undefined value bf88_3280 dch2cptr 31:24 ? ? ? ? ? ? ? ? 23:16 ? ? ? ? ? ? ? ? 15:8 ? ? ? ? ? ? ? ? 7:0 chcptr<7:0> bf88_3290 dch2dat 31:24 ? ? ? ? ? ? ? ? 23:16 ? ? ? ? ? ? ? ? 15:8 ? ? ? ? ? ? ? ? 7:0 chpdat<7:0> bf88_3294 dch2datclr 31:0 write clears selected bits in dch2dat, read yields undefined value bf88_3298 dch2datset 31:0 write sets selected bits in dch2dat, read yields undefined value bf88_329c dch2datinv 31:0 write inverts selected bits in dch2dat, read yields undefined value virtual address name bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 bf88_1070 iec1 23:16 ? ? ? ? dma3ie dma2ie dma1ie dma0ie bf88_1040 ifs1 23:16 ? ? ? ? dma3if dma2if dma1if dma0if bf88_1120 ipc9 23:16 ? ? ? dma2ip<2:0> dma2is<1:0> note 1: this summary table contains partial register definitions that only pertain to the dma peripheral. refer to the pic32mx family r eference manual (ds61132) for a detailed description of these registers. table 10-8: dma channel 2 sfr summary (continued) virtual address (1) name bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 note 1: the starting address of the registers for dma channel n is 0xbf883060 + 0xc0*n.
? 2008 microchip technology inc. preliminary ds61143e-page 205 pic32mx3xx/4xx table 10-10: dma channel 3 sfr summary virtual address (1) name bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 bf88_32a0 dch3con 31:24 ? ? ? ? ? ? ? ? 23:16 ? ? ? ? ? ? ? ? 15:8 ? ? ? ? ? ? ? chchns 7:0 chen chaed chchn chaen ? chedet chpri<1:0> bf88_32a4 dch3conclr 31:0 write clears selected bits in dch3con, read yields undefined value bf88_32a8 dch3conset 31:0 write sets selected bits in dch3con, read yields undefined value bf88_32ac dch3coninv 31:0 write inverts selected bits in dch3con, read yields undefined value bf88_32b0 dch3econ 31:24 ? ? ? ? ? ? ? ? 23:16 chairq<7:0> 15:8 chsirq<7:0> 7:0 cforce cabort paten sirqen airqen ? ? ? bf88_32b4 dch3econclr 31:0 write clears selected bits in dch3econ, read yields undefined value bf88_32b8 dch3econset 31:0 write sets selected bits in dch3econ, read yields undefined value bf88_32bc dch3econinv 31:0 write inverts selected bits in dch3econ, read yields undefined value bf88_32c0 dch3int 31:24 ? ? ? ? ? ? ? ? 23:16 chsdie chshie chddie chdhie chbcie chccie chtaie cherie 15:8 ? ? ? ? ? ? ? ? 7:0 chsdif chshif chddif chdhif chbcif chccif chtaif cherif bf88_32c4 dch3intclr 31:0 write clears selected bits in dch3int, read yields undefined value bf88_32c8 dch3intset 31:0 write sets selected bits in dch3int, read yields undefined value bf88_32cc dch3intinv 31:0 write inverts selected bits in dch3int, read yields undefined value bf88_32d0 dch3ssa 31:24 chssa<31:24> 23:16 chssa<23:16> 15:8 chssa<15:8> 7:0 chssa<7:0> bf88_32d4 dch3ssaclr 31:0 write clears selected bits in dch3ssa, read yields undefined value bf88_32d8 dch3ssaset 31:0 write sets selected bits in dch3ssa, read yields undefined value bf88_32dc dch3ssainv 31:0 write inverts selected bits in dch3ssa, read yields undefined value bf88_32e0 dch3dsa 31:24 chdsa<31:24> 23:16 chdsa<23:16> 15:8 chdsa<15:8> 7:0 chdsa<7:0> bf88_32e4 dch3dsaclr 31:0 write clears selected bits in dch3dsa, read yields undefined value bf88_32e8 dch3dsaset 31:0 write sets selected bits in dch3dsa, read yields undefined value bf88_32ec dch3dsainv 31:0 write inverts selected bits in dch3dsa, read yields undefined value bf88_32f0 dch3ssiz 31:24 ? ? ? ? ? ? ? ? 23:16 ? ? ? ? ? ? ? ? 15:8 ? ? ? ? ? ? ? ? 7:0 chssiz<7:0> bf88_32f4 dch3ssizclr 31:0 write clears selected bits in dch3ssiz, read yields undefined value bf88_32f8 dch3ssizset 31:0 write sets selected bits in dch3ssiz, read yields undefined value bf88_32fc dch3ssizinv 31:0 write inverts selected bits in dch3ssiz, read yields undefined value bf88_3300 dch3dsiz 31:24 ? ? ? ? ? ? ? ? 23:16 ? ? ? ? ? ? ? ? 15:8 ? ? ? ? ? ? ? ? 7:0 chdsiz<7:0> bf88_3304 dch3dsizclr 31:0 write clears selected bits in dch3dsiz, read yields undefined value bf88_3308 dch3dsizset 31:0 write sets selected bits in dch3dsiz, read yields undefined value bf88_330c dch3dsizinv 31:0 write inverts selected bits in dch3dsiz, read yields undefined value bf88_3310 dch3sptr 31:24 ? ? ? ? ? ? ? ? 23:16 ? ? ? ? ? ? ? ? 15:8 ? ? ? ? ? ? ? ? 7:0 chsptr<7:0> note 1: the starting address of the registers for dma channel n is 0xbf883060 + 0xc0*n.
pic32mx3xx/4xx ds61143e-page 206 preliminary ? 2008 microchip technology inc. table 10-11: dma channel 3 interrupt register summary bf88_3320 dch3dptr 31:24 ? ? ? ? ? ? ? ? 23:16 ? ? ? ? ? ? ? ? 15:8 ? ? ? ? ? ? ? ? 7:0 chdptr<7:0> bf88_3330 dch3csiz 31:24 ? ? ? ? ? ? ? ? 23:16 ? ? ? ? ? ? ? ? 15:8 ? ? ? ? ? ? ? ? 7:0 chcsiz<7:0> bf88_3334 dch3csizclr 31:0 write clears selected bits in dch3csiz, read yields undefined value bf88_3338 dch3csizset 31:0 write sets selected bits in dch3csiz, read yields undefined value bf88_333c dch3csizinv 31:0 write inverts selected bits in dch3csiz, read yields undefined value bf88_3340 dch3cptr 31:24 ? ? ? ? ? ? ? ? 23:16 ? ? ? ? ? ? ? ? 15:8 ? ? ? ? ? ? ? ? 7:0 chcptr<7:0> bf88_3350 dch3dat 31:24 ? ? ? ? ? ? ? ? 23:16 ? ? ? ? ? ? ? ? 15:8 ? ? ? ? ? ? ? ? 7:0 chpdat<7:0> bf88_3354 dch3datclr 31:0 write clears selected bits in dch3dat, read yields undefined value bf88_3358 dch3datset 31:0 write sets selected bits in dch3dat, read yields undefined value bf88_335c dch3datinv 31:0 write inverts selected bits in dch3dat, read yields undefined value table 10-10: dma channel 3 sfr summary (continued) virtual address (1) name bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 note 1: the starting address of the registers for dma channel n is 0xbf883060 + 0xc0*n. virtual address name bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 bf88_1070 iec1 23:16 ? ? ? ?dma3ie dma2ie dma1ie dma0ie bf88_1040 ifs1 23:16 ? ? ? ?dma3if dma2if dma1if dma0if bf88_1120 ipc9 31:24 ? ? ? dma3ip<2:0> dma3is<1:0> note 1: this summary table contains partial register definitions that only pertain to the dma peripheral. refer to the pic32mx family r eference manual (ds61132) for a detailed description of these registers.
? 2008 microchip technology inc. preliminary ds61143e-page 207 pic32mx3xx/4xx register 10-1: dmacon: dma controller control register r-x r-x r-x r-x r-x r-x r-x r-x ? ? ? ? ? ? ? ? bit 31 bit 24 r-x r-x r-x r-x r-x r-x r-x r-x ? ? ? ? ? ? ? ? bit 23 bit 16 r/w-0 r/w-0 r/w-0 r/w-0 r-x r-x r-x r-x on frz sidl suspend ? ? ? ? bit 15 bit 8 r-x r-x r-x r-x r-x r-x r-x r-x ? ? ? ? ? ? ? ? bit 7 bit 0 legend: r = readable bit w = writable bit p = programmable bit r = reserved bit u = unimplemented bit -n = bit value at por: (?0?, ?1?, x = unknown) bit 31-16 reserved: write ? 0 ?; ignore read bit 15 on: dma on bit 1 = dma module is enabled 0 = dma module is disabled bit 14 frz: dma freeze bit (1) 1 = dma is frozen during debug mode 0 = dma continues to run during debug mode note: frz is writable in debug exception mode only, it is forced to ? 0 ? in normal mode. bit 13 sidl: stop in idle mode bit 1 = dma transfers are frozen during sleep 0 = dma transfers continue during sleep bit 12 suspend: dma suspend bit 1 = dma transfers are suspended to allow cpu uninterrupted access to data bus 0 = dma operates normally bit 11-0 reserved: write ? 0 ?; ignore read
pic32mx3xx/4xx ds61143e-page 208 preliminary ? 2008 microchip technology inc. register 10-2: dmastat: dma status register (1) r-x r-x r-x r-x r-x r-x r-x r-x ? ? ? ? ? ? ? ? bit 31 bit 24 r-x r-x r-x r-x r-x r-x r-x r-x ? ? ? ? ? ? ? ? bit 23 bit 16 r-x r-x r-x r-x r-x r-x r-x r-x ? ? ? ? ? ? ? ? bit 15 bit 8 r-x r-x r-x r-x r-0 r-x r-0 r-0 ? ? ? ? rdwr ? dmach<1:0> bit 7 bit 0 legend: r = readable bit w = writable bit p = programmable bit r = reserved bit u = unimplemented bit -n = bit value at por: (?0?, ?1?, x = unknown) bit 31-4 reserved: write ? 0 ?; ignore read bit 3 rdwr: read/write status bit 1 = last dma bus access was a read 0 = last dma bus access was a write bit 2 reserved: write ? 0 ?; ignore read bit 1-0 dmach<1:0>: dma channel bits note 1: this register contains the value of the most recent active dma channel.
? 2008 microchip technology inc. preliminary ds61143e-page 209 pic32mx3xx/4xx register 10-3: dmaaddr: dma address register (1) r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 dmaaddr<31:24> bit 31 bit 24 r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 dmaaddr<23:16> bit 23 bit 16 r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 dmaaddr<15:8> bit 15 bit 8 r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 dmaaddr<7:0> bit 7 bit 0 legend: r = readable bit w = writable bit p = programmable bit r = reserved bit u = unimplemented bit -n = bit value at por: (?0?, ?1?, x = unknown) bit 31-0 dmaaddr<31:0>: dma module address bits note 1: this register contains the address of the most recent dma access.
pic32mx3xx/4xx ds61143e-page 210 preliminary ? 2008 microchip technology inc. register 10-4: dcrccon: dm a crc control register r-x r-x r-x r-x r-x r-x r-x r-x ? ? ? ? ? ? ? ? bit 31 bit 24 r-x r-x r-x r-x r-x r-x r-x r-x ? ? ? ? ? ? ? ? bit 23 bit 16 r-x r-x r-x r-x r/w-0 r/w-0 r/w-0 r/w-0 ? ? ? ? plen<3:0> bit 15 bit 8 r/w-0 r/w-0 r-x r-x r-x r-x r/w-0 r/w-0 crcen crcapp ? ? ? ? crcch<1:0> bit 7 bit 0 legend: r = readable bit w = writable bit p = programmable bit r = reserved bit u = unimplemented bit -n = bit value at por: (?0?, ?1?, x = unknown) bit 31-12 reserved: write ? 0 ?; ignore read bit 11-8 plen<3:0>: polynomial length bits denotes the length of the polynomial ?1. bit 7 crcen: crc enable bit 1 = crc module is enabled and channel transfers are routed through the crc module 0 = crc module is disabled and channel transfers proceed normally bit 6 crcapp: crc append mode bit 1 = data read will be passed to the crc, to be included in the crc calculation, but is not written to the destination register. when a block transfer completes, the calculated crc will be written to the location given by dchxdsa 0 = channel behaves normally, with the crc being calculated as data is transferred from the source to the destination bit 5-2 reserved: write ? 0 ?; ignore read bit 1-0 crcch<1:0>: crc channel select bits 11 = crc is assigned to channel 3 10 = crc is assigned to channel 2 01 = crc is assigned to channel 1 00 = crc is assigned to channel 0
? 2008 microchip technology inc. preliminary ds61143e-page 211 pic32mx3xx/4xx register 10-5: dcrcdata: dma crc data register r-x r-x r-x r-x r-x r-x r-x r-x ? ? ? ? ? ? ? ? bit 31 bit 24 r-x r-x r-x r-x r-x r-x r-x r-x ? ? ? ? ? ? ? ? bit 23 bit 16 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 dcrcdata<15:8> bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 dcrcdata<7:0> bit 7 bit 0 legend: r = readable bit w = writable bit p = programmable bit r = reserved bit u = unimplemented bit -n = bit value at por: (?0?, ?1?, x = unknown) bit 31-16 reserved: write ? 0 ?; ignore read bit 15-0 dcrcdata<15:0>: crc data register bits writing to this register will seed the crc generator. reading from this register will return the current value of the crc. bits > plen will return ? 0 ? on any read.
pic32mx3xx/4xx ds61143e-page 212 preliminary ? 2008 microchip technology inc. register 10-6: dcrcxor: dma crc xor enable register (1) r-x r-x r-x r-x r-x r-x r-x r-x ? ? ? ? ? ? ? ? bit 31 bit 24 r-x r-x r-x r-x r-x r-x r-x r-x ? ? ? ? ? ? ? ? bit 23 bit 16 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 dcrcxor<15:8> bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 dcrcxor<7:0> bit 7 bit 0 legend: r = readable bit w = writable bit p = programmable bit r = reserved bit u = unimplemented bit -n = bit value at por: (?0?, ?1?, x = unknown) bit 31-16 reserved: write ? 0 ?; ignore read bit 15-0 dcrcxor<15:0>: crc xor register bits 1 = enable the xor input to the shift register 0 = disable the xor input to the shift register; data is shifted directly in from the previous stage in the register note 1: the lsb of the dcrcxor register will be always set.
? 2008 microchip technology inc. preliminary ds61143e-page 213 pic32mx3xx/4xx register 10-7: dchxcon: dma channel x control register r-x r-x r-x r-x r-x r-x r-x r-x ? ? ? ? ? ? ? ? bit 31 bit 24 r-x r-x r-x r-x r-x r-x r-x r-x ? ? ? ? ? ? ? ? bit 23 bit 16 r-x r-x r-x r-x r-x r-x r-x r/w-0 ? ? ? ? ? ? ? chchns bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r-x r-0 r/w-0 r/w-0 chen chaed chchn chaen ? chedet chpri<1:0> bit 7 bit 0 legend: r = readable bit w = writable bit p = programmable bit r = reserved bit u = unimplemented bit -n = bit value at por: (?0?, ?1?, x = unknown) bit 31-9 reserved: write ? 0 ?; ignore read bit 8 chchns: chain channel selection bit 1 = chain to channel lower in natural priority (ch1 will be enabled by ch2 transfer complete) 0 = chain to channel higher in natural priority (ch1 will be enabled by ch0 transfer complete) note: the chain selection bit takes effect when chaining is enabled, i.e., chchn = 1 . bit 7 chen: channel enable bit 1 = channel is enabled 0 = channel is disabled bit 6 chaed: channel allow events if disabled bit 1 = channel start/abort events will be registered, even if the channel is disabled 0 = channel start/abort events will be ignored if the channel is disabled bit 5 chchn: channel chain enable bit 1 = allow channel to be chained to channel higher in natural priority 0 = do not chain to channel higher in natural priority bit 4 chaen: channel automatic enable bit 1 = channel is continuously enabled, and not automatically disabled after a block transfer is complete 0 = channel is disabled on block transfer complete bit 3 reserved: write ? 0 ?; ignore read bit 2 chedet: channel event detected bit 1 = an event has been detected 0 = no events have been detected bit 1-0 chpri<1:0>: channel priority bits 11 = channel has priority 3 (highest) 10 = channel has priority 2 01 = channel has priority 1 00 = channel has priority 0
pic32mx3xx/4xx ds61143e-page 214 preliminary ? 2008 microchip technology inc. register 10-8: dchxecon: dma channel x event control register r-x r-x r-x r-x r-x r-x r-x r-x ? ? ? ? ? ? ? ? bit 31 bit 24 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 chairq<7:0> bit 23 bit 16 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 chsirq<7:0> bit 15 bit 8 s-0 s-0 r/w-0 r/w-0 r/w-0 r-x r-x r-x cforce cabort paten sirqen airqen ? ? ? bit 7 bit 0 legend: r = readable bit w = writable bit p = programmable bit r = reserved bit u = unimplemented bit -n = bit value at por: (?0?, ?1?, x = unknown) bit 31-24 reserved: write ? 0 ?; ignore read bit 23-16 chairq<7:0>: irq that will abort channel transfer bits 11111111 = interrupt 255 will abort any transfers in progress and set chaif flag ? ? ? 00000001 = interrupt 1 will abort any transfers in progress and set chaif flag 00000000 = interrupt 0 will abort any transfers in progress and set chaif flag bit 15-8 chsirq<7:0>: irq that will start channel transfer bits 11111111 = interrupt 255 will initiate a dma transfer ? ? ? 00000001 = interrupt 1 will initiate a dma transfer 00000000 = interrupt 0 will initiate a dma transfer bit 7 cforce: dma forced transfer bit 1 = a dma transfer is forced to begin when this bit is written to a ? 1 ? 0 = this bit always reads ? 0 ? bit 6 cabort: dma abort transfer bit 1 = a dma transfer is aborted when this bit is written to a ? 1 ? 0 = this bit always reads ? 0 ? bit 5 paten: channel pattern match abort enable bit 1 = abort transfer and clear chen on pattern match 0 = pattern match is disabled bit 4 sirqen: channel start irq enable bit 1 = start channel cell transfer if an interrupt matching chsirq occurs 0 = interrupt number chsirq is ignored and does not start a transfer
? 2008 microchip technology inc. preliminary ds61143e-page 215 pic32mx3xx/4xx bit 3 airqen: channel abort irq enable bit 1 = channel transfer is aborted if an interrupt matching chairq occurs 0 = interrupt number chairq is ignored and does not terminate a transfer bit 2-0 reserved: write ? 0 ?; ignore read register 10-8: dchxecon: dma channel x event control register (continued)
pic32mx3xx/4xx ds61143e-page 216 preliminary ? 2008 microchip technology inc. register 10-9: dchxint: dma channe l x interrupt control register r-x r-x r-x r-x r-x r-x r-x r-x ? ? ? ? ? ? ? ? bit 31 bit 24 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 chsdie chshie chddie chdhie chb cie chccie chtaie cherie bit 23 bit 16 r-x r-x r-x r-x r-x r-x r-x r-x ? ? ? ? ? ? ? ? bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 chsdif chshif chddif chdhif chbcif chccif chtaif cherif bit 7 bit 0 legend: r = readable bit w = writable bit p = programmable bit r = reserved bit u = unimplemented bit -n = bit value at por: (?0?, ?1?, x = unknown) bit 31-24 reserved: write ? 0 ?; ignore read bit 23 chsdie: channel source done interrupt enable bit 1 = interrupt is enabled 0 = interrupt is disabled bit 22 chshie: channel source half empty interrupt enable bit 1 = interrupt is enabled 0 = interrupt is disabled bit 21 chddie: channel destination done interrupt enable bit 1 = interrupt is enabled 0 = interrupt is disabled bit 20 chdhie: channel destination half full interrupt enable bit 1 = interrupt is enabled 0 = interrupt is disabled bit 19 chbcie: channel block transfer complete interrupt enable bit 1 = interrupt is enabled 0 = interrupt is disabled bit 18 chccie: channel cell transfer complete interrupt enable bit 1 = interrupt is enabled 0 = interrupt is disabled bit 17 chtaie: channel transfer abort interrupt enable bit 1 = interrupt is enabled 0 = interrupt is disabled bit 16 cherie: channel address error interrupt enable bit 1 = interrupt is enabled 0 = interrupt is disabled bit 15-8 reserved: write ? 0 ?; ignore read
? 2008 microchip technology inc. preliminary ds61143e-page 217 pic32mx3xx/4xx bit 7 chsdif: channel source done interrupt flag bit 1 = channel source pointer has reached end of source (chsptr == chssiz) 0 = no interrupt is pending bit 6 chshif: channel source half empty interrupt flag bit 1 = channel source pointer has reached midpoint of source (chsptr == chssiz/2) 0 = no interrupt is pending bit 5 chddif: channel destination done interrupt flag bit 1 = channel destination pointer has reached end of destination (chdptr == chdsiz) 0 = no interrupt is pending bit 4 chdhif: channel destination half full interrupt flag bit 1 = channel destination pointer has reached midpoint of destination (chdptr == chdsiz/2) 0 = no interrupt is pending bit 3 chbcif: channel block transfer complete interrupt flag bit 1 = a block transfer has been completed (the larg er of chssiz/chdsiz bytes has been transferred) or a pattern match event occurs 0 = no interrupt is pending bit 2 chccif: channel cell transfer complete interrupt flag bit 1 = a cell transfer has been completed (chcsiz bytes have been transferred) 0 = no interrupt is pending bit 1 chtaif: channel transfer abort interrupt flag bit 1 = an interrupt matching chairq has been detected and the dma transfer has been aborted 0 = no interrupt is pending bit 0 cherif: channel address error interrupt flag bit 1 = a channel address error has been detected either the source or the destination address is invalid. 0 = no interrupt is pending register 10-9: dchxint: dma channel x in terrupt control register (continued)
pic32mx3xx/4xx ds61143e-page 218 preliminary ? 2008 microchip technology inc. register 10-10: dchxssa: dma channel x source start address register r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x chssa<31:24> bit 31 bit 24 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x chssa<23:16> bit 23 bit 16 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x chssa<15:8> bit 15 bit 8 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x chssa<7:0> bit 7 bit 0 legend: r = readable bit w = writable bit p = programmable bit r = reserved bit u = unimplemented bit -n = bit value at por: (?0?, ?1?, x = unknown) bit 31-0 chssa<31:0> channel source start address bits channel source start address. note: this must be the physical address of the source.
? 2008 microchip technology inc. preliminary ds61143e-page 219 pic32mx3xx/4xx register 10-11: dchxdsa: dma channel x destination start address register r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x chdsa<31:24> bit 31 bit 24 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x chdsa<23:16> bit 23 bit 16 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x chdsa<15:8> bit 15 bit 8 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x chdsa<7:0> bit 7 bit 0 legend: r = readable bit w = writable bit p = programmable bit r = reserved bit u = unimplemented bit -n = bit value at por: (?0?, ?1?, x = unknown) bit 31-0 chdsa<31:0>: channel destination start address bits channel destination start address. note: this must be the physical address of the destination.
pic32mx3xx/4xx ds61143e-page 220 preliminary ? 2008 microchip technology inc. register 10-12: dchxssiz: dma channel x source size register r-x r-x r-x r-x r-x r-x r-x r-x ? ? ? ? ? ? ? ? bit 31 bit 24 r-x r-x r-x r-x r-x r-x r-x r-x ? ? ? ? ? ? ? ? bit 23 bit 16 r-x r-x r-x r-x r-x r-x r-x r-x ? ? ? ? ? ? ? ? bit 15 bit 8 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x chssiz<7:0> bit 7 bit 0 legend: r = readable bit w = writable bit p = programmable bit r = reserved bit u = unimplemented bit -n = bit value at por: (?0?, ?1?, x = unknown) bit 31-8 reserved: write ? 0 ?; ignore read bit 7-0 chssiz<7:0>: channel source size bits 255 = 255-byte source size ? ? ? 2 = 2-byte source size 1 = 1-byte source size 0 = 256-byte source size
? 2008 microchip technology inc. preliminary ds61143e-page 221 pic32mx3xx/4xx register 10-13: dchxdsiz: dma channe l x destination size register r-x r-x r-x r-x r-x r-x r-x r-x ? ? ? ? ? ? ? ? bit 31 bit 24 r-x r-x r-x r-x r-x r-x r-x r-x ? ? ? ? ? ? ? ? bit 23 bit 16 r-x r-x r-x r-x r-x r-x r-x r-x ? ? ? ? ? ? ? ? bit 15 bit 8 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x chdsiz<7:0> bit 7 bit 0 legend: r = readable bit w = writable bit p = programmable bit r = reserved bit u = unimplemented bit -n = bit value at por: (?0?, ?1?, x = unknown) bit 31-8 reserved: write ? 0 ?; ignore read bit 7-0 chdsiz<7:0>: channel destination size bits 255 = 255-byte destination size ? ? ? 2 = 2-byte destination size 1 = 1-byte destination size 0 = 256-byte destination size
pic32mx3xx/4xx ds61143e-page 222 preliminary ? 2008 microchip technology inc. register 10-14: dchxsptr: dma channel x source pointer register r-x r-x r-x r-x r-x r-x r-x r-x ? ? ? ? ? ? ? ? bit 31 bit 24 r-x r-x r-x r-x r-x r-x r-x r-x ? ? ? ? ? ? ? ? bit 23 bit 16 r-x r-x r-x r-x r-x r-x r-x r-x ? ? ? ? ? ? ? ? bit 15 bit 8 r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 chsptr<7:0> bit 7 bit 0 legend: r = readable bit w = writable bit p = programmable bit r = reserved bit u = unimplemented bit -n = bit value at por: (?0?, ?1?, x = unknown) bit 31-8 reserved: write ? 0 ?; ignore read bit 7-0 chsptr<7:0>: channel source pointer bits 255 = points to 255th byte of the source ? ? ? 1 = points to 1st byte of the source 0 = points to 0th byte of the source note: this is reset on pattern detect, when in pattern detect mode.
? 2008 microchip technology inc. preliminary ds61143e-page 223 pic32mx3xx/4xx register 10-15: dchxdptr: channel x destination pointer register r-x r-x r-x r-x r-x r-x r-x r-x ? ? ? ? ? ? ? ? bit 31 bit 24 r-x r-x r-x r-x r-x r-x r-x r-x ? ? ? ? ? ? ? ? bit 23 bit 16 r-x r-x r-x r-x r-x r-x r-x r-x ? ? ? ? ? ? ? ? bit 15 bit 8 r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 chdptr<7:0> bit 7 bit 0 legend: r = readable bit w = writable bit p = programmable bit r = reserved bit u = unimplemented bit -n = bit value at por: (?0?, ?1?, x = unknown) bit 31-8 reserved: write ? 0 ?; ignore read bit 7-0 chdptr<7:0>: channel destination pointer bits 255 = points to 255th byte of the destination ? ? ? 1 = points to 1st byte of the destination 0 = points to 0th byte of the destination
pic32mx3xx/4xx ds61143e-page 224 preliminary ? 2008 microchip technology inc. register 10-16: dchxcsiz: dma channel x cell-size register r-x r-x r-x r-x r-x r-x r-x r-x ? ? ? ? ? ? ? ? bit 31 bit 24 r-x r-x r-x r-x r-x r-x r-x r-x ? ? ? ? ? ? ? ? bit 23 bit 16 r-x r-x r-x r-x r-x r-x r-x r-x ? ? ? ? ? ? ? ? bit 15 bit 8 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x chcsiz<7:0> bit 7 bit 0 legend: r = readable bit w = writable bit p = programmable bit r = reserved bit u = unimplemented bit -n = bit value at por: (?0?, ?1?, x = unknown) bit 31-8 reserved: write ? 0 ?; ignore read bit 7-0 chcsiz<7:0>: channel cell size bits 255 = 255 bytes transferred on an event ? ? ? 2 = 2 bytes transferred on an event 1 = 1 byte transferred on an event 0 = 256 bytes transferred on an event
? 2008 microchip technology inc. preliminary ds61143e-page 225 pic32mx3xx/4xx register 10-17: dchxcptr: dma channel x cell pointer register r-x r-x r-x r-x r-x r-x r-x r-x ? ? ? ? ? ? ? ? bit 31 bit 24 r-x r-x r-x r-x r-x r-x r-x r-x ? ? ? ? ? ? ? ? bit 23 bit 16 r-x r-x r-x r-x r-x r-x r-x r-x ? ? ? ? ? ? ? ? bit 15 bit 8 r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 chcptr<7:0> bit 7 bit 0 legend: r = readable bit w = writable bit p = programmable bit r = reserved bit u = unimplemented bit -n = bit value at por: (?0?, ?1?, x = unknown) bit 31-8 reserved: write ? 0 ?; ignore read bit 7-0 chcptr<7:0>: channel cell progress pointer bits 255 = 255 bytes have been transferred since the last event ? ? ? 1 = 1 bytes have been transferred since the last event 0 = 0 bytes have been transferred since the last event note: this is reset on pattern detect, when in pattern detect mode.
pic32mx3xx/4xx ds61143e-page 226 preliminary ? 2008 microchip technology inc. register 10-18: dchxdat: dma channel x pattern data register r-x r-x r-x r-x r-x r-x r-x r-x ? ? ? ? ? ? ? ? bit 31 bit 24 r-x r-x r-x r-x r-x r-x r-x r-x ? ? ? ? ? ? ? ? bit 23 bit 16 r-x r-x r-x r-x r-x r-x r-x r-x ? ? ? ? ? ? ? ? bit 15 bit 8 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x chpdat<7:0> bit 7 bit 0 legend: r = readable bit w = writable bit p = programmable bit r = reserved bit u = unimplemented bit -n = bit value at por: (?0?, ?1?, x = unknown) bit 31-8 reserved: write ? 0 ?; ignore read bit 7-0 chpdat<7:0>: channel data register bits pattern terminate mode : data to be matched must be stored in this register to allow terminate on match. all other modes : unused.
? 2008 microchip technology inc. preliminary ds61143e-page 227 pic32mx3xx/4xx 10.2 dma controller operation a dma channel will transfer data from a source to a destination without cpu intervention. dma controller configuration resources: ? the dma controller and the corresponding dma channel have to be enabled using the on (dmacon<15>) and the chen (dchxcon<7>) bits. ? the source and destination of the transfer are programmable using the dchxssa and dchxdsa registers respectively. ? the source and destination are further indepen- dently configurable using the dchxssiz and dchxdsiz registers. ? a dma transfer can be initiated in one of two ways: - software can initiate a transfer by setting the channel cforce (dchxecon<7>) bit. - an interrupt event occurs that matches the chsirq (dchxecon<15:8>) interrupt and sirqen = 1 (dchxecon<4>). the user can select any interrupt on the device to start a dma transfer. ? at each event requiring a dma transfer, a num- ber of bytes specified by the cell size (dchxcsiz) will be transferred (one or more transactions will occur). ? the channel keeps track of the number of bytes transferred from the source to destination, using source and destination pointers (dchxsptr and dchxdptr). ? the source and destination pointers are read- only and are updated after every transaction. ? interrupts are generated when the source or destination pointer is half of the source or desti- nation size (dchxssiz/2 or dchxdsiz/2), or when the source or destination counter equals the size of the source or destination. these interrupts are chshif, chdhif and chsdif, chddif, respectively. ? the source and destination pointers are reset: - on any device reset. - when the dma is turned off (on bit (dmacon<15>) is ? 0 ?). - a block transfer completes (regardless of the state of chaen (dchxcon<4>)). - a pattern match terminates a transfer (regardless of the state of auto-enable chaen (dchxcon<4>)). - cabort (dchxecon<6>) flag is written. - if the channel source address (dchxssa) is updated, the source pointer (dchxsptr) will be reset. - similarly, updates to the destination address (dchxdsa) will cause the destination pointer (dchxdptr) to be reset. ? normally, the dma channel remains enabled until the dma channel has completed a block transfer unless the auto-enable feature is turned on (i.e., chaen = 1 ). ? when the channel is disabled, further transfers will be prohibited until the channel is re-enabled (chen is set to ? 1 ?). ? a dma transfer request will be stopped/aborted by: - writing the cabort bit (dchxecon<6>). - pattern match occurs if pattern match is enabled paten = 1 (dchxecon<5>), pro- vided that channel chaen is not set. - interrupt event occurs on the device that matches the chairq (dchxecon<23:16>) interrupt if enabled by airqen (dchxecon<3>). - an address error is detected. - a block transfer completes provided that channel auto-enable mode (chaen) is not set. ? when a channel abort interrupt occurs, the channel abort interrupt flag, chtaif, (dchxint<1>) is set. this allows the user to detect and recover from an aborted dma transfer. when a transfer is aborted, any transaction currently underway will be completed. note: bmx arbitration mode 2 (rotating priority) is recommended when a system may experience heavy bus load. note: always wait for the channels to complete the current transactions (or abort first and make sure the transfers were successfully aborted) before switching the dma controller off. note: if the dma channel is suspended in the mid- dle of a transfer (if chen (dchxcon)<7> = 0 ) or if the dma controller is suspended in the middle of a transfer (if suspend (dmacon)<12> = 1 ) and a cabort is issued, the source, destination and cell pointers are not reset.
pic32mx3xx/4xx ds61143e-page 228 preliminary ? 2008 microchip technology inc. 10.2.1 dma controller terminology event: any system event that can initiate or abort a dma transfer. transaction: a single-word transfer (up to 4 bytes), comprised of read and write operations. cell transfer: the number of bytes transferred when a dma channel has a transfer initiated before waiting for another event (given by the dchcsiz register). a cell transfer comprises one or more transactions. block transfer: defined as the number of bytes trans- ferred when a channel is enabled. the number of bytes is the larger of either dchxssiz or dchxdsiz. a block transfer comprises one or more cell transfers. 10.3 basic transfer mode basic transfer mode transfer features: ? the transfer size is limited to a maximum of 256 bytes transferred per channel. ? the source and destination pointers wrap around based on the selected source and destination size. ? a block transfer is complete when the block size bytes have been transferred. the block size is the larger of source and destination sizes: - blocksize = max (dchxssiz, dchxdsiz). ? a dma event will transfer cell size (dchxcsiz) bytes from source to destination. however, if dchxcsiz is greater than the block size, then just block size bytes will be transferred. 10.3.1 basic transfer mode configuration microchip recommends taking the following steps to configure a dma transfer: ? disable the dma channel interrupts in the int controller. ? clear any existing channel interrupt flags in the int controller. ? enable the dma controller (if not already enabled) in dmacon register. ? set channel control register: priority, auto-enable mode, etc., in dchxcon. (don?t enable the channel yet!) ? set the channel event control: clear/set the events starting and aborting the transfer. if needed, also set the pattern match enable in dchxecon. ? if using a pattern match, set the pattern in the dchxdat register. ? set the transfer source and destination physical addresses (dchxssa and dchxdsa registers). ? set the source and destination sizes (dchxssiz, dchxdsiz registers). ? set the cell transfer size (dchxcsiz). ? clear any existing event flag in the dchxint register. ? if using interrupts: - set the conditions that will generate an inter- rupt in the dchxint register (at least error interrupt enable and abort interrupt enable, usually block complete interrupt). - set the dma channel interrupt priority and subpriority in the int controller. - enable the dma channel interrupt in the int controller. ? enable the selected dma channel with chen (dchxcon<7>). ? if not using system events to start the dma transfer use cforce (dchxecon<7>) to start transfer. ? until the dma transfer is complete you can do some other processing. ? if transfer complete interrupts (cell complete, block complete, etc.) are enabled, a notification will be presented in the isr that the dma transfer completed. ? otherwise, the dma channel can be polled to see if the transfer is completed using, for example, chbcif (dchxint<3>). refer to example 10-1.
? 2008 microchip technology inc. preliminary ds61143e-page 229 pic32mx3xx/4xx example 10-1: config uring the dma for basic transfer mode operation /* the following code example illustrates the dma channel 0 configuration for a basic transfer. */ iec1clr=0x00010000; // disable dma channel 0 interrupts ifs1clr=0x00010000; // clear existing dma channel 0 interrupt flag dmaconset=0x00008000; // enable the dma controller dch0con=0x3; // channel off, pri 3, no chaining ch0econ=0; // no start or stop irq?s, no pattern match // program the transfer dch0ssa=0x1d010000; // transfer source physical address dch0dsa=0x1d020000; // transfer destination physical address dch0ssiz=0; // source size 256 bytes dch0dsiz=0; // destination size 256 bytes dch0csiz=0; // 256 bytes transferred per event dch0intclr=0x00ff00ff; // clear existing events, disable all interrupts dch0conset=0x80; // turn channel on // initiate a transfer dch0econset=0x00000080; // set cforce to 1 // do something else // poll to see that the transfer was done while(true) { register int pollcnt; // use a poll counter. // polling continuously the dma controller in a tight // loop would affect the performance of the dma transfer int dmaflags=dch0int; if( (dmaflags&0xb) { // one of cherif (dchxint<0>), chtaif (dchxint<1>) // or chbcif (dchxint<3>) flags set break; // transfer completed } pollcnt=100; // use an adjusted value here while(pollcnt--); // wait before reading again the dma controller } // check the transfer completion result
pic32mx3xx/4xx ds61143e-page 230 preliminary ? 2008 microchip technology inc. 10.4 pattern match termination the pattern match mode is enabled by setting the paten bit (dchxecon<5>). this feature is useful in applications where a variable data size is required and eases the setup of the dma channel. a good usage is for transferring ascii com- mand strings from an uart, ended. this is also useful for implementing string copy routines with dma support. pattern match mode features: ? allows the user to end a transfer if a byte of data written during a transaction matches a specific pattern. ? a pattern match is treated the same way as a block transfer complete, where the chbcif (dchxint<3>) bit is set and the chen (dchxcon<7>) bit is cleared provided auto-enable chaen = 0 (dchxcon<4>). ? the pattern is stored in the dchxdat register. ? if any byte in the source matches dchxdat, a pattern match is detected. 10.4.1 pattern match mode configuration the pattern match mode is an option for use when performing dma transfers in basic dma configuration. therefore, the steps needed in pattern match mode are identical to those used in basic dma configuration. an extra step is needed to store the desired pattern in dchxdat register. the following steps are recommended to be taken to configure a dma transfer in pattern match mode: ? disable the dma channel interrupts in the int controller. ? clear any existing channel interrupt flags in the int controller. ? enable the dma controller (if not already enabled) in dmacon register. ? set channel control register: priority, auto-enable mode, etc., in dchxcon. don?t enable the channel yet. ? set the channel event control: clear/set the events starting and aborting the transfer. set the pattern match enable paten in dchxecon. ? set the pattern in the dchxdat register. ? set the transfer source and destination physical addresses (dchxssa and dchxdsa registers). ? set the source and destination sizes (dchxssiz, dchxdsiz registers). ? set the cell transfer size (dchxcsiz). ? clear any existing event flag in dchxint register. ? if using interrupts: - set the conditions that will generate an inter- rupt in the dchxint register (at least error interrupt enable and abort interrupt enable, usually block complete interrupt). - set the dma channel interrupt priority and subpriority in the int controller. - enable the dma channel interrupt in the int controller. ? enable the selected dma channel with chen (dchxcon<7>). ? if not using system events to start the dma transfer use cforce (dchxecon<7>) to start transfer. ? until the dma transfer is complete, you can do some other processing. ? if you enabled transfer complete interrupts (cell complete, block complete, etc) you?ll be notified in the isr that the dma transfer completed. ? otherwise, you can poll the dma channel to see if the transfer is completed using, for example, chbcif (dchxint<3>). refer to example 10-2.
? 2008 microchip technology inc. preliminary ds61143e-page 231 pic32mx3xx/4xx example 10-2: configuring the dma for pattern match operation /* the following code example illustrates the dma channel 0 configuration for data transfer with pattern match enabled. transfer from the uart1 a ended string, at most 256 characters long */ iec1clr=0x00010000; // disable dma channel 0 interrupts ifs1clr=0x00010000; // clear any existing dma channel 0 interrupt flag dmaconset=0x00008000; // enable the dma controller dch0con=0x03; // channel off, priority 3, no chaining dch0econ=(27 <<8)| 0x30; // start irq is uart1 rx, pattern match enabled dch0dat=?\r?; // pattern value, carriage return // program the transfer dch0ssa=virttophys(&u1rxreg); // transfer source physical address dch0dsa=0x1d020000; // transfer destination physical address dch0ssiz=1; // source size is 1 byte dch0dsiz=0; // dst size at most 256 bytes dch0csiz=1; // one byte per uart transfer request dch0intclr=0x00ff00ff; // clear existing events, disable all interrupts dch0intset=0x00090000; // enable block complete and error interrupts ipc9clr=0x0000001f; // clear the dma channel 0 priority and subpriority ipc9set=0x00000016; // set ipl 5, subpriority 2 iec1set=0x00010000; // enable dma channel 0 interrupt dch0conset=0x80; // turn channel on // wait for an uart rx interrupt to initiate a transfer // do something else // will get an interrupt when the transfer is done // or when an address error occurred
pic32mx3xx/4xx ds61143e-page 232 preliminary ? 2008 microchip technology inc. 10.5 channel chaining mode the chaining mode is enabled by setting the chaining enable it chcen bit (dchxcon<5>) and chaining direction bit chchns (dchxcon<8>). channel chaining is an enhancement to the dma channel operation. a good usage is for transferring data packets from one peripheral to memory and then from memory to another peripheral. this module is also useful for implementing data acquisition in multiple buffers. chaining mode features: ? a channel (slave channel) can be chained to an adjacent channel (master channel). when the master channel completes a block transfer the slave channel will be enabled. ? at this point, any event on the slave channel will initiate a cell transfer. if the channel has an event pending, a cell transfer will begin immediately. ? channels are chained in natural priority order where channel 0 has the highest priority and channel 3 the lowest. a specific channel can be enabled by an adjacent channel, either higher, or lower, in natural order, by configuring the chchns (dchxcon<8>) bit. chaining must be enabled, chchn (dchxcon<5>) = 1 . ? an important feature of the dma controller is the ability to allow events while the channel is dis- abled using the chaed (dchxcon<6>) bit. this bit is particularly useful in chained mode where the slave channel needs to be ready to start a transfer as soon as the channel is enabled by the master channel. 10.5.1 chaining mode configuration the chaining mode is an option for use when perform- ing dma transfers. therefore, the steps needed in chaining mode are identical to those used in basic dma configuration, with the following differences (refer to section 10.3.1 ?basic transfer mode con- figuration? ): ? two different channels have to be configured and the slave channel has to have chaining enable (chchn) and chaining direction (chchns) set. refer to example 10-3. 10.6 channel auto-enable mode the auto-enable mode is enabled by setting the chaen bit (dchxcon<4>). channel auto-enable function is an enhancement to the dma channel operation. the channel auto-enable can be used to keep a chan- nel active, even if a block transfer completes or a pat- tern match occurs. this prevents the user from having to re-enable the channel each time a block transfer completes. this mode is useful for applications that do repeated pattern matching. 10.6.1 auto-enable mode configuration the auto-enable mode is an extra option for use when performing dma transfers. therefore, the steps needed in auto-enable mode are identical to those used in basic dma configuration, with the following dif- ferences (refer to section 10.3.1 ?basic transfer mode configuration? ): ? the chaen bit has to be set before enabling the channel (setting the chen bit (dchxcon<7>)). ? the channel will behave as normal except that normal termination of a transfer will not result in the channel being disabled. ? normal block transfer completion is defined as: - block transfer complete - pattern match detect ? as before, the channel pointers will be reset.
? 2008 microchip technology inc. preliminary ds61143e-page 233 pic32mx3xx/4xx example 10-3: configuri ng the dma for chaining mode operation /* the following code example illustrates the dma channel 0 configuration for data transfer with pattern match enabled. dma channel 0 transfer from the uart1 to a ram buffer while dma channel 1 transfers data from the ram buffer to uart2. transferred strings are at most 256 characters long. transfer on uart2 will start as soon as the uart1 transfer is completed. */ unsigned char mybuff<256>; // transfer buffer iec1clr=0x00010000; // disable dma channel 0 interrupts ifs1clr=0x00010000; // clear any existing dma channel 0 interrupt flag dmaconset=0x00008000; // enable the dma controller dch0con=0x3; // channel 0 off, priority 3, no chaining dch1con=0x62; // channel 1 off, priority 2 // chain to higher priority // (ch 0), enable events detection while disabled dch0econ=(27 <<8)| 0x30; // start irq is uart1 rx, pattern enabled dch1econ=(42 <<8)| 0x30; // start irq is uart1 tx, pattern enabled dch0dat=dch1dat=?\r?; // pattern value, carriage return // program channel 0 transfer dch0ssa=virttophys(&u1rxreg); // transfer source physical address dch0dsa=virttophys(mybuff); // transfer destination physical address dch0ssiz=1; // source size is 1 byte dch0dsiz=0; // dst size at most 256 bytes dch0csiz=1; // one byte per uart transfer request // program channel 1 transfer dch1ssa=virttophys(mybuff); // transfer source physical address dch1dsa=virttophys(&u2txreg); // transfer destination physical address dch1ssiz=0; // source size at most 256 bytes dch1dsiz=1; // dst size is 1 byte dch1csiz=1; // one byte per uart transfer request dch0intclr=0x00ff00ff; // dma0: clear events, disable interrupts dch1intclr=0x00ff00ff; // dma1: clear events, disable interrupts dch1intset=0x00090000; // dma1: enable block complete and error interrupts ipc9clr=0x00001f1f; // clear the dma channels 0 and 1 priority and // subpriority ipc9set=0x00000b16; // set ipl 5, subpriority 2 for dma channel 0 // set ipl 2, subpriority 3 for dma channel 1 iec1set=0x00020000; // enable dma channel 1 interrupt dch0conset=0x80; // turn channel on // do something else // the uart1 rx interrupts will initiate the dma channel 0 transfer // once this transfer is complete, the dma channel 1 will start // upon dma channel 1 transfer completion will get an interrupt while(!intch1occurred); // poll dma channel 1 interrupt
pic32mx3xx/4xx ds61143e-page 234 preliminary ? 2008 microchip technology inc. 10.7 crc module operation the dma module has one integrated crc generation module shared by all channels. the crc module is a highly configurable, 16-bit crc generator. the crc module can be assigned to any available dma chan- nel by setting the crcch bits (dcrccon<1:0>) appropriately. the crc is enabled by setting the crcen bit (dcrccon<7>). the crc generator will take 1 system clock to process each byte of data read from the source. this implies that if 32 bits of data are read from the source, the crc generation will take 4 system clocks to process the data. the crc module modifies the behavior of the dma channel associated with the crc module. the two operating modes for a dma channel associated with the crc module are: ? background mode: crc is calculated in the background, with normal dma behavior maintained. ? append mode: data read from the source is not written to the destination, but the crc data is accumulated in the crc data register. the accu- mulated crc is written to the destination address when a block transfer completes. crc configurable resources: ? the terms of the polynomial can be programmed using the dcrcxor<15:0> bits. considering the crc polynomial: x 16 + x 12 + x 5 + 1, 17 bits are needed to define this polynomial. however, the value to be written to the dcrcxor register will be 0b0001 0000 0010 0000 , i.e., 0x1020. ? the length of the polynomial generator can be programmed using the plen (dcrccon<11:8>) bits. for the above polynomial, the size will be 16. the plen will be programmed with length -1, i.e., 0x0f. ? the crc module can be assigned to any avail- able dma channel by setting the crcch bits (dcrccon<2:0>) appropriately. ? the crc is enabled by setting the crcen bit (dcrccon<7>). ? the crc generator can be seeded by writing to the dcrcdata register before enabling the channel that will use the crc module. ? the crc can be read as it progresses by reading the dcrcdata register at any time during the crc generation. ? data order: as data is read from the source regis- ter, the data is fed into the crc generator msb first. 10.8 crc background mode the crc background mode is enabled by clearing crcapp (dcrccon<6>). in this mode, the behavior of the dma channel is maintained with data read from the channel source being passed to the crc module and then written back to the destination. in the background mode, the calculated crc is left in the dcrcdata register at the end of the block transfer. this mode can be used to calculate a crc as data is moved from source to destination. a good example of where this can be used is to calculate a crc as data is transmitted to or received from the uart module. when the data transfer is complete the user can read the calculated crc and either append it to the transmitted data or verify the received crc data. 10.8.1 crc background mode configuration microchip recommends taking the following steps to configure a crc calculation in background mode: ? seed the crc generator by writing the initial seed to the dcrcdata register. ? set the polynomial generator by writing to the dcrcxor register. ? set the polynomial generator length by writing the plen (dcrccon<11:8>). ? attach the crc calculation to the desired dma channel performing the transfer by writing the crcch (dcrccon<2:0>). ? use the background mode by clearing the crcapp (dcrccon<6>) bit. ? enable the crc calculation by setting the crcen (dcrccon<7>). ? once the dma transfer begins, the crc calculation will begin as well. ? once the dma transfer ends, the crc result will be available by reading the dcrcdata register. refer to example 10-4. note: the lsb and msb do not have to be specified, they are always set. the actual value used for the polynomial generator will be 0x11021. note: the configuration steps specific for the crc configuration are shown. the dma transfer configuration is the same as previously explained (see section 10.2 ?dma controller operation? ).
? 2008 microchip technology inc. preliminary ds61143e-page 235 pic32mx3xx/4xx example 10-4: crc backgro und mode operation /* the following code example illustrates a dma calculation using the crc background mode. data is transferred from a 256 bytes flash buffer to a ram buffer and the crc is calculated while the transfer takes place. */ unsigned int blockcrc; // crc of the flash block iec1clr=0x00010000; // disable dma channel 0 interrupts ifs1clr=0x00010000; // clear any existing dma channel 0 interrupt flag dmaconset=0x00008000; // enable the dma controller dcrcdata=0xffff; // seed the crc generator dcrcxor=0x1021; // use the standard ccitt crc 16 polynomial: x^16+x^12+x^5+1 dcrccon=0x0f80; // crc enabled, polynomial length 16, background mode // crc attached to the dma channel 0. dch0con=0x03; // channel off, priority 3, no chaining dch0econ=0; // no start irqs, no match enabled // program channel transfer dch0ssa=virttophys(flashbuff); // transfer source physical address dch0dsa=virttophys(rambuff); // transfer destination physical address dch0ssiz=0; // source size dch0dsiz=0; // dst size dch0csiz=0; // 256 bytes per transfer dch0intclr=0x00ff00ff; // dma0: clear events, disable interrupts dch0conset=0x80; // channel 0 on // initiate a transfer dch0econset=0x00000080; // set cforce to 1 // do something else while the transfer takes place // poll to see that the transfer was done bool error=false; while(true) { register int pollcnt; // don?t poll in a tight loop int dmaflags=dch0int; if( (dmaflags& 0x3) { // cherif (dchxint<0>) or chtaif (dchxint<1> set error=true; // error or aborted... break; } else if (dmaflags&0x8) { // chbcif (dchxint<3>) set break; // transfer completed normally } pollcnt=100; // use an adjusted value here while(pollcnt--); // wait before polling again } if(!error) { blockcrc=dcrdata; // read the crc of the transferred flash block } else { // process error }
pic32mx3xx/4xx ds61143e-page 236 preliminary ? 2008 microchip technology inc. 10.9 crc append mode the crc append mode is enabled by setting crcapp (dcrccon<6>). in this mode, the behavior of the dma channel is changed. data read from the source will be fed into the crc generation module. no data is written to the destina- tion address in crc append mode until a block trans- fer completes or a pattern match occurs. on completion, the crc value will be written to the address given by the destination register (dchxdsa). this mode can be used for the crc calculation of a memory buffer, without actually performing a dma transfer to a destination. crc append mode features: ? only the source is considered when deciding if a block transfer is complete. ? the destination address (dchxdsa) is only used as the location to write the generated crc to. ? the destination size (dchxdsiz) can have a maximum size of 4. - if dchxdsiz is greater than 4, only 4 bytes are written at the end of the transfer. - if dchxdsiz is less than 4, only dchxdsiz bytes of the crc are written to the destination address. - the high bytes (bits 31:16) are written as 0 ?s if more than 16 bits of the crc are written. - plen (crccon<11:8>) has no effect on the number of crc bits that will be written to the destination register. ? no crc written back on an abort irq, user abort, bus error, etc. 10.9.1 crc append mode configuration microchip recommends taking the following steps to configure a crc calculation in background mode: ? seed the crc generator by writing the initial seed to the dcrcdata register. ? set the polynomial generator by writing to the dcrcxor register. ? set the polynomial generator length by writing the plen (dcrccon<11:8>). ? attach the crc calculation to the desired dma channel performing the transfer by writing the crcch (dcrccon<2:0>). ? use the append mode by setting the crcapp (dcrccon<6>) bit. ? enable the crc calculation by setting the crcen (dcrccon<7>). ? program the dma transfer destination with the physical address of a variable where the crc is to be stored. ? once the dma transfer begins, the crc calculation will begin as well. ? once the dma transfer ends, the crc result will be deposited at the programmed dma destination address. refer to example 10-5. note: the configuration steps specific for the crc configuration are shown. the dma transfer configuration is the same as previously explained (see section 10.2 ?dma controller operation? ).
? 2008 microchip technology inc. preliminary ds61143e-page 237 pic32mx3xx/4xx example 10-5: crc append mode operation /* the following code example illustrates a dma calculation using the crc append mode. the crc of a 200 bytes flash buffer is calculated without performing any data transfer. as soon as the crc calculation is completed the crc value of the flash buffer is available in a local variable for further use. */ unsigned int blockcrc; // crc of the flash block iec1clr=0x00010000; // disable dma channel 0 interrupts ifs1clr=0x00010000; // clear any existing dma channel 0 interrupt flag dmaconset=0x00008000; // enable the dma controller dcrcdata=0xffff; // seed the crc generator dcrcxor=0x1021; // use the standard ccitt crc 16 polynomial: x^16+x^12+x^5+1 dcrccon=0x0fc0; // crc enabled, polynomial length 16, append mode // crc attached to the dma channel 0. dch0con=0x03; // channel off, priority 3, no chaining dch0econ=0; // no start irqs, no match enabled // program channel transfer dch0ssa=virttophys(flashbuff); // transfer source physical address dch0dsa=virttophys(&blockcrc); // transfer destination physical address dch0ssiz=200; // source size dch0dsiz=200; // dst size dch0csiz=200; // 200 bytes per transfer dch0intclr=0x00ff00ff; // dma0: clear events, disable interrupts dch1intclr=0x00ff00ff; // dma1: clear events, disable interrupts dch0conset=0x80; // channel 0 on // initiate a transfer dch0econset=0x00000080; // set cforce to 1 // do something else while the crc calculation takes place // poll to see that the transfer was done bool error=false; while(true) { register int pollcnt; // don?t poll in a tight loop int dmaflags=dch0int; if( (dmaflags& 0x3) { // cherif (dchxint<0>) or chtaif (dchxint<1> set error=true; // error or aborted... break; } else if (dmaflags&0x8) { // chbcif (dchxint<3>) set break; // transfer completed normally } pollcnt=100; // use an adjusted value here while(pollcnt--); // wait before polling again } if(error) { // process error } // the block crc is available in the blockcrc variable
pic32mx3xx/4xx ds61143e-page 238 preliminary ? 2008 microchip technology inc. 10.10 dma interrupts the dma device has the ability to generate interrupts reflecting the events that occur during the channel?s data transfer. the different kinds of dma interrupt flags are: ? cherif (dchxint<0>): channel error interrupts, enabled using cherie (dchxint<16>). ? chtaif (dchxint<1>): channel abort interrupts, enabled using chtaie (dchxint<17>). ? chbcif (dchxint<3>): channel block complete interrupts, enabled using chbcie (dchxint<19>). ? chccif (dchxint<2>): channel cell complete interrupts, enabled using chccie (dchxint<18>). ? chsdif (dchxint<7>): channel source pointer reached the end of the source, enabled by chsdie (dchxint<23>). ? chshif (dchxint<6>): channel source pointer reached midpoint of the source, enabled by chshie (dchxint<22>). ? chddif (dchxint<5>): channel destination pointer reached the end of the destination, enabled by chddie (dchxint<21>) ? chdhif (dchxint<4>): channel destination pointer reached midpoint of the destination, enabled by chdhie (dchxint<20>). all the interrupts belonging to a dma channel map to the corresponding channel interrupt vector. the corresponding interrupt flags are: ? dma0if (ifs1<16>) ? dma1if (ifs1<17>) ? dma2if (ifs1<18>) ? dma3if (ifs1<19>) all these interrupt flags must be cleared in software. a dma channel is enabled as a source of interrupts via the respective dma interrupt enable bits: ? dma0ie (iec1<16>) ? dma1ie (iec1<17>) ? dma2ie (iec1<18>) ? dma3ie (iec1<19>) the interrupt priority level bits and interrupt subpriority level bits must be also be configured: ? dma0ip<2:0> (ipc9<4:2>), dma0is<1:0> (ipc9<1:0>). ? dma1ip<2:0> (ipc9<12:10>), dma1is<1:0> (ipc9<9:8>). ? dma2ip<2:0> (ipc9<20:18>), dma2is<1:0> (ipc9<17:16>). ? dma3ip<2:0> (ipc9<28:26>), dma3is<1:0> (ipc9<25:24>). in addition to enabling the dma interrupts, interrupt service routines (isrs) are required for each different interrupt vector used. see example 10-6 and example 10-7. note: it is the user?s responsibility to clear the corresponding interrupt flag bit before returning from an isr.
? 2008 microchip technology inc. preliminary ds61143e-page 239 pic32mx3xx/4xx example 10-6: dma initialization with interrupts example 10-7: dma channel 0 isr /* the following code example illustrates a dma channel 0 interrupt configuration. when the dma channel 0 interrupt is generated, the cpu will jump to the vector assigned to dma0 interrupt. */ iec1clr=0x00010000; // disable dma channel 0 interrupts ifs1clr=0x00010000; // clear any existing dma channel 0 interrupt flag dmaconset=0x00008000; // enable the dma controller dch0con=0x03; // channel off, priority 3, no chaining dch0econ=0; // no start or stop irq?s, no pattern match // program the transfer dch0ssa=0x1d010000; // transfer source physical address dch0dsa=0x1d020000; // transfer destination physical address dch0ssiz=0; // source size 256 bytes dch0dsiz=0; // destination size 256 bytes dch0csiz=0; // 256 bytes transferred pe event dch0intclr=0x00ff00ff; // clear existing events, disable all interrupts dch0intset=0x00090000; // enable block complete and error interrupts ipc9clr=0x0000001f; // clear the dma channel 0 priority and subpriority ipc9set=0x00000016; // set ipl 5, subpriority 2 iec1set=0x00010000; // enable dma channel 0 interrupt dch0conset=0x80; // turn channel on // initiate a transfer dch0econset=0x00000080; // set cforce to 1 // do something else // will get an interrupt when the block transfer is done // or when error occurred /* the following code example demonstrates a simple interrupt service routine for dma channel 0 interrupts. the user?s code at this vector should perform any application specific operations and must clear the dma0 interrupt flags before exiting. */ void __isr(_dma_0_vector, ipl5) __dma0interrupt(void) { int dmaflags=dch0int&0xff; // read the interrupt flags // perform application specific operations in response to any interrupt flag set dch0intclr=0x000000ff; // clear the dma channel interrupt flags ifs1clr = 0x00010000; // be sure to clear the dma0 interrupt flags // before exiting the service routine. } note: the dma isr code example shows mplab ? c32 c compiler specific syntax. refer to your compiler manual regarding support for isrs.
pic32mx3xx/4xx ds61143e-page 240 preliminary ? 2008 microchip technology inc. 10.11 i/o pin control the dma controller module does not use any i/o pins.
? 2008 microchip technology inc. preliminary ds61143e-page 241 pic32mx3xx/4xx 11.0 usb on-the-go the universal serial bus (usb) module contains ana- log and digital components to provide a usb 2.0 full- speed and low-speed embedded host, full-speed device, or otg implementation with a minimum of external components. this module in host mode is intended for use as an embedded host and therefore does not implement a uhci or ohci controller. the usb module consists of the clock generator, the usb voltage comparators, the transceiver, the serial interface engine (sie), a dedicated usb dma control- ler, pull-up and pull-down resistors, and the register interface. a block diagram of the pic32mx usb otg module is presented in figure 11-1. the clock generator provides the 48 mhz clock required for usb full-speed and low-speed communi- cation. the voltage comparators monitor the voltage on the v bus pin to determine the state of the bus. the transceiver provides the analog translation between the usb bus and the digital logic. the sie is a state machine that transfers data to and from the endpoint buffers, and generates the hardware protocol for data transfers. the usb dma controller transfers data between the data buffers in ram and the sie. the inte- grated pull-up and pull-down resistors eliminate the need for external signaling components. the register interface allows the cpu to configure and communicate with the module. the pic32mx usb module includes the following features: ? usb full-speed support for host and device ? low-speed host support ? usb on-the-go (otg) support ? integrated signaling resistors ? integrated analog comparators for v bus monitoring ? integrated usb transceiver ? transaction handshaking performed by hardware ? endpoint buffering anywhere in system ram ? integrated dma controller to access system ram and flash note: this data sheet summarizes the features of the pic32mx3xx/4xx family of devices. it is not intended to be a comprehensive refer- ence source. refer to the ?pic32mx family reference manual? (ds61132) for a detailed description of this peripheral. note: important: the implementation and use of the usb specifications, as well as other third-party specifications or technol- ogies, may require licensing; including, but not limited to, usb implementers forum, inc. (also referred to as usb-if). the user is fully responsible for investigat- ing and satisfying any applicable licensing obligations.
pic32mx3xx/4xx ds61143e-page 242 preliminary ? 2008 microchip technology inc. figure 11-1: pic32mx3xx/4xx family usb interface diagram osc1 osc2 primary oscillator 8mhztypical frc oscillator tun<5:0> ( 4 ) pll 48 mhz usb clock ( 7 ) div x fupllen ( 6 ) (pb out) ( 1 ) ufrcen ( 3 ) (posc) fupllidiv ( 6 ) uf in ( 5 ) div 2 v usb d+ ( 2 ) d- ( 2 ) id ( 8 ) v bus transceiver sie v buson ( 8 ) comparators usb srp charge srp discharge registers and control interface transceiver power 3.3v to clock generator for core and peripherals sleep or idle sleep usben usb suspend cpu clock not posc usb module voltage system ram usb suspend full speed pull-up host pull-down low speed pull-up host pull-down id pull-up dma controller note 1: pb clock is only available on this pin for select ec modes. 2: pins can be used as digital inputs when usb is not enabled. 3: this bit field is contained in the osccon register. 4: this bit field is contained in the osctrm register. 5: usb pll u f in requirements: 4 mhz <= f in <= 5 mhz. 6: this bit field is contained in the devcfg2 register. 7: a 48 mhz clock is required for proper usb operation. 8: pins can be used as gpio w hen the usb module is disabled.
? 2008 microchip technology inc. preliminary ds61143e-page 243 pic32mx3xx/4xx 11.1 control registers the usb module includes the following special func- tion registers (sfrs): ? u1otgir: usb otg interrupt flag register ? u1otgie: usb otg interrupt enable register ? u1otgstat: usb comparator and pin status register ? u1otgcon: usb resistor and pin control register ? u1pwrc: usb power control register ? u1ir: usb pending interrupt register ? u1ie: usb interrupt enable register ? u1eir: usb pending error interrupt register ? u1eie: usb interrupt enable register ? u1stat: usb status fifo register ? u1con: usb module control register ? u1addr: usb address register ? u1frmh and u1frml: usb frame count registers ? u1tok: usb host control register ? u1sof: usb sof counter register ? u1bdtp1, u1bdtp2, and u1bdtp3: usb buffer descriptor table pointer register ? u1cnfg1: usb debug and idle register ? u1ep0-u1ep15: usb endpoint control registers 11.1.1 u1otgir register u1otgir (register 11-1) records changes on the id, data and v bus pins, enabling software to determine which event caused an interrupt. the interrupt bits are cleared by writing a ? 1 ? to the corresponding interrupt. 11.1.2 u1otgie register u1otgie (register 11-2) enables the corresponding interrupt status bits defined in the u1otgir register to generate an interrupt. 11.1.3 u1otgstat register u1otgstat (register 11-3) provides access to the status of the v bus voltage comparators and the debounced status of the id pin. 11.1.4 u1otgcon register u1otgcon (register 11-4) controls the operation of the v bus pin, and the pull-up and pull-down resistors. 11.1.5 u1pwrc register u1pwrc (register 11-5) controls the power-saving modes, as well as the module enable/disable control. 11.1.6 u1ir register u1ir (register 11-6) contains information on pending interrupts. once an interrupt bit is set, it can be cleared by writing a ? 1 ? to the corresponding bit. 11.1.7 u1ie register u1ie (register 11-7) values provide gating of the vari- ous interrupt signals onto the usb interrupt signal. these values do not interact with the usb module. setting any of these bits enables the corresponding interrupt source in the u1ir register. 11.1.8 u1eir register u1eir (register 11-8) contains information on pending error interrupt values. once an interrupt bit is set, it can be cleared by writing a ? 1 ? to the corresponding bit. 11.1.9 u1eie register u1eie (register 11-9) values provide gating of the var- ious interrupt signals onto the usb interrupt signal. these values do not interact with the usb module. set- ting any of these bits enables the respective interrupt source in the u1eir register if uerr is also set in the u1ie register. 11.1.10 u1stat register u1stat (register 11-10) is a 16-deep first in, first out (fifo) register. it is read-only by the cpu and read/write by the usb module. u1stat is only valid when the u1ir bit is set. 11.1.11 u1con register u1con (register 11-11) provides miscellaneous control and information about the module. 11.1.12 u1addr register u1addr (register 11-12) is a read/write register from the cpu side and read-only from the usb module side. although the register values affect the settings of the usb module, the content of the registers does not change during access. in device mode, this address defines the usb device address as assigned by the host during the setup phase. the firmware writes the address in response to the setup request. the address is automatically reset when a usb bus reset is detected. in host mode, the module transmits the address provided in this register with the corresponding token packet. this allows the usb module to uniquely address the connected device. 11.1.13 u1frmh and u1frml registers u1frmh and u1frml (register 11-13 and register 11-14) are read-only registers. the frame number is formed by concatenating the two 8-bit regis- ters. the high-order byte is in the u1frmh register, and the low-order byte is in u1frml.
pic32mx3xx/4xx ds61143e-page 244 preliminary ? 2008 microchip technology inc. 11.1.14 u1tok register u1tok (register 11-15) is a read/write register required when the module operates as a host. it is used to specify the token type, pid<3:0> (packet id), and the endpoint, ep<3:0>, being addressed by the host processor. writing to this register triggers a host transaction. 11.1.15 u1sof register u1sof (register 11-16) threshold is a read/write reg- ister that contains the count bits of the start-of-frame (sof) threshold value, and are used in host mode only. to prevent colliding a packet data with the sof token that is sent every 1 ms, the usb module will not send any new transactions within the last u1sof byte times. the usb module will complete any transactions that are in progress. in host mode, the sof interrupt occurs when this threshold is reached, not when the sof occurs. in device mode, the interrupt occurs when a sof is received. transactions started within the sof threshold are held by the usb module until after the sof token is sent. 11.1.16 u1bdtp1, u1bdtp2 and u1bdtp3 registers these registers (register 11-17, register 11-18 and register 11-19) are read/write registers that define the upper 23 bits of the 32-bit base address of the buffer descriptor table (bdt) in the system memory. the bdt is forced to be 512 byte-aligned. this register allows relocation of the bdt in real time. 11.1.17 u1cnfg1 register u1cnfg1 (register 11-20) is a read/write register that controls the debug and idle behavior of the module. the register must be preprogrammed prior to enabling the module. 11.1.18 u1ep0-u1ep15 registers these registers control the behavior of the correspond- ing endpoint. 11.1.19 associated registers the following registers are not part of the usb module but are associated with module operation. ? iec1: interrupt enable control register (register 11-22) ? ifs1: interrupt flag status register (register 8-5) ? devcfg2: device configuration word 2 (register 27-3) ? osccon: oscillator control register (register 4-1) 11.1.20 clearing usb otg interrupts unlike other device-level interrupts, the usb otg interrupt status flags are not freely writable in software. all usb otg flag bits are implemented as hardware- set bits. these bits can only be cleared in software by writing a ? 1 ? to their locations. writing a ? 0 ? to a flag bit has no effect. note: throughout this section, a bit that can only be cleared by writing a ? 1 ? to its location is referred to as ?write ? 1 ? to clear bit?. in reg- ister descriptions, this function is indicated by the descriptor ?k?.
? 2008 microchip technology inc. preliminary ds61143e-page 245 pic32mx3xx/4xx table 11-1: usb register summary virtual address name bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 bf88_5040 u1otgir 31:24 ? ? ? ? ? ? ? ? 23:16 ? ? ? ? ? ? ? ? 15:8 ? ? ? ? ? ? ? ? 7:0 idif t1msecif lstateif actvif sesvdif sesendif ? vbusvdif bf88_5050 u1otgie 31:24 ? ? ? ? ? ? ? ? 23:16 ? ? ? ? ? ? ? ? 15:8 ? ? ? ? ? ? ? ? 7:0 idie t1msecie lstateie actvie sesvdie sesendie ? vbusvdie bf88_5060 u1otgstat 31:24 ? ? ? ? ? ? ? ? 23:16 ? ? ? ? ? ? ? ? 15:8 ? ? ? ? ? ? ? ? 7:0 id ?lstate ? sesvd sesend ? vbusvd bf88_5070 u1otgcon 31:24 ? ? ? ? ? ? ? ? 23:16 ? ? ? ? ? ? ? ? 15:8 ? ? ? ? ? ? ? ? 7:0 dppulup dmpulup dppuldwn dmpuldwn vbuson otgen vbuschg vbusdis bf88_5080 u1pwrc 31:24 ? ? ? ? ? ? ? ? 23:16 ? ? ? ? ? ? ? ? 15:8 ? ? ? ? ? ? ? ? 7:0 uactpnd ? ?uslpgrd ? ? ususpend usbpwr bf88_5200 u1ir 31:24 ? ? ? ? ? ? ? ? 23:16 ? ? ? ? ? ? ? ? 15:8 ? ? ? ? ? ? ? ? 7:0 stallif attachif resumeif idleif trnif sofif uerrif urstif detachif bf88_5210 u1ie 31:24 ? ? ? ? ? ? ? ? 23:16 ? ? ? ? ? ? ? ? 15:8 ? ? ? ? ? ? ? ? 7:0 stallie attachie resumeie idleie trnie sofie uerrie urstie detachie bf88_5220 u1eir 31:24 ? ? ? ? ? ? ? ? 23:16 ? ? ? ? ? ? ? ? 15:8 ? ? ? ? ? ? ? ? 7:0 btsef bmxef dmaef btoef dfn8ef crc16ef crc5ef pidef eofef bf88_5230 u1eie 31:24 ? ? ? ? ? ? ? ? 23:16 ? ? ? ? ? ? ? ? 15:8 ? ? ? ? ? ? ? ? 7:0 btsee bmxee dmaee btoee dfn8ee crc16ee crc5ee pidee eofee bf88_5240 u1stat 31:24 ? ? ? ? ? ? ? ? 23:16 ? ? ? ? ? ? ? ? 15:8 ? ? ? ? ? ? ? ? 7:0 endpt<3:0> dir ppbi ? ?
pic32mx3xx/4xx ds61143e-page 246 preliminary ? 2008 microchip technology inc. bf88_5250 u1con 31:24 ? ? ? ? ? ? ? ? 23:16 ? ? ? ? ? ? ? ? 15:8 ? ? ? ? ? ? ? ? 7:0 jstate se0 pktdis usbrst hosten resume ppbrst usben tokbusy sofen bf88_5260 u1addr 31:24 ? ? ? ? ? ? ? ? 23:16 ? ? ? ? ? ? ? ? 15:8 ? ? ? ? ? ? ? ? 7:0 lspden devaddr<6:0> bf88_5270 u1bdtp1 31:24 ? ? ? ? ? ? ? ? 23:16 ? ? ? ? ? ? ? ? 15:8 ? ? ? ? ? ? ? ? 7:0 bdtptrl<15:9> ? bf88_5280 u1frml 31:24 ? ? ? ? ? ? ? ? 23:16 ? ? ? ? ? ? ? ? 15:8 ? ? ? ? ? ? ? ? 7:0 frml<7:0> bf88_5290 u1frmh 31:24 ? ? ? ? ? ? ? ? 23:16 ? ? ? ? ? ? ? ? 15:8 ? ? ? ? ? ? ? ? 7:0 ? ? ? ? ? frmh<10:8> bf88_52a0 u1tok 31:24 ? ? ? ? ? ? ? ? 23:16 ? ? ? ? ? ? ? ? 15:8 ? ? ? ? ? ? ? ? 7:0 pid<3:0> ep<3:0> bf88_52b0 u1sof 31:24 ? ? ? ? ? ? ? ? 23:16 ? ? ? ? ? ? ? ? 15:8 ? ? ? ? ? ? ? ? 7:0 cnt<7:0> bf88_52c0 u1bdtp2 31:24 ? ? ? ? ? ? ? ? 23:16 ? ? ? ? ? ? ? ? 15:8 ? ? ? ? ? ? ? ? 7:0 bdtptrh<23:16> bf88_52d0 u1bdtp3 31:24 ? ? ? ? ? ? ? ? 23:16 ? ? ? ? ? ? ? ? 15:8 ? ? ? ? ? ? ? ? 7:0 bdtptru<31:24> bf88_52e0 u1cnfg1 31:24 ? ? ? ? ? ? ? ? 23:16 ? ? ? ? ? ? ? ? 15:8 ? ? ? ? ? ? ? ? 7:0 uteye uoemon usbfrz usbsidl ? ? ? ? bf88_5300 u1ep0 31:24 ? ? ? ? ? ? ? ? 23:16 ? ? ? ? ? ? ? ? 15:8 ? ? ? ? ? ? ? ? 7:0 lspd retrydis ? epcondis eprxen eptxen epstall ephshk table 11-1: usb register summary (continued) virtual address name bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0
? 2008 microchip technology inc. preliminary ds61143e-page 247 pic32mx3xx/4xx bf88_5310 u1ep1 31:24 ? ? ? ? ? ? ? ? 23:16 ? ? ? ? ? ? ? ? 15:8 ? ? ? ? ? ? ? ? 7:0 ? ? ? epcondis eprxen eptxen epstall ephshk bf88_5320 u1ep2 31:24 ? ? ? ? ? ? ? ? 23:16 ? ? ? ? ? ? ? ? 15:8 ? ? ? ? ? ? ? ? 7:0 ? ? ? epcondis eprxen eptxen epstall ephshk bf88_5330 u1ep3 31:24 ? ? ? ? ? ? ? ? 23:16 ? ? ? ? ? ? ? ? 15:8 ? ? ? ? ? ? ? ? 7:0 ? ? ? epcondis eprxen eptxen epstall ephshk bf88_5340 u1ep4 31:24 ? ? ? ? ? ? ? ? 23:16 ? ? ? ? ? ? ? ? 15:8 ? ? ? ? ? ? ? ? 7:0 ? ? ? epcondis eprxen eptxen epstall ephshk bf88_5350 u1ep5 31:24 ? ? ? ? ? ? ? ? 23:16 ? ? ? ? ? ? ? ? 15:8 ? ? ? ? ? ? ? ? 7:0 ? ? ? epcondis eprxen eptxen epstall ephshk bf88_5360 u1ep6 31:24 ? ? ? ? ? ? ? ? 23:16 ? ? ? ? ? ? ? ? 15:8 ? ? ? ? ? ? ? ? 7:0 ? ? ? epcondis eprxen eptxen epstall ephshk bf88_5370 u1ep7 31:24 ? ? ? ? ? ? ? ? 23:16 ? ? ? ? ? ? ? ? 15:8 ? ? ? ? ? ? ? ? 7:0 ? ? ? epcondis eprxen eptxen epstall ephshk bf88_5380 u1ep8 31:24 ? ? ? ? ? ? ? ? 23:16 ? ? ? ? ? ? ? ? 15:8 ? ? ? ? ? ? ? ? 7:0 ? ? ? epcondis eprxen eptxen epstall ephshk bf88_5390 u1ep9 31:24 ? ? ? ? ? ? ? ? 23:16 ? ? ? ? ? ? ? ? 15:8 ? ? ? ? ? ? ? ? 7:0 ? ? ? epcondis eprxen eptxen epstall ephshk bf88_53a0 u1ep10 31:24 ? ? ? ? ? ? ? ? 23:16 ? ? ? ? ? ? ? ? 15:8 ? ? ? ? ? ? ? ? 7:0 ? ? ? epcondis eprxen eptxen epstall ephshk bf88_53b0 u1ep11 31:24 ? ? ? ? ? ? ? ? 23:16 ? ? ? ? ? ? ? ? 15:8 ? ? ? ? ? ? ? ? 7:0 ? ? ? epcondis eprxen eptxen epstall ephshk table 11-1: usb register summary (continued) virtual address name bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0
pic32mx3xx/4xx ds61143e-page 248 preliminary ? 2008 microchip technology inc. bf88_53c0 u1ep12 31:24 ? ? ? ? ? ? ? ? 23:16 ? ? ? ? ? ? ? ? 15:8 ? ? ? ? ? ? ? ? 7:0 ? ? ? epcondis eprxen eptxen epstall ephshk bf88_53d0 u1ep13 31:24 ? ? ? ? ? ? ? ? 23:16 ? ? ? ? ? ? ? ? 15:8 ? ? ? ? ? ? ? ? 7:0 ? ? ? epcondis eprxen eptxen epstall ephshk bf88_53e0 u1ep14 31:24 ? ? ? ? ? ? ? ? 23:16 ? ? ? ? ? ? ? ? 15:8 ? ? ? ? ? ? ? ? 7:0 ? ? ? epcondis eprxen eptxen epstall ephshk bf88_53f0 u1ep15 31:24 ? ? ? ? ? ? ? ? 23:16 ? ? ? ? ? ? ? ? 15:8 ? ? ? ? ? ? ? ? 7:0 ? ? ? epcondis eprxen eptxen epstall ephshk table 11-1: usb register summary (continued) virtual address name bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 table 11-2: usb interrupt register summary (1) virtual address name bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 bf88_1040 ifs1 31:24 ? ? ? ? ? ? usbif fceif bf88_1070 iec1 31:24 ? ? ? ? ? ?usbie fceie bf88_1140 ipc11 15:8 ? ? ? usbip<2:0> usbis<1:0> note 1: this summary table contains partial register definitions that only pertain to the usb peripheral. refer to the ? pic32mx family reference manual ? (ds61132) for a detailed description of these registers. table 11-3: oscilla tor configuration (1) virtual address name bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 bf88_f000 osccon 7:0 clklock ulock lock slpen cf ufrcen soscen oswen bfc0_2ff4 devcfg2 15:8 fupllen (2) ? ? ? ? fupllidiv<2:0> (2) note 1: this summary table contains partial register definitions that only pertain to the usb peripheral. refer to the ? pic32mx family reference manual ? (ds61132) for a detailed description of these registers. note 2: fupllen and fpllodiv<2:0> are only ava ilable on pic32mx4xx family variants.
? 2008 microchip technology inc. preliminary ds61143e-page 249 pic32mx3xx/4xx register 11-1: u1otgir: usb otg interrupt flag register r-x r-x r-x r-x r-x r-x r-x r-x ? ? ? ? ? ? ? ? bit 31 bit 24 r-x r-x r-x r-x r-x r-x r-x r-x ? ? ? ? ? ? ? ? bit 23 bit 16 r-x r-x r-x r-x r-x r-x r-x r-x ? ? ? ? ? ? ? ? bit 15 bit 8 r/w/k-0 r/w/k-0 r/w/k-0 r/w/k-0 r/w/k-0 r/w/k-0 r-x r/w/k-0 idif t1msecif lstateif actvif sesvdif sesendif ? vbusvdif bit 7 bit 0 legend: r = readable bit w = writable bit p = programmable bit r = reserved bit u = unimplemented bit k = write ?1? to clear -n = bit value at por: (?0?, ?1?, x = unknown) bit 31-8 reserved: write ? 0 ?; ignore read bit 7 idif: id state change indicator bit write a ? 1 ? to this bit to clear the interrupt. 1 = change in id state detected 0 = no change in id state detected bit 6 t1msecif: 1 millisecond timer bit write a ? 1 ? to this bit to clear the interrupt. 1 = 1 millisecond timer has expired 0 = 1 millisecond timer has not expired bit 5 lstateif: line state stable indicator bit write a ? 1 ? to this bit to clear the interrupt. 1 = usb line state has been stable for 1 ms, but different from last time 0 = usb line state has not been stable for 1 ms bit 4 actvif: bus activity indicator bit write a ? 1 ? to this bit to clear the interrupt. 1 = activity on the d+, d-, id, or v bus pins has caused the device to wake-up 0 = activity has not been detected bit 3 sesvdif: session valid change indicator bit write a ? 1 ? to this bit to clear the interrupt. 1 = v bus voltage has dropped below the session end level 0 = v bus voltage has not dropped below the session end level bit 2 sesendif: b-device v bus change indicator bit write a ? 1 ? to this bit to clear the interrupt. 1 = a change on the session end input was detected 0 = no change on the session end input was detected bit 1 reserved: write ? 0 ?; ignore read
pic32mx3xx/4xx ds61143e-page 250 preliminary ? 2008 microchip technology inc. register 11-1: u1otgir: usb otg interrupt flag register r-x r-x r-x r-x r-x r-x r-x r-x ? ? ? ? ? ? ? ? bit 31 bit 24 r-x r-x r-x r-x r-x r-x r-x r-x ? ? ? ? ? ? ? ? bit 23 bit 16 r-x r-x r-x r-x r-x r-x r-x r-x ? ? ? ? ? ? ? ? bit 15 bit 8 r/w/k-0 r/w/k-0 r/w/k-0 r/w/k-0 r/w/k-0 r/w/k-0 r-x r/w/k-0 idif t1msecif lstateif actvif sesvdif sesendif ? vbusvdif bit 7 bit 0 legend: r = readable bit w = writable bit p = programmable bit r = reserved bit u = unimplemented bit k = write ?1? to clear -n = bit value at por: (?0?, ?1?, x = unknown) bit 31-8 reserved: write ? 0 ?; ignore read bit 7 idif: id state change indicator bit write a ? 1 ? to this bit to clear the interrupt. 1 = change in id state detected 0 = no change in id state detected bit 6 t1msecif: 1 millisecond timer bit write a ? 1 ? to this bit to clear the interrupt. 1 = 1 millisecond timer has expired 0 = 1 millisecond timer has not expired bit 5 lstateif: line state stable indicator bit write a ? 1 ? to this bit to clear the interrupt. 1 = usb line state has been stable for 1 ms, but different from last time 0 = usb line state has not been stable for 1 ms bit 4 actvif: bus activity indicator bit write a ? 1 ? to this bit to clear the interrupt. 1 = activity on the d+, d-, id, or v bus pins has caused the device to wake-up 0 = activity has not been detected bit 3 sesvdif: session valid change indicator bit write a ? 1 ? to this bit to clear the interrupt. 1 = v bus voltage has dropped below the session end level 0 = v bus voltage has not dropped below the session end level bit 2 sesendif: b-device v bus change indicator bit write a ? 1 ? to this bit to clear the interrupt. 1 = a change on the session end input was detected 0 = no change on the session end input was detected bit 1 reserved: write ? 0 ?; ignore read
? 2008 microchip technology inc. preliminary ds61143e-page 251 pic32mx3xx/4xx bit 0 vbusvdif: a-device v bus change indicator bit write a ? 1 ? to this bit to clear the interrupt. 1 = change on the session valid input detected 0 = no change on the session valid input detected register 11-1: u1otgir: usb otg interrupt flag register
pic32mx3xx/4xx ds61143e-page 252 preliminary ? 2008 microchip technology inc. register 11-2: u1otgie: usb otg interrupt enable register r-x r-x r-x r-x r-x r-x r-x r-x ? ? ? ? ? ? ? ? bit 31 bit 24 r-x r-x r-x r-x r-x r-x r-x r-x ? ? ? ? ? ? ? ? bit 23 bit 16 r-x r-x r-x r-x r-x r-x r-x r-x ? ? ? ? ? ? ? ? bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 idie t1msecie lstateie actvie sesvdie sesendie ? vbusvdie bit 7 bit 0 legend: r = readable bit w = writable bit p = programmable bit r = reserved bit u = unimplemented bit -n = bit value at por: (?0?, ?1?, x = unknown) bit 31-8 reserved: write ? 0 ?; ignore read bit 7 idie: id interrupt enable bit 1 = id interrupt enabled 0 = id interrupt disabled bit 6 t1msecie: 1 millisecond timer interrupt enable bit 1 = 1 millisecond timer interrupt enabled 0 = 1 millisecond timer interrupt disabled bit 5 lstateie: line state interrupt enable bit 1 = line state interrupt enabled 0 = line state interrupt disabled bit 4 actvie: bus activity interrupt enable bit 1 = activity interrupt enabled 0 = activity interrupt disabled bit 3 sesvdie: session valid interrupt enable bit 1 = session valid interrupt enabled 0 = session valid interrupt disabled bit 2 sesendie: b-session end interrupt enable bit 1 = b-session end interrupt enabled 0 = b-session end interrupt disabled bit 1 reserved: write ? 0 ?; ignore read bit 0 vbusvdie: a-v bus valid interrupt enable bit 1 = a-v bus valid interrupt enabled 0 = a-v bus valid interrupt disabled
? 2008 microchip technology inc. preliminary ds61143e-page 253 pic32mx3xx/4xx register 11-3: u1otgstat: usb otg status register r-x r-x r-x r-x r-x r-x r-x r-x ? ? ? ? ? ? ? ? bit 31 bit 24 r-x r-x r-x r-x r-x r-x r-x r-x ? ? ? ? ? ? ? ? bit 23 bit 16 r-x r-x r-x r-x r-x r-x r-x r-x ? ? ? ? ? ? ? ? bit 15 bit 8 r-0 r-x r-0 r-x r-0 r-0 r-x r-0 id ?lstate ? sesvd sesend ? vbusvd bit 7 bit 0 legend: r = readable bit w = writable bit p = programmable bit r = reserved bit u = unimplemented bit -n = bit value at por: (?0?, ?1?, x = unknown) bit 31-8 reserved: write ? 0 ?; ignore read bit 7 id: id pin state indicator bit 1 = no cable is attached or a type b cable has been plugged into the usb receptacle 0 = a type a otg cable has been plugged into the usb receptacle bit 6 reserved: write ? 0 ?; ignore read bit 5 lstate: line state stable indicator bit 1 = usb line state (u1con[se0] and u1con[jstate]) has been stable for the previous 1 ms 0 = usb line state (u1con[se0] and u1con[jstate]) has not been stable for the previous 1 ms bit 4 reserved: write ? 0 ?; ignore read bit 3 sesvd: session valid indicator bit 1 = v bus voltage is above session valid on the a or b device 0 = v bus voltage is below session valid on the a or b device bit 2 sesend: b-session end indicator bit 1 = v bus voltage is below session valid on the b device 0 = v bus voltage is above session valid on the b device bit 1 reserved: write ? 0 ?; ignore read bit 0 vbusvd: a-v bus valid indicator bit 1 = v bus voltage is above session valid on the a device 0 = v bus voltage is below session valid on the a device
pic32mx3xx/4xx ds61143e-page 254 preliminary ? 2008 microchip technology inc. register 11-4: u1otgcon: usb otg control register r-x r-x r-x r-x r-x r-x r-x r-x ? ? ? ? ? ? ? ? bit 31 bit 24 r-x r-x r-x r-x r-x r-x r-x r-x ? ? ? ? ? ? ? ? bit 23 bit 16 r-x r-x r-x r-x r-x r-x r-x r-x ? ? ? ? ? ? ? ? bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 dppulup dmpulup dppuldwn dmpuldwn vbuson otgen vbuschg vbusdis bit 7 bit 0 legend: r = readable bit w = writable bit p = programmable bit r = reserved bit u = unimplemented bit -n = bit value at por: (?0?, ?1?, x = unknown) bit 31-8 reserved: write ? 0 ?; ignore read bit 7 dppulup: d+ pull-up enable bit 1 = d+ data line pull-up resistor is enabled 0 = d+ data line pull-up resistor is disabled bit 6 dmpulup: d- pull-up enable bit 1 = d- data line pull-up resistor is enabled 0 = d- data line pull-up resistor is disabled bit 5 dppuldwn: d+ pull-down enable bit 1 = d+ data line pull-down resistor is enabled 0 = d+ data line pull-down resistor is disabled bit 4 dmpuldwn: d- pull-down enable bit 1 = d- data line pull-down resistor is enabled 0 = d- data line pull-down resistor is disabled bit 3 vbuson: v bus power-on bit 1 = v bus line is powered 0 = v bus line is not powered bit 2 otgen: otg functionality enable bit 1 = dppulup, dmpulup, dppuldwn, and dmpuldwn bits are under software control 0 = dppulup, dmpulup, dppuldwn, and dmpuldwn bits are under usb hardware control bit 1 vbuschg: v bus charge enable bit 1 = v bus line is charged through a pull-up resistor 0 = v bus line is not charged through a resistor bit 0 vbusdis: v bus discharge enable bit 1 = v bus line is discharged through a pull-down resistor 0 = v bus line is not discharged through a resistor
? 2008 microchip technology inc. preliminary ds61143e-page 255 pic32mx3xx/4xx register 11-5: u1pwrc: usb power control register r-x r-x r-x r-x r-x r-x r-x r-x ? ? ? ? ? ? ? ? bit 31 bit 24 r-x r-x r-x r-x r-x r-x r-x r-x ? ? ? ? ? ? ? ? bit 23 bit 16 r-x r-x r-x r-x r-x r-x r-x r-x ? ? ? ? ? ? ? ? bit 15 bit 8 r-0 r-x r-x r/w-0 r-x r-x r/w-0 r/w-0 uactpnd ? ? uslpgrd ? ? ususpend usbpwr bit 7 bit 0 legend: r = readable bit w = writable bit p = programmable bit r = reserved bit u = unimplemented bit -n = bit value at por: (?0?, ?1?, x = unknown) bit 31-8 reserved: write ? 0 ?; ignore read bit 7 uactpnd: usb suspend mode bit 1 = usb bus activity has been detected; but an interrupt is pending, it has not been generated yet 0 = an interrupt is not pending bit 6-5 reserved: write ? 0 ?; ignore read bit 4 uslpgrd: usb sleep entry guard bit 1 = sleep entry is blocked if usb bus activity is detected or if a notification is pending 0 = usb module does not block sleep entry bit 3-2 reserved: write ? 0 ?; ignore read bit 1 ususpend: usb suspend mode bit 1 = usb module is placed in suspend mode (the 48 mhz usb clock will be gated off. the transceiver is placed in a low-power state.) 0 = usb module operates normally. bit 0 usbpwr: usb operation enable bit 1 = usb module is turned on 0 = usb module is disabled (outputs held inactive, device pins not used by usb, analog features are shut-down to reduce power consumption.)
pic32mx3xx/4xx ds61143e-page 256 preliminary ? 2008 microchip technology inc. register 11-6: u1ir: usb interrupt register r-x r-x r-x r-x r-x r-x r-x r-x ? ? ? ? ? ? ? ? bit 31 bit 24 r-x r-x r-x r-x r-x r-x r-x r-x ? ? ? ? ? ? ? ? bit 23 bit 16 r-x r-x r-x r-x r-x r-x r-x r-x ? ? ? ? ? ? ? ? bit 15 bit 8 r/w/k-0 r/w/k-0 r/w/k-0 r/w/k-0 r/w/k-0 r/w/k-0 r/k-0 r/w/k-0 stallif attachif resumeif idleif trnif sofif uerrif urstif (5) detachif (6) bit 7 bit 0 legend: r = readable bit w = writable bit p = programmable bit r = reserved bit u = unimplemented bit k = write ?1? to clear -n = bit value at por: (0, 1, x = unknown) bit 31-8 reserved: write ? 0 ?; ignore read bit 7 stallif: stall handshake interrupt bit write a ? 1 ? to this bit to clear the interrupt. 1 = in host mode a stall handshake was received during the handshake phase of the transaction in device mode a stall handshake was transmitted during the handshake phase of the transaction 0 = stall handshake has not been sent bit 6 attachif: peripheral attach interrupt bit (1) write a ? 1 ? to this bit to clear the interrupt. 1 = peripheral attachment was detected by the usb module 0 = peripheral attachment was not detected bit 5 resumeif: resume interrupt bit (2) write a ? 1 ? to this bit to clear the interrupt. 1 = k-state is observed on the d+ or d- pin for 2.5 s 0 = k-state is not observed bit 4 idleif: idle detect interrupt bit write a ? 1 ? to this bit to clear the interrupt. 1 = idle condition detected (constant idle state of 3 ms or more) 0 = no idle condition detected bit 3 trnif: token processing complete interrupt bit (3) write a ? 1 ? to this bit to clear the interrupt. 1 = processing of current token is complete; a read of the u1stat register will provide endpoint information 0 = processing of current token not complete
? 2008 microchip technology inc. preliminary ds61143e-page 257 pic32mx3xx/4xx bit 2 sofif: sof token interrupt bit write a ? 1 ? to this bit to clear the interrupt. 1 = sof token received by the peripheral or the sof threshold reached by the host 0 = sof token was not received nor threshold reached bit 1 uerrif: usb error condition interrupt bit (4) write a ? 1 ? to this bit to clear the interrupt. 1 = unmasked error condition has occurred 0 = unmasked error condition has not occurred bit 0 urstif: usb reset interrupt bit (device mode) 1 = valid usb reset has occurred 0 = no usb reset has occurred detachif: usb detach interrupt bit (host mode) 1 = peripheral detachment was detected by the usb module 0 = peripheral detachment was not detected note 1: this bit is valid only if the hosten bit is set (see register 11-11), there is no activity on the usb for 2.5 s, and the current bus state is not se0. 2: when not in suspend mode, this interrupt should be disabled. 3: clearing this bit will cause the stat fifo to advance. 4: only error conditions enabled through the u1eie register will set this bit. 5: device mode. 6: host mode. register 11-6: u1ir: usb interrupt register (continued)
pic32mx3xx/4xx ds61143e-page 258 preliminary ? 2008 microchip technology inc. register 11-7: u1ie: usb interrupt enable register (1) r-x r-x r-x r-x r-x r-x r-x r-x ? ? ? ? ? ? ? ? bit 31 bit 24 r-x r-x r-x r-x r-x r-x r-x r-x ? ? ? ? ? ? ? ? bit 23 bit 16 r-x r-x r-x r-x r-x r-x r-x r-x ? ? ? ? ? ? ? ? bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 stallie attachie resumeie idleie trnie sofie uerrie urstie (2) detachie (3) bit 7 bit 0 legend: r = readable bit w = writable bit p = programmable bit r = reserved bit u = unimplemented bit -n = bit value at por: (?0?, ?1?, x = unknown) bit 31-8 reserved: write ? 0 ?; ignore read bit 7 stallie: stall handshake interrupt enable bit 1 = stall interrupt enabled 0 = stall interrupt disabled bit 6 attachie: attach interrupt enable bit 1 = attach interrupt enabled 0 = attach interrupt disabled bit 5 resumeie: resume interrupt enable bit 1 = resume interrupt enabled 0 = resume interrupt disabled bit 4 idleie: idle detect interrupt enable bit 1 = idle interrupt enabled 0 = idle interrupt disabled bit 3 trnie: token processing complete interrupt enable bit 1 = trnif interrupt enabled 0 = trnif interrupt disabled bit 2 sofie: sof token interrupt enable bit 1 = sofif interrupt enabled 0 = sofif interrupt disabled bit 1 uerrie: usb error interrupt enable bit 1 = usb error interrupt enabled 0 = usb error interrupt disabled
? 2008 microchip technology inc. preliminary ds61143e-page 259 pic32mx3xx/4xx bit 0 urstie: usb reset interrupt enable bit (device mode) 1 = urstif interrupt enabled 0 = urstif interrupt disabled detachie: usb detach interrupt enable bit (host mode) 1 = dattchif interrupt enabled 0 = dattchif interrupt disabled note 1: for an interrupt to propagate to the u1ir bit usbif(ifs1<25>), the uerrie bit (u1ie<1>) must be set. 2: device mode. 3: host mode. register 11-7: u1ie: usb interrupt enable register (1) (continued)
pic32mx3xx/4xx ds61143e-page 260 preliminary ? 2008 microchip technology inc. register 11-8: u1eir: usb error interrupt status register r-x r-x r-x r-x r-x r-x r-x r-x ? ? ? ? ? ? ? ? bit 31 bit 24 r-x r-x r-x r-x r-x r-x r-x r-x ? ? ? ? ? ? ? ? bit 23 bit 16 r-x r-x r-x r-x r-x r-x r-x r-x ? ? ? ? ? ? ? ? bit 15 bit 8 r/w/k-0 r/w/k-0 r/w/k-0 r/w/k-0 r/w/k-0 r/w/k-0 r/w-0 r/w-0 btsef bmxef dmaef btoef dfn8ef crc16ef crc5ef (4) pidef eofef (5) bit 7 bit 0 legend: r = readable bit w = writable bit p = programmable bit r = reserved bit u = unimplemented bit k = write ?1? to clear -n = bit value at por: (?0?, ?1?, x = unknown) bit 31-8 reserved: write ? 0 ?; ignore read bit 7 btsef: bit stuff error flag bit write a ? 1 ? to this bit to clear the interrupt. 1 = packet rejected due to bit stuff error 0 = packet accepted bit 6 bmxef: bus matrix error flag bit write a ? 1 ? to this bit to clear the interrupt. 1 = the base address, of the bdt, or the address of an individual buffer pointed to by a bdt entry, is invalid. 0 = no address error bit 5 dmaef: dma error flag bit (1) write a ? 1 ? to this bit to clear the interrupt. 1 = usb dma error condition detected 0 = no dma error bit 4 btoef: bus turnaround time-out error flag bit (2) write a ? 1 ? to this bit to clear the interrupt. 1 = bus turnaround time-out has occurred 0 = no bus turnaround time-out bit 3 dfn8ef: data field size error flag bit write a ? 1 ? to this bit to clear the interrupt. 1 = data field received is not an integral number of bytes 0 = data field received is an integral number of bytes bit 2 crc16ef: crc16 failure flag bit write a ? 1 ? to this bit to clear the interrupt. 1 = data packet rejected due to crc16 error 0 = data packet accepted
? 2008 microchip technology inc. preliminary ds61143e-page 261 pic32mx3xx/4xx bit 1 crc5ef: crc5 host error flag bit (3) (device mode) write a ? 1 ? to this bit to clear the interrupt. 1 = token packet rejected due to crc5 error 0 = token packet accepted eofef: eof error flag bit (host mode) 1 = eof error condition detected 0 = no eof error condition bit 0 pidef: pid check failure flag bit 1 = pid check failed 0 = pid check passed note 1: this type of error occurs when the module?s request for the dma bus is not granted in time to service the module?s demand for memory, resulting in an overflow or underflow condition, and/or the allocated buffer size is not sufficient to store the received data packet causing it to be truncated. 2: this type of error occurs when more than 16 bit-times of idle from the previous (end-of-packet) eop has elapsed. 3: this type of error occurs when the module is transmitting or receiving data and the sof counter has reached zero. 4: device mode. 5: host mode. register 11-8: u1eir: usb error interrupt status register
pic32mx3xx/4xx ds61143e-page 262 preliminary ? 2008 microchip technology inc. register 11-9: u1eie: usb error interrupt enable register (1) r-x r-x r-x r-x r-x r-x r-x r-x ? ? ? ? ? ? ? ? bit 31 bit 24 r-x r-x r-x r-x r-x r-x r-x r-x ? ? ? ? ? ? ? ? bit 23 bit 16 r-x r-x r-x r-x r-x r-x r-x r-x ? ? ? ? ? ? ? ? bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 btsee bmxee dmaee btoee dfn8ee crc16ee crc5ee (2) pidee eofee (3) bit 7 bit 0 legend: r = readable bit w = writable bit p = programmable bit r = reserved bit u = unimplemented bit -n = bit value at por: (?0?, ?1?, x = unknown) bit 31-8 reserved: write ? 0 ?; ignore read bit 7 btsee: bit stuff error interrupt enable bit 1 = btsef interrupt enabled 0 = btsef interrupt disabled bit 6 bmxee: bus matrix error interrupt enable bit 1 = bmxef interrupt enabled 0 = bmxef interrupt disabled bit 5 dmaee: dma error interrupt enable bit 1 = dmaef interrupt enabled 0 = dmaef interrupt disabled bit 4 btoee: bus turnaround time-out error interrupt enable bit 1 = btoef interrupt enabled 0 = btoef interrupt disabled bit 3 dfn8ee: data field size error interrupt enable bit 1 = dfn8ef interrupt enabled 0 = dfn8ef interrupt disabled bit 2 crc16ee: crc16 failure interrupt enable bit 1 = crc16ef interrupt enabled 0 = crc16ef interrupt disabled note 1: for an error interrupt to propagate to usbif(ifs1<25>), the uerrie bit (u1ie<1> must be set). 2: device mode. 3: host mode.
? 2008 microchip technology inc. preliminary ds61143e-page 263 pic32mx3xx/4xx bit 1 crc5ee: crc5 host error interrupt enable bit (device mode) 1 = crc5ef interrupt enabled 0 = crc5ef interrupt disabled eofee: eof error interrupt enable bit (host mode) 1 = eof interrupt enabled 0 = eof interrupt disabled bit 0 pidee: pid check failure interrupt enable bit 1 = pidef interrupt enabled 0 = pidef interrupt disabled register 11-9: u1eie: usb error interrupt enable register (1) (continued) note 1: for an error interrupt to propagate to usbif(ifs1<25>), the uerrie bit (u1ie<1> must be set). 2: device mode. 3: host mode.
pic32mx3xx/4xx ds61143e-page 264 preliminary ? 2008 microchip technology inc. register 11-10: u1stat: usb status fifo register r-x r-x r-x r-x r-x r-x r-x r-x ? ? ? ? ? ? ? ? bit 31 bit 24 r-x r-x r-x r-x r-x r-x r-x r-x ? ? ? ? ? ? ? ? bit 23 bit 16 r-x r-x r-x r-x r-x r-x r-x r-x ? ? ? ? ? ? ? ? bit 15 bit 8 r-x r-x r-x r-x r-x r-x r-x r-x endpt<3:0> dir ppbi ? ? bit 7 bit 0 legend: r = readable bit w = writable bit p = programmable bit r = reserved bit u = unimplemented bit -n = bit value at por: (?0?, ?1?, x = unknown) bit 31-8 reserved: write ? 0 ?; ignore read bit 7-4 endpt<3:0>: encoded number of last endpoint activity bits (represents the number of the bdt, updated by the last usb transfer.) 1111 = endpoint 15 1110 = endpoint 14 .... 0001 = endpoint 1 0000 = endpoint 0 bit 3 dir: last bd direction indicator bit 1 = last transaction was a transmit transfer (tx) 0 = last transaction was a receive transfer (rx) bit 2 ppbi: ping-pong bd pointer indicator bit 1 = the last transaction was to the odd bd bank 0 = the last transaction was to the even bd bank bit 1-0 reserved: write ? 0 ?; ignore read note: the u1stat register is a window into a 4-byte fifo maintained by the usb module. u1stat value is only valid when u1ir is active. clearing the u1ir bit advances the fifo. data in register is invalid when u1ir = 0 .
? 2008 microchip technology inc. preliminary ds61143e-page 265 pic32mx3xx/4xx register 11-11: u1con: us b module control register r-x r-x r-x r-x r-x r-x r-x r-x ? ? ? ? ? ? ? ? bit 31 bit 24 r-x r-x r-x r-x r-x r-x r-x r-x ? ? ? ? ? ? ? ? bit 23 bit 16 r-x r-x r-x r-x r-x r-x r-x r-x ? ? ? ? ? ? ? ? bit 15 bit 8 r-x r-x r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 jstate se0 pktdis (4) usbrst hosten resume ppbrst usben (4) tokbusy (5) sofen (5) bit 7 bit 0 legend: r = readable bit w = writable bit p = programmable bit r = reserved bit u = unimplemented bit -n = bit value at por: (?0?, ?1?, x = unknown) bit 31-8 reserved: write ? 0 ?; ignore read bit 7 jstate: live differential receiver jstate flag bit 1 = jstate detected on the usb 0 = no jstate detected bit 6 se0: live single-ended zero flag bit 1 = single-ended zero detected on the usb 0 = no single-ended zero detected bit 5 pktdis: packet transfer disable bit (device mode) 1 = token and packet processing disabled (set upon setup token received) 0 = token and packet processing enabled tokbusy: token busy indicator bit (1) (host mode) 1 = token being executed by the usb module 0 = no token being executed bit 4 usbrst: module reset bit (host mode only) 1 = usb reset generated 0 = usb reset terminated bit 3 hosten: host mode enable bit (2) 1 = usb host capability enabled 0 = usb host capability disabled bit 2 resume: resume signaling enable bit (3) 1 = resume signaling activated 0 = resume signaling disabled bit 1 ppbrst: ping-pong buffers reset bit 1 = reset all even/odd buffer pointers to the even bd banks 0 = even/odd buffer pointers not being reset
pic32mx3xx/4xx ds61143e-page 266 preliminary ? 2008 microchip technology inc. bit 0 usben: usb module enable bit (device mode) 1 = usb module and supporting circuitry enabled 0 = usb module and supporting circuitry disabled sofen: sof enable bit (host mode) 1 = sof token sent every 1 ms 0 = sof token disabled note 1: software is required to check this bit before issuing another token command to the u1tok register, see register 11-15. 2: all host control logic is reset any time that the value of this bit is toggled. 3: software must set resume for 10 ms if the part is a function, or for 25 ms if the part is a host, and then clear it to enable remote wake-up. in host mode, the usb module will append a low-speed eop to the resume signaling when this bit is cleared. 4: device mode. 5: host mode. register 11-11: u1con: usb modu le control register (continued)
? 2008 microchip technology inc. preliminary ds61143e-page 267 pic32mx3xx/4xx register 11-12: u1addr: usb address register r-x r-x r-x r-x r-x r-x r-x r-x ? ? ? ? ? ? ? ? bit 31 bit 24 r-x r-x r-x r-x r-x r-x r-x r-x ? ? ? ? ? ? ? ? bit 23 bit 16 r-x r-x r-x r-x r-x r-x r-x r-x ? ? ? ? ? ? ? ? bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 lspden devaddr<6:0> bit 7 bit 0 legend: r = readable bit w = writable bit p = programmable bit r = reserved bit u = unimplemented bit -n = bit value at por: (?0?, ?1?, x = unknown) bit 31-8 reserved: write ? 0 ?; ignore read bit 7 lspden: low-speed enable indicator bit 1 = next token command to be executed at low speed 0 = next token command to be executed at full speed bit 6-0 devaddr<6:0>: 7-bit usb device address bits
pic32mx3xx/4xx ds61143e-page 268 preliminary ? 2008 microchip technology inc. register 11-13: u1frml: usb frame count low register r-x r-x r-x r-x r-x r-x r-x r-x ? ? ? ? ? ? ? ? bit 31 bit 24 r-x r-x r-x r-x r-x r-x r-x r-x ? ? ? ? ? ? ? ? bit 23 bit 16 r-x r-x r-x r-x r-x r-x r-x r-x ? ? ? ? ? ? ? ? bit 15 bit 8 r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 frml<7:0> bit 7 bit 0 legend: r = readable bit w = writable bit p = programmable bit r = reserved bit u = unimplemented bit -n = bit value at por: (?0?, ?1?, x = unknown) bit 31-8 reserved: write ? 0 ?; ignore read bit 7-0 frml<7:0>: the 11-bit frame number lower bits the register bits are updated with the current frame number whenever a sof token is received.
? 2008 microchip technology inc. preliminary ds61143e-page 269 pic32mx3xx/4xx register 11-14: u1frmh: usb frame count high register r-x r-x r-x r-x r-x r-x r-x r-x ? ? ? ? ? ? ? ? bit 31 bit 24 r-x r-x r-x r-x r-x r-x r-x r-x ? ? ? ? ? ? ? ? bit 23 bit 16 r-x r-x r-x r-x r-x r-x r-x r-x ? ? ? ? ? ? ? ? bit 15 bit 8 r-x r-x r-x r-x r-x r-0 r-0 r-0 ? ? ? ? ?frmh<2:0> bit 7 bit 0 legend: r = readable bit w = writable bit p = programmable bit r = reserved bit u = unimplemented bit -n = bit value at por: (?0?, ?1?, x = unknown) bit 31-3 reserved: write ? 0 ?; ignore read bit 2-0 frmh<2:0>: the upper 3 bits of the frame numbers the register bits are updated with the current frame number whenever a sof token is received.
pic32mx3xx/4xx ds61143e-page 270 preliminary ? 2008 microchip technology inc. register 11-15: u1tok: usb host control register r-x r-x r-x r-x r-x r-x r-x r-x ? ? ? ? ? ? ? ? bit 31 bit 24 r-x r-x r-x r-x r-x r-x r-x r-x ? ? ? ? ? ? ? ? bit 23 bit 16 r-x r-x r-x r-x r-x r-x r-x r-x ? ? ? ? ? ? ? ? bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 pid<3:0> ep<3:0> bit 7 bit 0 legend: r = readable bit w = writable bit p = programmable bit r = reserved bit u = unimplemented bit -n = bit value at por: (?0?, ?1?, x = unknown) bit 31-8 reserved: write ? 0 ?; ignore read bit 7-4 pid<3:0>: token type indicator bits (1) 0001 = out (tx) token type transaction 1001 = in (rx) token type transaction 1101 = setup (tx) token type transaction bit 3-0 ep<3:0>: token command endpoint address bits the four-bit value must specify a valid endpoint. note 1: all other values are reserved and must not be used.
? 2008 microchip technology inc. preliminary ds61143e-page 271 pic32mx3xx/4xx register 11-16: u1sof: usb sof counter register r-x r-x r-x r-x r-x r-x r-x r-x ? ? ? ? ? ? ? ? bit 31 bit 24 r-x r-x r-x r-x r-x r-x r-x r-x ? ? ? ? ? ? ? ? bit 23 bit 16 r-x r-x r-x r-x r-x r-x r-x r-x ? ? ? ? ? ? ? ? bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r-x cnt<7:0> bit 7 bit 0 legend: r = readable bit w = writable bit p = programmable bit r = reserved bit u = unimplemented bit -n = bit value at por: (?0?, ?1?, x = unknown) bit 31-8 reserved: write ? 0 ?; ignore read bit 7-0 cnt<7:0>: sof threshold value bits typical values of the threshold are: 0100 1010 = 64-byte packet 0010 1010 = 32-byte packet 0001 1010 = 16-byte packet 0001 0010 = 8-byte packet
pic32mx3xx/4xx ds61143e-page 272 preliminary ? 2008 microchip technology inc. register 11-17: u1bdtp1: usb bdt register r-x r-x r-x r-x r-x r-x r-x r-x ? ? ? ? ? ? ? ? bit 31 bit 24 r-x r-x r-x r-x r-x r-x r-x r-x ? ? ? ? ? ? ? ? bit 23 bit 16 r-x r-x r-x r-x r-x r-x r-x r-x ? ? ? ? ? ? ? ? bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r-x bdtptrl<6:0> ? bit 7 bit 0 legend: r = readable bit w = writable bit p = programmable bit r = reserved bit u = unimplemented bit -n = bit value at por: (?0?, ?1?, x = unknown) bit 31-8 reserved: write ? 0 ?; ignore read bit 7-1 bdtptrl<6:0>: bdt base address bits this 7-bit value provides address bits 15 through 9 of the bdt base address, which defines the bdt?s starting location in the system memory. the 32-bit bdt base address is 512-byte aligned. bit 0 reserved: write ? 0 ?; ignore read
? 2008 microchip technology inc. preliminary ds61143e-page 273 pic32mx3xx/4xx register 11-18: u1bdtp2: usb bdt page 2 register r-x r-x r-x r-x r-x r-x r-x r-x ? ? ? ? ? ? ? ? bit 31 bit 24 r-x r-x r-x r-x r-x r-x r-x r-x ? ? ? ? ? ? ? ? bit 23 bit 16 r-x r-x r-x r-x r-x r-x r-x r-x ? ? ? ? ? ? ? ? bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 bdtptrh<7:0> bit 7 bit 0 legend: r = readable bit w = writable bit p = programmable bit r = reserved bit u = unimplemented bit -n = bit value at por: (?0?, ?1?, x = unknown) bit 31-8 reserved: write ? 0 ?; ignore read bit 7-0 bdtptrh<7:30>: bdt base address bits this 8-bit value provides address bits 23 through 16 of the bdt base address, which defines the bdt?s starting location in the system memory. the 32-bit bdt base address is 512-byte aligned.
pic32mx3xx/4xx ds61143e-page 274 preliminary ? 2008 microchip technology inc. register 11-19: u1bdtp3: usb bdt page 3 register r-x r-x r-x r-x r-x r-x r-x r-x ? ? ? ? ? ? ? ? bit 31 bit 24 r-x r-x r-x r-x r-x r-x r-x r-x ? ? ? ? ? ? ? ? bit 23 bit 16 r-x r-x r-x r-x r-x r-x r-x r-x ? ? ? ? ? ? ? ? bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 bdtptru<7:0> bit 7 bit 0 legend: r = readable bit w = writable bit p = programmable bit r = reserved bit u = unimplemented bit -n = bit value at por: (?0?, ?1?, x = unknown) bit 31-8 reserved: write ? 0 ?; ignore read bit 7-0 bdtptru<7:0>: bdt base address bits this 8-bit value provides address bits 31 through 24 of the bdt base address, which defines the bdt?s starting location in the system memory. the 32-bit bdt base address is 512-byte aligned.
? 2008 microchip technology inc. preliminary ds61143e-page 275 pic32mx3xx/4xx register 11-20: u1cnfg1: usb debug and idle register r-x r-x r-x r-x r-x r-x r-x r-x ? ? ? ? ? ? ? ? bit 31 bit 24 r-x r-x r-x r-x r-x r-x r-x r-x ? ? ? ? ? ? ? ? bit 23 bit 16 r-x r-x r-x r-x r-x r-x r-x r-x ? ? ? ? ? ? ? ? bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r-x r-x r-x r-x uteye uoemon usbfrz usbsidl ? ? ? ? bit 7 bit 0 legend: r = readable bit w = writable bit p = programmable bit r = reserved bit u = unimplemented bit -n = bit value at por: (?0?, ?1?, x = unknown) bit 31-8 reserved: write ? 0 ?; ignore read bit 7 uteye: usb eye-pattern test enable bit 1 = eye-pattern test enabled 0 = eye-pattern test disabled bit 6 uoemon: usb oe monitor enable bit 1 = oe signal active; it indicates intervals during which the d+/d- lines are driving 0 = oe signal inactive bit 5 usbfrz: freeze in debug mode bit 1 = when emulator is in debug mode, module freezes operation 0 = when emulator is in debug mode, module continues operation note: usbfrz is writable in debug exception mode only, it is forced to ? 0 ? in normal mode. bit 4 usbsidl: stop in idle mode bit 1 = discontinue module operation when device enters idle mode 0 = continue module operation in idle mode bit 3-0 reserved: write ? 0 ?; ignore read
pic32mx3xx/4xx ds61143e-page 276 preliminary ? 2008 microchip technology inc. register 11-21: u1ep0-u1ep15: usb endpoint control register r-x r-x r-x r-x r-x r-x r-x r-x ? ? ? ? ? ? ? ? bit 31 bit 24 r-x r-x r-x r-x r-x r-x r-x r-x ? ? ? ? ? ? ? ? bit 23 bit 16 r-x r-x r-x r-x r-x r-x r-x r-x ? ? ? ? ? ? ? ? bit 15 bit 8 r/w-0 r/w-0 r-x r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 lspd retrydis ? epcondis eprxen eptxen epstall ephshk bit 7 bit 0 legend: r = readable bit w = writable bit p = programmable bit r = reserved bit u = unimplemented bit -n = bit value at por: (?0?, ?1?, x = unknown) bit 31-8 reserved: write ? 0 ?; ignore read bit 7 lspd: low-speed direct connection enable bit (host mode and u1ep0 only) 1 = direct connection to a low-speed device enabled 0 = direct connection to a low-speed device disabled; hub required with pre_pid bit 6 retrydis: retry disable bit (host mode and u1ep0 only) 1 = retry nak?d transactions disabled 0 = retry nak?d transactions enabled; retry done in hardware bit 5 reserved: write ? 0 ?; ignore read bit 4 epcondis: bidirectional endpoint control bit if eptxen = 1 and eprxen = 1 : 1 = disable endpoint n from control transfers; only tx and rx transfers allowed 0 = enable endpoint n for control (setup) transfers; tx and rx transfers also allowed otherwise, this bit is ignored. bit 3 eprxen: endpoint receive enable bit 1 = endpoint n receive enabled 0 = endpoint n receive disabled bit 2 eptxen: endpoint transmit enable bit 1 = endpoint n transmit enabled 0 = endpoint n transmit disabled bit 1 epstall: endpoint stall status bit 1 = endpoint n was stalled 0 = endpoint n was not stalled bit 0 ephshk: endpoint handshake enable bit 1 = endpoint handshake enabled 0 = endpoint handshake disabled (typically used for isochronous endpoints)
? 2008 microchip technology inc. preliminary ds61143e-page 277 pic32mx3xx/4xx register 11-22: iec1: interrupt enable control register 1 (1) r-x r-x r-x r-x r-x r-x r/w-0 r/w-0 ? ? ? ? ? ? usbie fceie bit 31 bit 24 rrrrr/w-0r/w-0r/w-0r/w-0 ? ? ? ? dma3ie dma2ie dma1ie dma0ie bit 23 bit 16 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 rtccie fscmie i2c2mie i2c2sie i2c2bie u2txie u2rxie u2eie bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 spi2rxie spi2txie spi2eie cmp2ie cmp1ie pmpie ad1ie cnie bit 7 bit 0 legend: r = readable bit w = writable bit p = programmable bit r = reserved bit u = unimplemented bit -n = bit value at por: (?0?, ?1?, x = unknown) bit 31-26 reserved: write ? 0 ?; ignore read bit 25 usbie: usb interrupt enable bit 1 = interrupt is enabled 0 = interrupt is disabled bit 24-0 reserved: write ? 0 ?; ignore read note 1: register is cleared on all forms of reset. shaded bit names in this interrupt register control other pic32mx3xx/4xx peripherals and are not related to usb.
pic32mx3xx/4xx ds61143e-page 278 preliminary ? 2008 microchip technology inc. 11.2 operation this section contains a brief overview of usb opera- tion, followed by pic32mx usb module implementa- tion specifics, and module initialization requirements. 11.3 usb 2.0 operation overview usb is an asynchronous serial interface with a tiered star configuration. usb is implemented as a mas- ter/slave configuration. on a given bus, there can be multiple (up to 127) slaves (devices), but there is only one master (host). there are three possible module modes of operation: host, device, and otg dual role. 11.4 modes of operation the following usb implementation modes are described in this overview: ? host mode - usb standard host mode ? the usb imple- mentation that is typically used for a personal computer - embedded host mode ? the usb implemen- tation that is typically used for a microcontroller ? device mode ? the usb implementation that is typically used for a peripheral such as a thumb- drive, keyboard, or mouse ? otg dual role mode ? the usb implementation in which an application may dynamically switch its role as either host or device 11.4.1 host mode the host is the master in a usb system and is respon- sible for identifying all devices connected to it (enumer- ation), initiating all transfers, allocating bus bandwidth and supplying power to any bus-powered usb devices connected directly to it. 11.4.1.1 usb standard host in usb standard host mode, the following features and requirements are relevant: ? large variety of devices are supported ? supports all usb transfer types ? usb hubs are supported (allows connection of multiple devices simultaneously) ? device drivers can be updated to support new devices ? type ?a? receptacle is used for each port ? each port must be able to deliver a minimum of 100 ma for a configured or unconfigured device, and optionally, up to 500 ma for a configured device ? full-speed and low-speed protocols must be sup- ported (high-speed can be supported). 11.4.1.2 embedded host in embedded host mode, the following features and requirements are relevant: ? only supports a specific list of devices, referred to as a targeted peripheral list (tpl) ? only required to support those transfer types that are required by devices in the tpl ? usb hub support is optional ? device drivers are not required to be updateable ? type ?a? receptacle is used for each port ? only those speeds required by devices in the tlp must be supported ? each port must be able to deliver a minimum of 100 ma for a configured or unconfigured device, and optionally, up to 500 ma for a configured device 11.4.2 device mode usb devices accept commands and data from the host and respond to requests for data. usb devices perform peripheral functions, e.g., a mouse or other i/o, or data storage. the following characteristics generally describe a usb device: ? functionality may be class- or vendor-specific ? draws 100 ma or less from the bus before config- uration ? can draw up to 500 ma from the bus after suc- cessful negotiation with the host ? can support low-speed, full-speed, or high-speed protocol (high-speed support requires implemen- tation of full-speed protocol to enumerate) ? supports control and data transfers as required for implementation note: a good understanding of usb can be gained from documents that are available on the usb implementers web site. in par- ticular, refer to the ? universal serial bus specification, revision 2.0? (http://www.usb.org/developers/docs/). note: this mode is not supported by the pic32mx family.
? 2008 microchip technology inc. preliminary ds61143e-page 279 pic32mx3xx/4xx ? optionally supports session request protocol (srp) ? can be bus-powered or self-powered 11.4.3 otg dual role the otg dual role device supports both usb host and device functionality. otg dual role devices use a micro-ab receptacle. this allows a micro-a or a micro- b plug to be attached. both the micro-a and micro-b plugs have an additional pin, the id pin, to signify which plug type was connected. the plug type connected to the receptacle, micro-a or micro-b, determines the default role of the otg device, host or device. an otg device will perform the role of a host when a micro-a plug is detected. when a micro-b plug is detected, the role of a usb device is performed. when an otg device is directly connected to another otg device using an otg cable (micro-a to micro-b), host negotiation protocol (hnp) can be used to swap the roles of host and usb device between the two with- out disconnecting and reconnecting the cable. to differ- entiate between the two otg devices, the term ?a- device? refers to the device connected to the micro-a plug and ?b-device? refers to the device connected to the micro-b plug. 11.4.3.1 a-device, the default host in otg dual role, operating as a host, the following fea- tures and requirements describe an a-device: ? supports the devices on the tpl (class support is not allowed) ? required to support those transaction types that are required by devices in the tpl ? usb hub support is optional ? device drivers are not required to be updateable ? a single micro-ab receptacle is used ? full-speed protocol must be supported (high- speed and/or low-speed protocol can be supported) ? usb port must be able to deliver a minimum of 8 ma for a configured or unconfigured device, and optionally, up to 500 ma for a configured device ? supports hnp; the host can switch roles to become a device ? supports at least one form of srp ? a-device supplies v bus power when the bus is powered, even if the roles are swapped using hnp 11.4.3.2 b-device, the default device in otg dual role, operating as a usb device, the fol- lowing features and requirements describe a b-device: ? class- or vendor-specific functionality ? draws 8 ma or less before configuration ? is typically self-powered, due to low-current requirements, but can draw up to 500 ma after successful negotiation with the host ? a single micro-ab receptacle is used ? must support full-speed protocol (support of low- speed and/or high-speed protocol is optional ? supports control transfers, and supports data transfers as they are required for implementation ? supports both forms of srp ? v bus pulsing and data-line pulsing ? supports hnp b-device does not supply v bus power, even if the roles are swapped using hnp. ? 11.4.4 physical bus interface 11.4.4.1 bus speed selection the usb specification defines full-speed operation as 12 mb/s and low speed operation as 1.5 mb/s. a data line pull-up resistor is used to identify a device as full speed or low speed. for full-speed operation, the d+ line is pulled up; for low-speed operation, the d- line is pulled up. 11.4.4.2 v bus control v bus is the 5v usb power supplied by the host or a hub to operate bus-powered devices. the need for v bus control depends on the role of the application. if v bus power must be enabled and disabled, the control must be managed by firmware. the following list details the v bus requirements: ? standard host typically supplies power to the bus at all times. ? host may switch off v bus to conserve power ? usb device never powers the bus ? v bus pulsing may be supported as part of the srp. ? otg a-device supplies power to the bus, and typically turns off v bus to conserve power. ? otg b-device can pulse v bus for srp. note: dual role devices that do not support full otg functionality are possible using mul- tiple usb receptacles. however, there may be special requirements if those devices are to be made usb compliant. refer to the usb implementer?s forum for the most current details. note: refer to the specific device data sheet for v bus electrical parameters.
pic32mx3xx/4xx ds61143e-page 280 preliminary ? 2008 microchip technology inc. 11.5 pic32mx implementation specifics this section details how the usb specification require- ments are implemented in the pic32mx usb module. 11.5.1 bus speed the pic32mx usb module supports the following speeds: ? full-speed operation as a host and a device ? low-speed operation as a host 11.5.2 endpoints and descriptors all usb endpoints are implemented as buffers in ram. the cpu and usb module have access to the buffers. to arbitrate access to these buffers between the usb module and cpu, a semaphore flag system is used. each endpoint can be configured for tx and/or rx, and each has an odd and an even buffer. use of the buffer descriptor table (bdt) allows the buf- fers to be located anywhere in ram, and provides sta- tus flags and control bits. the bdt contains the address of each endpoint data buffer, as well as infor- mation about each buffer (see figure 11-2, figure 11-3 and figure 11-4). each bdt entry is called a buffer descriptor (bd) and is 8 bytes long. all endpoints, rang- ing from endpoint 0 to the highest endpoint in use, must have four descriptor entries. even if all of the buffers for an endpoint are not used, four descriptors entries are required for each endpoint. the usb module calculates a buffer?s location in ram using the bdt. the base of the bdt is held in registers u1bdtp1 through u1bdtp3. the address of the desired buffer is found by using the endpoint number, the type (rx/tx) and the odd/even bit to index into the bdt. the address held by this entry is the address of the desired data buffer. refer to section 11.4.3.1 ?a-device, the default host? . each of the 16 endpoints owns two descriptor pairs: two for packets to transmit, and two for packets received. each pair manages two buffers, an even and an odd, requiring a maximum of 64 descriptors (16 * 2 * 2). having even and odd buffers for each direction allows the cpu to access data in one buffer while the usb module transfers data to or from the other buffer. the usb module alternates between buffers, clearing the uown bit in the buffer descriptor automatically when the transaction for that buffer is complete (see section 11.4.3 ?otg dual role? ). the use of alternat- ing buffers maximizes data throughput by allowing cpu data access in parallel with data transfer. this technique is referred to as ping-pong buffering. figure 11-2 illustrates how the endpoints are mapped in the bdt. 11.5.2.1 endpoint control each endpoint is controlled by an endpoint control reg- ister, u1epn, that configures the transfer direction, the handshake, and the stalling properties of the endpoint. the endpoint control register also allows support of control transfers. 11.5.2.2 host endpoints the host performs all transactions through a single endpoint (endpoint 0). all other endpoints should be disabled and other endpoint buffers are not be used. 11.5.2.3 device endpoints endpoint 0 must be implemented for a usb device to be enumerated and controlled. devices typically imple- ment additional endpoints to transfer data. 11.5.3 buffer management the buffers are shared between the pic32mx and the usb module, and are implemented in system memory. so, a simple semaphore mechanism is used to distin- guish current ownership of the bd, and associated buf- fers, in memory. this semaphore mechanism is implemented by the uown bit in each bd. the usb module clears the uown bit automatically when the transaction for that buffer is complete. when the uown bit is clear, the descriptor is owned by the pic32mx ? which may modify the descriptor and buffer as necessary. software must configure the bdt entry for the next transaction, then set the uown bit to return control to the usb module. a bd is only valid if the corresponding endpoint has been enabled in the u1epn register. the bdt is imple- mented in data memory, and the bds are not modified when the usb module is reset. initialize the bds prior to enabling them through the u1epn. at a minimum, the uown bits must be cleared prior to being enabled. in host mode, bdt initialization is required before the u1tok register is written, triggering a transfer. note: the contents of the u1bdtp1-u1bdtp3 registers provide the upper 23 bits of the 32-bit address; therefore, the btd must be aligned to a 512-byte boundary (see figure 11-2). this address must be the physical (not virtual) memory address. note: in host mode, endpoint 0 has additional bits for auto-retry and hub support.
? 2008 microchip technology inc. preliminary ds61143e-page 281 pic32mx3xx/4xx figure 11-2: bdt address generation bdtba<22:0> endpoint<3:0> dir ppbi fsotg 31:9 8:5 4 3 2:0 bit 31:9 bdtba<22:0>: bdt base address bits the 23-bit value is made up of the contents of the u1bdtp3, u1bdtp2, and u1bdtp1 registers. bit 8:5 endpoint<3:0>: transfer endpoint number bits 0000 = endpoint 0 0001 = endpoint 1 .... 1110 = endpoint 14 1111 = endpoint 15 bit 4 dir: transfer direction bit 1 = transmit: setup/out for host, in for function 0 = receive: in for host, setup/out for function bit 3 ppbi: ping-pong pointer bit 1 = odd buffer 0 = even buffer bit 2:0 manipulated by the usb module
pic32mx3xx/4xx ds61143e-page 282 preliminary ? 2008 microchip technology inc. 11.5.3.1 buffer descriptor format the buffer descriptor is used in the following formats: ?control ? status. buffer descriptor control format, in which software writes the descriptor and hands it to hardware, is shown in figure 11-3. buffer descriptor status format, in which hardware writes the descriptor and hands it back to software, is shown in figure 11-4. figure 11-3: usb buffer descriptor format: software hardware address offset +0 31 2625 1615 876543210 ? byte count<9:0> ? uown data0/1 keep ninc dts bstall ? address offset +4 31 0 buffer address<31:0> address offset +0 bit 25-16 byte_count<9:0>: byte count bits byte count represents the number of bytes to be transmitted or the maximum number of bytes to be received during a transfer. bit 7 uown: usb own bit 1 = usb module owns the bd and its corresponding buffer cpu must not modify the bd or the buffer. 0 = cpu owns the bd and its corresponding buffer usb module ignores all other fields in the bd. usbfrz is writable in debug exception mode only, it is forced to ? 0 ? in normal mode. note: this bit can be programmed by either the cpu or the usb module, and it must be initialized by the user to the desired value prior to enabling the usb module. bit 6 data0/1: data toggle packet bit 1 = transmit a data 1 packet or check received pid = data1, if dts = 1 0 = transmit a data 0 packet or check received pid = data1, if dts = 1 bit 5 keep: bd keep enable bit 1 = usb will keep the bd indefinitely once uown is set u1stat fifo will not be updated and trnif bit will not be set at the end of each transaction. 0 = usb will hand back the bd once a token has been processed bit 4 ninc: dma address increment disable bit 1 = dma address increment disabled 0 = dma address increment enabled bit 3 dts: data toggle synchronization enable bit 1 = data toggle synchronization is enabled ? data packets with incorrect sync value will be ignored 0 = no data toggle synchronization is performed note: expected value of data pid (data0/data1) specified in the data0/1 field.
? 2008 microchip technology inc. preliminary ds61143e-page 283 pic32mx3xx/4xx bit 2 bstall: buffer stall enable bit 1 = buffer stall enabled stall handshake issued if a token is received that would use the bd in the given location (uown bit remains set, bd value is unchanged). corresponding epstall bit will get set on any stall handshake. 0 = buffer stall disabled address offset +4 bit 31-0 buffer_address: buffer address bits (3) starting point address of the endpoint packet data buffer. note: the individual buffer addresses in the bdt must be physical memory addresses.
pic32mx3xx/4xx ds61143e-page 284 preliminary ? 2008 microchip technology inc. figure 11-4: usb buffer de scriptor format: hardware software address offset +0 31 2625 1615 876543210 ? byte count<9:0> ? uown data0/1 pid<3:0> ? address offset +4 31 0 buffer address<31:0> address offset +0 bit 25-16 byte_count<9:0>: byte count bits byte count reflects the actual number of bytes received or transmitted. bit 7 uown: usb own bit 1 = usb module owns the bd and its corresponding buffer cpu must not modify the bd or the buffer. 0 = cpu owns the bd and its corresponding buffer note: this bit can be programmed by either the cpu or the usb module, and it must be initialized by the user to the desired value prior to enabling the usb module. bit 6 data0/1: data toggle packet bit 1 = data 1 packet received 0 = data 0 packet received note: this bit is unchanged on an outgoing packet. bit 5-2 pid<3:0>: packet identifier bits the current token pid when a transfer completes. the values written back are the token pid values from the usb specification: 0x1 for an out token, 0x9 for an in token or 0xd for a setup token. in host mode, this field is used to report the last returned pid or a transfer status indication. the possible values returned are: 0x3 data0, 0xb data1, 0x2 ack, 0xe stall, 0xa nak, 0x0 bus time-out, 0xf data error. address offset +4 bit 31-0 buffer_address: buffer address bits starting point address of the endpoint packet data buffer.
? 2008 microchip technology inc. preliminary ds61143e-page 285 pic32mx3xx/4xx figure 11-5: buffer management overview u1bdtp1:3 pointer bdt located in ram* ep0 rx even descriptor ep0 rx odd descriptor ep0 tx even descriptor ep0 tx odd descriptor ep1 rx even descriptor ep1 rx odd descriptor ep1 tx even descriptor ep1 tx odd descriptor ep2 rx even descriptor ep2 rx odd descriptor ep2 tx even descriptor ep2 tx odd descriptor ... ep15 tx odd descriptor *512 byte aligned transfer buffers located in ram ep0 rx even buffer ep0 rx odd buffer ep0 tx even buffer ep0 tx odd buffer ep1 rx even buffer ep1 rx odd buffer ep1 tx even buffer ep1 tx odd buffer ep2 rx even buffer ep2 rx odd buffer ep2 tx even buffer ep2 tx odd buffer ... ep15 tx odd buffer
pic32mx3xx/4xx ds61143e-page 286 preliminary ? 2008 microchip technology inc. 11.5.4 buffer descriptor configuration the uown, dtsen and bstall bits in each bdt entry control the data transfer for the associated buffer and endpoint. setting the dtsen bit enables the usb module to per- form data toggle synchronization. when dts is enabled: if a packet arrives with an incorrect dts, it will be ignored, the buffer remains unchanged, and the packet will be nak?d (negatively acknowledged). setting the bstall bit causes the usb to issue a stall handshake if a token is received by the sie that would use the bd in this location ? the corresponding epstall bit is set and a stallif interrupt is gener- ated. when the bstall bit is set, the bd is not con- sumed by the usb module (the uown bit remains set and the rest of the bd values are unchanged). if a setup token is sent to the stalled endpoint, the mod- ule automatically clears the corresponding bstall bit. the byte count represents the total number of bytes that are transmitted or received. valid byte counts range from 0 to 1023. for all endpoint transfers, the byte count is updated by the usb module, with the actual number of bytes transmitted or received, after the transfer is completed. if the number of bytes received exceeds the corresponding byte count value written by the firmware, the overflow bit is set and the data is truncated to fit the size of the buffer (as given in the btd). 11.6 hardware interface 11.6.1 power supply requirements power supply requirements for usb implementation vary with the type of application, and are outlined below. ? device: operation as a device requires a power supply for the pic32mx and the usb transceiver, see figure 11-6 for an overview of usb implementa- tion as a device. ? embedded host: operation as a host requires a power supply for the pic32mx, the usb transceiver, and a 5v nominal supply for the usb v bus . the power supply must be able to deliver 100 ma, or up to 500 ma, depending on the requirements of the devices in the tpl. the application dictates whether the v bus power supply can be disabled or disconnected from the bus by the pic32mx application. figure 11-7 presents an overview of usb implementation as a host. ? otg dual role: operation as an otg dual role requires a power supply for the pic32mx, the usb transceiver, and a switchable 5v nominal supply for the usb v bus . an overview of usb implementation as otg is presented in figure 11-8. when acting as an a-device, power must be supplied to v bus . the power supply must be able to deliver 8 ma, 100 ma, or up to 500 ma, depending on the requirements of the devices in the tpl. when acting as a b-device, power must not be supplied to v bus . v bus pulsing can be per- formed by the usb module or by a capable power supply. 11.6.2 v bus regulator interface the vbuson output can be used to control an off-chip 5v v bus regulator. the vbuson pin is controlled by the vbuson bit (u1otgcon<3>). vbuson appears in figure 11-7 and figure 11-8.
? 2008 microchip technology inc. preliminary ds61143e-page 287 pic32mx3xx/4xx figure 11-6: overview of usb implementation as a device v usb d+ d- v bus usb module usb type ?b? connector 3 2 1 4 3.3v
pic32mx3xx/4xx ds61143e-page 288 preliminary ? 2008 microchip technology inc. figure 11-7: overview of usb implementation as a host v usb d+ d- v bus usb module external power usb type ?a? connector 3 2 1 4 vbuson 5v 3.3v
? 2008 microchip technology inc. preliminary ds61143e-page 289 pic32mx3xx/4xx figure 11-8: overview of usb impl ementation for otg (dual role) v usb d+ d- v bus usb module external power 3 2 1 5 vbuson 5v srp source srp discharge 4 id 3.3v usb type micro ?ab? connector
pic32mx3xx/4xx ds61143e-page 290 preliminary ? 2008 microchip technology inc. 11.7 module initialization this section describes the steps that must be taken to properly initialize the otg usb module. 11.7.1 enabling the usb hardware in order to use the usb peripheral, software must set the usbpwr bit (u1pwrc<0>) to ? 1 ?. this may be done in start-up boot sequence. usbpwr is used to initiate the following actions: ? start the usb clock ? allow the usb interrupt to be activated ? select usb as the owner of the necessary io pins ? enable the usb transceiver ? enable the usb comparators the usb module and internal registers are reset when usbpwr is cleared. consequently, the appropriate ini- tialization process must be performed whenever the usb module is enabled, as described in the following subsections. otherwise, any configuration packet sent to the usb module will be stalled, by hardware, until the reset is complete. 11.7.2 initializing the bdt all descriptors for a given endpoint and direction must be initialized prior to enabling the endpoint (for that direction). after a reset, all endpoints are disabled and start with the even buffer for transmit and receive directions. transmit descriptors must be written with the uown bit cleared to ? 0 ? (owned by software). all other transmit descriptor setup may be performed anytime prior to setting the uown bit to ? 1 ?. receive descriptors must be fully initialized to receive data. this means that memory must be reserved for received packet data. the pointer to that memory (physical address), and the size reserved in bytes, must be written to the descriptor. the receive descrip- tor uown bit should be initialized to ? 1 ? (owned by hardware). the dts and stall bits should also be configured appropriately. if a transaction is received and the descriptor?s uown bit is ? 0 ? (owned by software), the usb module returns a nak handshake to the host. usually, this causes the host to retry the transaction. 11.7.3 usb enable/mode bits usb mode of operation is controlled by the following enable bits: otgen (u1otgcon<2>), hosten (u1con<3>), and usben /sofen (u1con<0>). ?otgen: otgen selects whether the pic32mx is to act as an otg part (otgen = 1 ) or not. otg devices support srp and hnp in hardware with firmware management and have direct control over the data-line pull-up and pull-down resis- tors. ?hosten: hosten controls whether the part is acting in the role of usb host (hosten = 1 ) or usb device (hosten = 0 ). note that this role may change dynamically in an otg application. ? usben/sofen: usben controls the connection to usb when the usb module is not configured as a host. if the usb module is configured as a host, sofen controls whether the host is active on the usb link and sends sof tokens every 1 ms. 11.8 device operation all communication on the usb is initiated by the host. therefore, in device mode, when usb is enabled usben = 1 (u1con<0>), endpoint 0 must be ready to receive control transfers. initialization of the remaining endpoints, descriptors, and buffers can be delayed until the host selects a configuration for the device. refer to chapter 9 of the ? universal serial bus specification, revision 2.0 ? for more information on this subject. the following steps are performed to respond to a usb transaction: 1. software pre-initializes the appropriate bds, and sets the uown bits to ? 1 ? to be ready for a transaction. 2. hardware receives a token pid (in, out, setup) from the usb host, and checks the appropriate bd. 3. if the transaction will be transmitted (in), the module reads packet data from data memory. 4. hardware receives a data pid (data0/1), and sends or receives the packet data. 5. if a transaction is received (setup, out), the module writes packet data to data memory. note: the other usb module control registers should be properly initialized before enabling usb via these bits.
? 2008 microchip technology inc. preliminary ds61143e-page 291 pic32mx3xx/4xx 6. the module issues, or waits for, a handshake pid (ack, nak, stall), unless the endpoint is setup as an isochronous endpoint (ephshk bit uepmx<0> is cleared). 7. the module updates the bd, and writes the uown bit to ? 0 ? (sw owned). 8. the module updates the u1stat register, and sets the trnif interrupt. 9. software reads the u1stat register, and deter- mines the endpoint and direction for the transac- tion. 10. software reads the appropriate bd, completes all necessary processing, and clears the trnif interrupt. 11.8.1 receiving an in token in device mode perform the following steps to receive an in token in device mode: 1. attach to a usb host and enumerate as described in chapter 9 of the usb 2.0 specification. 2. populate the data buffer with the data to send to the host. 3. in the appropriate (even or odd) transmit buf- fer descriptor for the desired endpoint: a) set up the control bit field (bdnstat) with the correct data toggle (data0/1) value and the byte count of the data buffer. b) set up the address bit field (bdnadr) with the starting address of the data buffer. c) set the uown bit field to ? 1 ?. 4. when the usb module receives an in token, it automatically transmits the data in the buffer. upon completion, the module updates the sta- tus bit field (bdnstat), clears the uown bit and sets the transfer complete interrupt (u1ir). 11.8.2 receiving an out token in device mode perform the following steps to receive an out token in device mode: 1. attach to a usb host and enumerate as described in chapter 9 of the usb 2.0 specification. 2. create a data buffer with the amount of data you are expecting from the host. 3. in the appropriate (even or odd) transmit buf- fer descriptor for the desired endpoint: a) set up the status bit field (bdnstat) with the correct data toggle (data0/1) value and the byte count of the data buffer. b) set up the address bit field (bdnadr) with the starting address of the data buffer. c) set the uown bit of the status bit field to ? 1 ?. 4. when the usb module receives an out token, it will automatically receive the data the host sent into the buffer. upon completion, the mod- ule updates the status bit field (bdnstat), clears the uown bit and sets the transfer complete interrupt (u1ir). 11.9 host mode operation in host mode, only endpoint 0 is used (all other end- points should be disabled). since the host initiates all transfers, the bd does not require immediate initializa- tion. however, the bds must be configured before a transfer is initiated ? which is done by writing to the u1tok register. the following sections describe how to perform com- mon host mode tasks. in host mode, usb transfers are invoked explicitly by the host software. the host software is responsible for initiating the setup, data, and status stages of all control transfers. the acknowl- edge (ack or nak) is generated automatically by the hardware, based on the crc. host software is also responsible for scheduling packets so that they do not violate usb protocol. all transfers are performed using the endpoint 0 control register (u1ep0) and bds. note: for transmitted (in) transactions (host reading data from the device), the read data must be ready when the host begins usb signaling. otherwise, the usb mod- ule will send a nak handshake if uown is ? 0 ?.
pic32mx3xx/4xx ds61143e-page 292 preliminary ? 2008 microchip technology inc. 11.10 configuring the sof threshold the module counts down the number of bits that could be transmitted within the current usb full-speed frame. since 12,000 bits can be transmitted during the 1 ms frame time, a counter, not visible to software, is loaded with the value ?12,000? at the start of each frame. the counter decrements once for each bit time in the frame. when the counter reaches zero the next frame?s sof packet is transmitted, see figure 11-9. the sof threshold register (u1sof) is used to ensure that no new tokens are started too close to the end of a frame. this prevents a conflict with the next frame?s sof packet. when the counter reaches the threshold value of the u1sof register (the value in the u1sof register is in terms of bytes), no new tokens are started until after the sof has been transmitted. thus, the usb module attempts to ensure that the usb link is idle when the sof token needs to be transmitted. this implies that the value programmed into the u1sof register must reserve enough time to insure the completion of the worst-case transaction. typically, the worst-case transaction is an in token followed by a maximum-sized data packet from the target, followed by the response from the host. if the host is targeting a low-speed device that is bridging through a full-speed hub, the transaction will also include the special pre token packets. figure 11-9: allocation of bits for a full-speed frame table 11-4 and table 11-5 show examples of calculat- ing worst-case bit times. sof sof u1sof * 8 bit times 0 ms 1 ms (12,000 bit times) note: drawing is not to scale. sof threshold 1 full-speed frame note 1: while the u1sof register value is described in terms of bytes, these examples show the result in terms of bits. 2: in the second table, the in, data, and handshake packets are transmitted at low speed (8 times slower than full speed). 3: these calculations do not take the possibility that the packet data needs to be bit-stuffed for nrzi encoding into account. table 11-4: example of sof threshold calculation: full speed packet fields bits in sync, pid, addr, endp, crc5, eop 35 turnaround (1) 8 data sync, pid, data (2) , crc16, eop 547 turnaround 2 handshake sync, pid, eop 19 inter-packet 2 to t a l 613 note 1: inter-packet delay of 2. an additional 5.5 bit times of latency is added to represent a worst-case propaga- tion delay through 5 hubs. 2: using 64-bytes maximum packet size for this example calculation.
? 2008 microchip technology inc. preliminary ds61143e-page 293 pic32mx3xx/4xx table 11-5: example of sof threshold calculation: low speed via hub packet fields bits fs bits pre sync, pid 16 16 hub setup 44 in sync, pid, addr, endp, crc5, eop 35 280 turnaround (1) 88 data sync, pid, data (2) , crc16, eop 99 792 turnaround 22 pre sync, pid 16 16 handshake sync, pid, eop 19 152 inter-packet 22 to t a l 1272 note 1: inter-packet delay of 2. an additional 5.5 bit times of latency is added to represent a worst-case propaga- tion delay through 5 hubs. 2: packets limited to 8-bytes maximum in low-speed mode. note: refer to section 5.11.3 ?calculating bus transaction times? in the usb 2.0 spec- ification for details on calculating bus transaction time.
pic32mx3xx/4xx ds61143e-page 294 preliminary ? 2008 microchip technology inc. 11.11 enabling host mode and discovering a connected device to enable host mode, perform the following steps: 1. enable host mode (u1con = 1 ). this enables the d+ and d- pull-down resistors, and disables the d+ and d- pull-up resistors. to reduce noise on the bus, disable the sof packet generation by writing the sof enable bit to ? 0 ? (u1con = 0 ). 2. enable the device attach interrupt (u1ie = 1 ). 3. wait for the device attach interrupt (u1ir). this is signaled by the usb device changing the state of d+ or d- from ? 0 ? to ? 1 ? (se0 to jstate). after it occurs, wait for the device power to sta- bilize (10 ms is minimum, 100 ms is recom- mended). 4. check the state of the jstate and se0 bits in the control register u1con. if u1con is ? 0 ?, the connecting device is low speed; otherwise, the device is full speed. 5. if the connecting device is low speed, set the low-speed enable bit in the address register (u1addr= 1 ), and the low-speed bit in the endpoint 0 control register (u1ep0 = 1 ). but, if the device is full speed, clear these bits. 6. reset the usb device by sending the reset sig- naling for at least 50 ms (u1con = 1 ). after 50 ms, terminate the reset (u1con = 0 ). 7. enable sof packet generation to keep the con- nected device from going into suspend (u1con = 1 ). 8. wait 10 ms for the device to recover from reset. 9. perform enumeration as described in chapter 9 of the usb 2.0 specification. 11.11.1 host transactions when acting as a host, a transaction consists of the fol- lowing: 1. software configures the appropriate bd (end- point n, dir, ppbi), and sets the uown bit to ? 1 ? (hw owned). 2. software checks the state of tokbusy (u1con<5>) to verify that any previous transaction has completed. 3. software writes the address of the target device in the u1addr register. 4. software writes the endpoint number and the desired token pid (in, out, or setup) to the u1tok register. 5. hardware reads the bd to determine the appro- priate action, and to obtain the pointer to data memory. 6. hardware issues the correct token pid (in, out, setup) on the usb link. 7. if the transaction is a transmit transaction (out, setup), the usb module reads the packet data out of data memory. then the module follows with the desired data pid (data0/data1) and packet data. 8. if the transaction is a receive transaction (in), the usb module waits to receive the data pid and packet data. hardware writes the packet data to memory. 9. hardware issues or waits for a handshake pid (ack, nak, or stall), unless the endpoint is set up as an isochronous endpoint (ephshk bit u1epx<0> is cleared). 10. hardware updates the bd, and writes the uown bit to ? 0 ? (sw owned). 11. hardware updates the u1stat register, and sets the trnif (u1ir<3>) interrupt. 12. hardware reads the next bd (even or odd) to see whether it is owned by the usb module. if it is, hardware begins the next transaction. 13. software should read the u1stat register, and then clear the trnif interrupt. if software does not set the uown bit to ? 1 ? in the appropriate bd prior to writing the u1tok register, the module will read the descriptor and do nothing.
? 2008 microchip technology inc. preliminary ds61143e-page 295 pic32mx3xx/4xx 11.12 completing a control transaction to a connected device complete all of the following steps to discover a con- nected device: 1. set up the endpoint control register for bidirec- tional control transfers, u1ep0<4:0> = 0x0d. 2. place an 8-byte of the device setup packet in the appropriate memory buffer. see chapter 9 of the usb 2.0 specification for information on the device framework command set. 3. initialize the current (even or odd) tx ep0 bd to transfer the 8 byte device framework com- mand (for example, a get device descrip- tor command). a) set the bd status (bd0stat) to 0x8008 ? uown bit set, byte count of 8. b) set the bd data buffer address (bd0adr) to the starting address of the 8-byte memory buffer containing the command, if it is not already initialized. 4. set the usb address of the target device in the address register u1addr<6:0>. after a usb bus reset, the device usb address will be zero. after enumeration, it must be set to another value, between 1 and 127, by the host software. 5. write the token register with a setup command to endpoint 0, the target device?s default control pipe (u1tok = 0xd0). this will initiate a setup token on the bus followed by a data packet. the device handshake will be returned in the pid field of bd0stat after the packets complete. when the module updates bd0stat, a transfer done interrupt will be asserted (u1ir). this completes the setup stage of the setup transfer as described in chapter 9 of the usb specification. 6. to initiate the data stage of the setup transaction (for example, get the data for the get device descriptor command), set up a buffer in memory to store the received data. 7. initialize the current (even or odd) rx or tx (rx for in, tx for out) ep0 bd to transfer the data. a) set the bd status (bd0stat) uown bit to ? 1 ?, data toggle (dts) to data1 and byte count to the length of the data buffer. b) set the bd data buffer address (bd0adr) to the starting address of the data buffer if it is not already initialized. 8. write the token register with the appropriate in or out token to endpoint 0, the target device?s default control pipe) for example, an in token for a get device descriptor command (u1tok = 0x90). this will initiate an in token on the bus followed by a data packet from the device to the host. when the data packet com- pletes, the bd0stat is written and a transfer done interrupt will be asserted (u1ir). for control transfers with a single packet data phase, this completes the data phase of the setup transaction. if more data needs to be transferred, return to step 8. 9. to initiate the status stage of the setup transac- tion, set up a buffer in memory to receive or send the zero length status phase data packet. 10. initialize the current (even or odd) tx ep0 bd to transfer the status data. a) set the bd status (bd0stat) to 0x8000 ? uown bit to ? 1 ?, data toggle (dts) to data0 and byte count to ? 0 ?. b) set the bdt buffer address field to the start address of the data buffer. 11. write the token register with the appropriate in or out token to endpoint 0, the target device?s default control pipe) for example, an out token for a get device descriptor command (u1tok = 0x10). this will initiate a token on the bus, followed by a zero length data packet from the host to the device. when the data packet completes, the bd is updated with the hand- shake from the device, and a transfer done inter- rupt will be asserted (u1ir). this completes the status phase of the setup transaction. note: some devices can only effectively respond to one transaction per frame.
pic32mx3xx/4xx ds61143e-page 296 preliminary ? 2008 microchip technology inc. 11.13 data transfer with a target device complete all of the following steps to discover and con- figure a connected device. 1. write the ep0 control register (u1ep0) to enable transmit and receive transfers as appro- priate with handshaking enabled (unless iso- chronous transfers are to be used). if the target device is a low-speed device, also set the low- speed enable bit (u1ep0). if you want the hardware to automatically retry indefinitely if the target device asserts a nak on the transfer, clear the retry disable bit (u1ep0). 2. set up the current buffer descriptor (even or odd) in the appropriate direction to transfer the desired number of bytes. 3. set the address of the target device in the address register (u1addr<6:0>). 4. write the token register (u1tok) with an in or out token as appropriate for the desired end- point. this triggers the module?s transmit state machines to begin transmitting the token and the data. 5. wait for the transfer done interrupt (u1ir). this will indicate that the bd has been released back to the microprocessor and the transfer has completed. if the retry dis- able bit is set, the handshake (ack, nak, stall or error (0xf)) will be returned in the bd pid field. if a stall interrupt occurs, then the pending packet must be dequeued and the error condition in the target device cleared. if a detach interrupt occurs (se0 for more than 2.5 s), then the target has detached (u1ir). 6. once the transfer done interrupt (u1ir) occurs, the bd can be examined and the next data packet queued by returning to step 2. 11.13.1 usb link states three possible link states are described in the following subsections: ?reset ? idle and suspend ? resume signalling 11.13.1.1 reset as a host, software is required to drive reset signaling. it may do this by setting usbrst (u1con<4>). as per the usb specification, the host must drive the reset for at least 50 ms. (this does not have to be continuous reset signaling. refer to the usb 2.0 specification for more information.) following reset, the host must not initiate any downstream traffic for another 10 ms. as a device, the usb module will assert the urstif (u1ir<0>) interrupt when it has detected reset signal- ing for 2.5 s. software must perform any reset initial- ization processing at this time. this includes setting the address register to 0x00 and enabling endpoint 0. the urstif interrupt will not be set again until the reset signaling has gone away and then has been detected again for 2.5 s. 11.13.1.2 idle and suspend the idle state of the usb is a constant j state. when the usb has been idle for 3 ms, a device should go into suspend state. during active operation, the usb host will send a sof token every 1 ms, preventing a device from going into suspend state. once the usb link is in the suspend state, a usb host or device must drive resume signaling prior to initiating any bus activity. (the usb link may also be discon- nected.) as a usb host, software should consider the link in suspend state as soon as software clears the sofen (u1con<0>). as a usb device, hardware will set the idleif (u1ir<4>) interrupt when it detects a constant idle on the bus for 3 ms. software should consider the link in suspend state when the idleif interrupt is set. once a suspend condition has been detected, the soft- ware may wish to place the usb hardware in a sus- pend mode by setting ususpend (u1pwrc<1>). the hardware suspend mode gates the usb module?s 48 mhz clock and places the usb transceiver in a low- power mode. additionally, the user may put the pic32mx into sleep mode while the link is suspended. 11.13.1.3 driving resume signaling if software wants to wake the usb from suspend state, it may do so by setting resume (u1con<2>). this will cause the hardware to generate the proper resume signaling (including finishing with a low-speed eop if a host). a usb device should not drive resume signaling unless the idle state has persisted for at least 5 ms. the usb host also must have enabled the function for remote wake-up. note: use of automatic indefinite retries can lead to a deadlock condition if the device never responds. note: usb speed, transceiver and pull-ups should only be configured during the mod- ule set-up phase. it is not recommended to change these settings while the module is enabled.
? 2008 microchip technology inc. preliminary ds61143e-page 297 pic32mx3xx/4xx software must set resume for 1-15 ms if a usb device, or >20 ms if a usb host, then clear it to enable remote wake-up. for more information on resume signaling, see section 7.1.7.7, 11.9 and 11.4.4 in the usb 2.0 specification. writing resume will automatically clear the special hardware suspend (low-power) state. if the part is acting as a usb host, software should, at minimum, set the sofen (u1con<0>) after driving its resume signaling. otherwise, the usb link would return right back to the suspend state. also, software must not initiate any downstream traffic for 10 ms following the end of resume signaling. 11.13.1.4 receiving resume signaling when the usb logic detects resume signaling on the usb bus for 2.5 s, hardware will set the resumeif (u1ir<5>) interrupt. a device receiving resume signaling must prepare itself to receive normal usb activity. a host receiving resume signaling must immediately start driving resume signal- ing of its own. the special hardware suspend (low- power) state is automatically cleared upon receiving any activity on the usb link. reception of any activity on the usb link (this may be due to resume signaling or a link disconnect) while the pic32mx is in sleep mode will cause the actvif (u1otgir<4>) interrupt to be set. this will cause wake-up from sleep. 11.13.1.5 srp support srp support is not required by non-otg applications. srp may only be initiated at full speed. refer to the on-the-go supplement specification for more infor- mation regarding srp. an otg a-device or embedded host may decide to power-down the v bus supply when it is not using the usb link. software may do this by clearing vbuson (u1otgcon<3>). when the v bus supply is powered down, the a-device is said to have ended a usb ses- sion. an otg a-device or embedded host may repower the v bus supply at any time to initiate a new session. an otg b-device may also request that the otg a-device repower the v bus supply to initiate a new session. this is the purpose of the srp. prior to requesting a new session, the b-device must first check that the previous session has definitely ended. to do this, the b-device must check that: 1. v bus supply is below the session end voltage. 2. both d+ and d- have been low for at least 2 ms. the b-device will be notified of condition 1 by the ses- endif (u1otgir<2>) interrupt. software can use the lstateif (u1otgir<5>) bit and the 1 ms timer to identify condition 2. the b-device may aid in achieving condition 1 by dis- charging the v bus supply through a resistor. software may do this by setting vbusdis (u1otgcon<0>). the b-device then proceeds by pulsing the d+ data line. software should do this by setting dppulup (u1otgcon<7>). the data line should be held high for 5-10 ms. after these initial conditions are met, the b-device may begin requesting the new session. it begins by pulsing the v bus supply. software should do this by setting vbuschg (u1otgcon<1>). when an a-device detects srp signaling (either via the attachif (u1ir<6>) interrupt or via the sesvdif (u1otgir<3>) interrupt), the a-device must restore the v bus supply by setting vbuson (u1otgcon<3>). the b-device should not monitor the state of the v bus supply while performing v bus supply pulsing. after- wards, if the b-device does detect that the v bus supply has been restored (via the sesvdif (u1otgir<3>) interrupt), it must reconnect to the usb link by pulling up d+. the a-device must complete the srp by enabling v bus and driving reset signalling. 11.13.1.6 hnp an otg application with a micro-ab receptacle must support hnp. hnp allows an otg b-device to tempo- rarily become the usb host. the a-device must first enable hnp in the b-device. hnp may only be initiated at full-speed. refer to the on-the-go supplement for more information regarding hnp. after being enabled for hnp by the a-device, the b-device can request to become the host any time that the usb link is in suspend state by simply indicating a disconnect. software may accomplish this by clearing the dppulup bit (u1otgcon<7>). when the a-device detects the disconnect condition (via the urstif (u1ir<0>) interrupt), the a-device may allow the b-device to take over as host. the a- device does this by signaling connect as a full-speed device. software may accomplish this by disabling host operation, hosten = 0 (u1con<3>), and connecting as a device (dppulup = 1). if the a-device instead responds with resume signaling, the a-device will remain as host. when the b-device detects the connect condition (via attachif (u1ir<6>), the b-device becomes host. the b-device drives reset signaling prior to using the bus. note: when the a-device powers down the v bus supply, the b-device must disconnect its pull-up resistor unless signalling a desire to become host during hnp negotiation. refer to section 11.13.1.6 ?hnp? .
pic32mx3xx/4xx ds61143e-page 298 preliminary ? 2008 microchip technology inc. when the b-device has finished in its role as host, it stops all bus activity and turns on its d+ pull-up resistor by disabling host operations (hosten = 0 ) and recon- necting as a device (dppulup = 1). then the a-device detects a suspend condition (idle for 3 ms), the a-device turns off its d+ pull-up. alternatively the a-device may also power-down the v bus supply to end the session. when the a-device detects the connect condition (via attachif), the a-device resumes host operation, and drives reset signaling. 11.13.2 clock requirements for proper usb operation, the usb module must be clocked with a 48 mhz clock. this clock source is used to generate the timing for usb transfers; it is the clock source for the sie. the control registers are clocked at the same speed as the cpu (refer to figure 11-1). the usb module clock is derived from the primary oscillator (posc) for usb operation. a usb pll and input prescalers are provided to allow 48 mhz clock generation from a wide variety of input frequencies. the usb pll allows the cpu and the usb module to operate at different frequencies while both use the posc as a clock source. to prevent buffer overruns and timing issues, the cpu core must be clocked at a minimum of 16 mhz. the usb module can also use the on-board fast rc oscillator (frc) as a clock source. when using this clock source, the usb module will not meet the usb timing requirements. the frc clock source is intended to allow the usb module to detect a usb wake-up and report it to the interrupt controller when operating in low-power modes. the usb module must be running from the primary oscillator before beginning usb transmissions. 11.14 interrupts the usb module uses interrupts to signal usb events such as a change in status, data received and buffer empty events, to the cpu. software must be able to respond to these interrupts in a timely manner. 11.15 interrupt control each interrupt source in the usb module has an inter- rupt flag bit and a corresponding enable bit. in addition, the uerrif bit (u1ir<1>) is a logical or of all the enabled error flags and is read-only. the uerrif bit can be used to poll the usb module for events while in an interrupt service routine (isr). 11.16 usb module interrupt request generation the usb module can generate interrupt requests from a variety of events. to interface these interrupts to the cpu, the usb interrupts are combined such that any enabled usb interrupt will cause a generic usb inter- rupt (if the usb interrupt is enabled) to the interrupt controller, see figure 11-11. the usb isr must then determine which usb event(s) caused the cpu inter- rupt and service them appropriately. there are two lay- ers of interrupt registers in the usb module. the top level of bits consists of overall usb status interrupts in the u1otgir and u1ir registers. the u1otgir and u1ir bits are individually enabled through the corre- sponding bits in the u1otgie and u1ie registers. in addition, the usb error condition bit (uerrif) passes through any interrupt conditions in the u1eir register enabled via the u1eie register bits. 11.17 interrupt timing interrupts for transfers are generated at the end of the transfer. figure 11-10 shows some typical event sequences that can generate a usb interrupt and when that interrupt is generated. there is no mecha- nism by which software can manually set an interrupt bit. the values in the interrupt enable registers (u1ie, u1eie, u1otgie) only affect the propagation of an interrupt condition to the cpu?s interrupt controller. even though an interrupt is not enabled, interrupt flag bits can still be polled and serviced. 11.18 interrupt servicing once an interrupt bit has been set by the usb module (in u1ir, u1eir or u1otgir), it must be cleared by software by writing a ? 1 ? to the appropriate bit position to clear the interrupt. the usb interrupt, usbif (ifs1<25>), must be cleared before the end of the isr.
? 2008 microchip technology inc. preliminary ds61143e-page 299 pic32mx3xx/4xx figure 11-10: typical events for usb interrupts usb usbrst ack setup token data urstif interrupt generated trnif interrupt generated in token data ack out token data trnif interrupt generated trnif interrupt generated control ack =host = function sof sofif interrupt generated
pic32mx3xx/4xx ds61143e-page 300 preliminary ? 2008 microchip technology inc. figure 11-11: usb interrupt logic dmaef dmaee btoef btoee dfn8ef dfn8ee crc16ef crc16ee crc5ef/eofef crc5ee/eofee pidef pidee attachif attachie resumeif resumeie idleif idleie trnif trnie sofif sofie detachif/urstif detachie/urstie usb interrupt stallif stallie btsef btsee t1msecif t1msecie lstateif lstateie actvif actvie sesvdif sesvdie sesendif sesendie vbusvdif vbusvdie idif idie uerrif uerrie bmxef bmxee
? 2008 microchip technology inc. preliminary ds61143e-page 301 pic32mx3xx/4xx 11.19 i/o pins table 11-6 summarizes the use of pins relating to the usb module. table 11-6: pins associated with the usb module mode pin name module control controlling bit field (1) required tris bit setting pin type description embedded host d+ usben ? ? u data line + d- usben ? ? u data line - v bus usben ? ? p input for usb power, connects to otg comparators vbuson usben vbuson ? d, o output to control supply for v bus (2) v usb ? ? ? p power in for usb transceiver id usben ? ? r reserved device d+ usben ? ? u data line + d- usben ? ? u data line - v bus usben ? ? p input for usb power, connects to otg comparators vbuson ? ? ? r reserved (2) v usb ? ? ? p power in for usb transceiver id ? ? ? r reserved otg d+ usben ? ? u data line + d- usben ? ? u data line - v bus usben vbuschg, vbusdis ? a, i/o, p analog input for usb power, connects to otg comparators vbuson usben vbuschg, vbusdis vbuson ?d, o output to control supply for v bus (2) v usb ? ? ? p power in for usb transceiver id usben ? ? d, i otg mode host/device select input usb disabled d+ usben ? 1 d, i general purpose digital input d- usben ? 1 d, i general purpose digital input v bus usben ? ? r reserved vbuson usben ? 0 d, o general purpose digital input vbuson usben ? 1 d, i general purpose digital output v usb usben ? ? r reserved id usben ? 1 d, i general purpose digital input legend: i = input o = output a = analog d = digital u = usb p = power r = reserved note 1: all pins are subject to the device pin priority control. see the specific device data sheet for further information. 2: when usb is enabled, this pin is controlled by the usb module and therefore is not available as a comparator input.
pic32mx3xx/4xx ds61143e-page 302 preliminary ? 2008 microchip technology inc. id usben ? 0 d, o general purpose digital output table 11-6: pins associated with the usb module (continued) mode pin name module control controlling bit field (1) required tris bit setting pin type description legend: i = input o = output a = analog d = digital u = usb p = power r = reserved note 1: all pins are subject to the device pin priority control. see the specific device data sheet for further information. 2: when usb is enabled, this pin is controlled by the usb module and therefore is not available as a comparator input.
? 2008 microchip technology inc. preliminary ds61143e-page 303 pic32mx3xx/4xx notes:
pic32mx3xx/4xx ds61143e-page 304 preliminary ? 2008 microchip technology inc.
? 2008 microchip technology inc. preliminary ds61143e - page 305 pic32mx3xx/4xx 12.0 i/o ports the general purpose i/o pins can be considered the simplest of peripherals. they allow the pic ? mcu to monitor and control other devices. to add flexibility and functionality, some pins are multiplexed with alternate function(s). these functions depend on which periph- eral features are on the device. in general, when a peripheral is functioning, that pin may not be used as a general purpose i/o pin. following are some of the key features of this module: ? individual output pin open-drain enable/disable ? individual input pin weak pull-up enable/disable ? monitor selective inputs and generate interrupt when change in pin state is detected ? operation during cpu sleep and idle modes ? fast bit manipulation using clr, set and inv registers figure 12-1 shows a block diagram of a typical i/o port, whereas figure 12-2 shows a block diagram of a typical multiplexed i/o port. figure 12-1: block diagram of a typical port structure note: this data sheet summarizes the features of the pic32mx3xx/4xx family of devices. it is not intended to be a comprehensive refer- ence source. refer to the ?pic32mx family reference manual? (ds61132) for a detailed description of this peripheral. wr lat i/o pin wr port data bus rd lat rd port rd tris wr tris i/o cell dedicated port module 0 1 rd odc sys clk q d ck en q q d ck en q q d ck en q q d ck q q d ck q 0 1 synchronization sys clk wr odc odc tris lat sleep
pic32mx3xx/4xx ds61143e - page 306 preliminary ? 2008 microchip technology inc. figure 12-2: block diagram of a typical multiplexed port structure peripheral output data peripheral module peripheral output enable pio module peripheral module enable wr lat io pin wr port data bus rd lat rd port rd tris wr tris 0 1 rd odc sys clk q d ck en q q d ck en q q d ck en q q d ck q q d ck q 0 1 sys clk wr odc odc tris lat sleep 1 0 1 0 output multiplexers io cell synchronization r peripheral input notes: this block diagram is a gener al representation of a shared port/peripher al structure for illustration purposes only. the actual structure for any specific port/peripher al combination may be different than what is shown here. legend: r = peripheral input buffer types may vary. refer to the specific pic32mx3xx/4xx data sheet for peripheral details. peripheral input buffer
? 2008 microchip technology inc. preliminary ds61143e - page 307 pic32mx3xx/4xx 12.1 port registers table 12-1: porta sfr summary virtual address name bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 bf88_6000 trisa 31:24 ? ? ? ? ? ? ? ? 23:16 ? ? ? ? ? ? ? ? 15:8 trisa15 trisa14 ? ? ?trisa10trisa9 ? 7:0 trisa<7:0> bf88_6004 trisaclr 31:0 write clears selected bits in trisa, read yields undefined value bf88_6008 trisaset 31:0 write sets selected bits in trisa, read yields undefined value bf88_600c trisainv 31:0 write inverts selected bits in trisa, read yields undefined value bf88_6010 porta 31:24 ? ? ? ? ? ? ? ? 23:16 ? ? ? ? ? ? ? ? 15:8 ra15 ra14 ? ? ?ra10ra9 ? 7:0 ra<7:0> bf88_6014 portaclr 31:0 write clears selected bits in porta, read yields undefined value bf88_6018 portaset 31:0 write sets selected bits in porta, read yields undefined value bf88_601c portainv 31:0 write inverts selected bits in porta, read yields undefined value bf88_6020 lata 31:24 ? ? ? ? ? ? ? ? 23:16 ? ? ? ? ? ? ? ? 15:8 lata15 lata14 ? ? ? lata10 lata9 ? 7:0 lata<7:0> bf88_6024 lataclr 31:0 write clears selected bits in lata, read yields undefined value bf88_6028 lataset 31:0 write sets selected bits in lata, read yields undefined value bf88_602c latainv 31:0 write inverts selected bits in lata, read yields undefined value bf88_6030 odca 31:24 ? ? ? ? ? ? ? ? 23:16 ? ? ? ? ? ? ? ? 15:8 odca15 odca14 ? ? ? odca10 odca9 ? 7:0 odca<7:0> bf88_6034 odcaclr 31:0 write clears selected bits in odca, read yields undefined value bf88_6038 odcfaset 31:0 write sets selected bits in odca, read yields undefined value bf88_603c odcainv 31:0 write inverts selected bits in odca, read yields undefined value notes: trisa, porta, lata and odca registers are not implemented on 64-pin devices, and read as ? 0 ?. jtag program/debug port is multiplexed with port pins ra 0, ra1, ra4 and ra5 on 100-pin devices. at power-on-reset, these pins are controlled by the jtag port. to use these pi ns for general purpose i/o, the user?s application code must clear jtagen (ddpcon<3>) bit = 0 . to use these pins for jtag program/debug, the user?s application code must maintain jtagen bit = 1. on specific 100-pin devices, the instruction trace port is multiplexed with porta pins ra6, ra7; portg pins rg12, rg13 and rg14. at power-on reset, these pins are general pur pose i/o pins. to maintain these pins as general pur- pose i/o pins, the user?s application code must maintain troen (ddpcon<2>) bit = 0 . to use these pins as instruction trace pins, troen must be set = 1 .
pic32mx3xx/4xx ds61143e - page 308 preliminary ? 2008 microchip technology inc. table 12-2: portb sfr summary virtual address name bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 bf88_6040 trisb 31:24 ? ? ? ? ? ? ? ? 23:16 ? ? ? ? ? ? ? ? 15:8 trisb<15:8> 7:0 trisb<7:0> bf88_6044 trisbclr 31:0 write clears selected bits in trisb, read yields undefined value bf88_6048 trisbset 31:0 write sets selected bits in trisb, read yields undefined value bf88_604c trisbinv 31:0 write inverts selected bits in trisb, read yields undefined value bf88_6050 portb 31:24 ? ? ? ? ? ? ? ? 23:16 ? ? ? ? ? ? ? ? 15:8 rb<15:8> 7:0 rb<7:0> bf88_6054 portbclr 31:0 write clears selected bits in portb, read yields undefined value bf88_6058 portbset 31:0 write sets selected bits in portb, read yields undefined value bf88_605c portbinv 31:0 write inverts selected bits in portb, read yields undefined value bf88_6060 latb 31:24 ? ? ? ? ? ? ? ? 23:16 ? ? ? ? ? ? ? ? 15:8 latb<15:8> 7:0 latb<7:0> bf88_6064 latbclr 31:0 write clears selected bits in latb, read yields undefined value bf88_6068 latbset 31:0 write sets selected bits in latb, read yields undefined value bf88_606c latbinv 31:0 write inverts selected bits in latb, read yields undefined value bf88_6070 odcb 31:24 ? ? ? ? ? ? ? ? 23:16 ? ? ? ? ? ? ? ? 15:8 odcb<15:8> 7:0 odcb<7:0> bf88_6074 odcbclr 31:0 write clears selected bits in odcb, read yields undefined value bf88_6078 odcbset 31:0 write sets selected bits in odcb, read yields undefined value bf88_607c odcbinv 31:0 write inverts selected bits in odcb, read yields undefined value note: jtag program/debug port is multiplexed with port pins rb 10, rb11, rb12 and rb13 on 64-pin devices. at power-on-reset, these pins are controlled by the jtag por t. to use these pins for general purpose i/o, the user?s application code must clear jtagen (ddpcon<3>) bit = 0 . to use these pins for jtag program/debug, the user?s application code must maintain jtagen bit = 1 .
? 2008 microchip technology inc. preliminary ds61143e - page 309 pic32mx3xx/4xx table 12-3: portc sfr summary virtual address name bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 bf88_6080 trisc 31:24 ? ? ? ? ? ? ? ? 23:16 ? ? ? ? ? ? ? ? 15:8 trisc15 trisc14 trisc13 trisc12 ? ? ? ? 7:0 ? ? ?trisc4 (1) trisc3 (1) trisc2 (1) trisc1 (1) ? bf88_6084 triscclr 31:0 write clears selected bits in trisc, read yields undefined value bf88_60088 triscset 31:0 write sets selected bits in trisc, read yields undefined value bf88_6088c triscinv 31:0 write inverts selected bits in trisc, read yields undefined value bf88_6090 portc 31:24 ? ? ? ? ? ? ? ? 23:16 ? ? ? ? ? ? ? ? 15:8 rc15 rc14 rc13 rc12 ? ? ? ? 7:0 ? ? ? rc4 (1) rc3 (1) rc2 (1) rc1 (1) ? bf88_6094 portcclr 31:0 write clears selected bits in portc, read yields undefined value bf88_6098 portcset 31:0 write sets selected bits in portc, read yields undefined value bf88_609c portcinv 31:0 write inverts selected bits in portc, read yields undefined value bf88_60a0 latc 31:24 ? ? ? ? ? ? ? ? 23:16 ? ? ? ? ? ? ? ? 15:8 latc15 latc14 latc13 latc12 ? ? ? ? 7:0 ? ? ?latc4 (1) latc3 (1) latc2 (1) latc1 (1) ? bf88_60a4 latcclr 31:0 write clears selected bits in latc, read yields undefined value bf88_60a8 latcset 31:0 write sets selected bits in latc, read yields undefined value bf88_60ac latcinv 31:0 write inverts selected bits in latc, read yields undefined value bf88_60b0 odcc 31:24 ? ? ? ? ? ? ? ? 23:16 ? ? ? ? ? ? ? ? 15:8 odcc15 odcc14 odcc13 odcc12 ? ? ? ? 7:0 ? ? ? odcc4 (1) odcc3 (1) odcc2 (1) odcc1 (1) ? bf88_60b4 odccclr 31:0 write clears selected bits in odcc, read yields undefined value bf88_60b8 odccset 31:0 write sets selected bits in odcc, read yields undefined value bf88_60bc odccinv 31:0 write inverts selected bits in odcc, read yields undefined value note 1: tris, port, lat and odc bit(s) are not im plemented on 64-pin devices, and read as ? 0 ?.
pic32mx3xx/4xx ds61143e - page 310 preliminary ? 2008 microchip technology inc. table 12-4: portd sfr summary virtual address name bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 bf88_60c0 trisd 31:24 ? ? ? ? ? ? ? ? 23:16 ? ? ? ? ? ? ? ? 15:8 trisd15 (1) trisd14 (1) trisd13 (1) trisd12 (1) trisd<11:8> 7:0 trisd<7:0> bf88_60c4 trisdclr 31:0 write clears selected bits in trisd, read yields undefined value bf88_60c8 trisdset 31:0 write sets selected bits in trisd, read yields undefined value bf88_60cc trisdinv 31:0 write inverts selected bits in trisd, read yields undefined value bf88_60d0 portd 31:24 ? ? ? ? ? ? ? ? 23:16 ? ? ? ? ? ? ? 15:8 rd15 (1) rd14 (1) rd13 (1) rd12 (1) rd<11:8> 7:0 rd<7:0> bf88_60d4 portdclr 31:0 write clears selected bits in portd, read yields undefined value bf88_60d8 portdset 31:0 write sets selected bits in portd, read yields undefined value bf88_60dc portdinv 31:0 write inverts selected bits in portd, read yields undefined value bf88_60e0 latd 31:24 ? ? ? ? ? ? ? ? 23:16 ? ? ? ? ? ? ? ? 15:8 lat15 (1) lat14 (1) lat13 (1) lat12 (1) latd<11:8> 7:0 latd<7:0> bf88_60e4 latdclr 31:0 write clears selected bits in latd, read yields undefined value bf88_60e8 latdset 31:0 write sets selected bits in latd, read yields undefined value bf88_60ec latdinv 31:0 write inverts selected bits in latd, read yields undefined value bf88_60f0 odcd 31:24 ? ? ? ? ? ? ? ? 23:16 ? ? ? ? ? ? ? ? 15:8 odcd15 (1) odcd14 (1) odcd13 (1) odcd12 (1) odcd<11:8> 7:0 odcd<7:0> bf88_60f4 odcdclr 31:0 write clears selected bits in odcd, read yields undefined value bf88_60f8 odcdset 31:0 write sets selected bits in odcd, read yields undefined value bf88_60fc odcdinv 31:0 write inverts selected bits in odcd, read yields undefined value note 1: tris, port, lat and odc bit(s) are not im plemented on 64-pin devices, and read as ? 0 ?.
? 2008 microchip technology inc. preliminary ds61143e - page 311 pic32mx3xx/4xx table 12-5: porte sfr summary virtual address name bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 bf88_6100 trise 31:24 ? ? ? ? ? ? ? ? 23:16 ? ? ? ? ? ? ? ? 15:8 ? ? ? ? ? ?trise9 (1) trise8 (1) 7:0 trise<7:0> bf88_6104 triseclr 31:0 write clears selected bits in trise, read yields undefined value bf88_6108 triseset 31:0 write sets selected bits in trise, read yields undefined value bf88_610c triseinv 31:0 write inverts selected bits in trise, read yields undefined value bf88_6110 porte 31:24 ? ? ? ? ? ? ? ? 23:16 ? ? ? ? ? ? ? ? 15:8 ? ? ? ? ? ?re9 (1) re8 (1) 7:0 re<7:0> bf88_6114 porteclr 31:0 write clears selected bits in porte, read yields undefined value bf88_6118 porteset 31:0 write sets selected bits in porte, read yields undefined value bf88_611c porteinv 31:0 write inverts selected bits in porte, read yields undefined value bf88_6120 late 31:24 ? ? ? ? ? ? ? ? 23:16 ? ? ? ? ? ? ? ? 15:8 ? ? ? ? ? ?late9 (1) late8 (1) 7:0 late<7:0> bf88_6124 lateclr 31:0 write clears selected bits in late, read yields undefined value bf88_6128 lateset 31:0 write sets selected bits in late, read yields undefined value bf88_612c lateinv 31:0 write inverts selected bits in late, read yields undefined value bf88_6130 odce 31:24 ? ? ? ? ? ? ? ? 23:16 ? ? ? ? ? ? ? ? 15:8 ? ? ? ? ? ?odce9 (1) odce8 (1) 7:0 odce<7:0> bf88_6134 odceclr 31:0 write clears selected bits in odce, read yields undefined value bf88_6138 odceset 31:0 write sets selected bits in odce, read yields undefined value bf88_613c odceinv 31:0 write inverts selected bits in odce, read yields undefined value note 1: tris, port, lat and odc bit(s) are not im plemented on 64-pin devices, and read as ? 0 ?.
pic32mx3xx/4xx ds61143e - page 312 preliminary ? 2008 microchip technology inc. table 12-6: portf sfr summary virtual address name bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 bf88_6140 trisf 31:24 ? ? ? ? ? ? ? ? 23:16 ? ? ? ? ? ? ? ? 15:8 ? ?trisf13 (1) trisf12 (1) ? ? ?trisf8 (1) 7:0 trisf7 (1) trisf6 trisf5 trisf4 trisf3 trisf2 trisf1 trisf0 bf88_6144 trisfclr 31:0 write clears selected bits in trisf, read yields undefined value bf88_6148 trisfset 31:0 write sets selected bits in trisf, read yields undefined value bf88_614c trisfinv 31:0 write inverts selected bits in trisf, read yields undefined value bf88_6150 portf 31:24 ? ? ? ? ? ? ? ? 23:16 ? ? ? ? ? ? ? ? 15:8 ? ?rf13 (1) rf12 (1) ? ? ?rf8 (1) 7:0 rf7 (1) rf6 rf5 rf4 rf3 rf2 rf1 rf0 bf88_6154 portfclr 31:0 write clears selected bits in portf, read yields undefined value bf88_6158 portfset 31:0 write sets selected bits in portf, read yields undefined value bf88_615c portfinv 31:0 write inverts selected bits in portf, read yields undefined value bf88_6160 latf 31:24 ? ? ? ? ? ? ? ? 23:16 ? ? ? ? ? ? ? ? 15:8 ? ? latf13 (1) latf12 (1) ? ? ?latf8 (1) 7:0 latf7 (1) latf6 latf5 latf4 latf3 latf2 latf1 latf0 bf88_6164 latfclr 31:0 write clears selected bits in latf, read yields undefined value bf88_6168 latfset 31:0 write sets selected bits in latf, read yields undefined value bf88_616c latfinv 31:0 write inverts selected bits in latf, read yields undefined value bf88_6170 odcf 31:24 ? ? ? ? ? ? ? ? 23:16 ? ? ? ? ? ? ? ? 15:8 ? ? odcf13 (1) odcf12 (1) ? ? ?odcf8 (1) 7:0 odcf7 (1) odcf6 odcf5 odcf4 odcf3 odcf2 odcf1 odcf0 bf88_6174 odcfclr 31:0 write clears selected bits in odcf, read yields undefined value bf88_6178 odcfset 31:0 write sets selected bits in odcf, read yields undefined value bf88_617c odcfinv 31:0 write inverts selected bits in odcf, read yields undefined value note 1: tris, port, lat and odc bit(s) are not im plemented on 64-pin devices, and read as ? 0 ?.
? 2008 microchip technology inc. preliminary ds61143e - page 313 pic32mx3xx/4xx table 12-7: portg sfr summary virtual address name bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 bf88_6180 trisg 31:24 ? ? ? ? ? ? ? ? 23:16 ? ? ? ? ? ? ? ? 15:8 trisg15 (1) trisg14 (1) trisg13 (1) trisg12 (1) ? ? trisg9 trisg8 7:0 trisg7 trisg6 ? ? trisg3 trisg2 trisg1 (1) trisg0 (1) bf88_6184 trisgclr 31:0 write clears selected bits in trisg, read yields undefined value bf88_6188 trisgset 31:0 write sets selected bits in trisg, read yields undefined value bf88_618c trisginv 31:0 write inverts selected bits in trisg, read yields undefined value bf88_6190 portg 31:24 ? ? ? ? ? ? ? ? 23:16 ? ? ? ? ? ? ? ? 15:8 rg15 (1) rg14 (1) rg13 (1) rg12 (1) ? ?rg9rg8 7:0 rg7 rg6 ? ?rg3rg2rg1 (1) rg0 (1) bf88_6194 portgclr 31:0 write clears selected bits in portg, read yields undefined value bf88_6198 portgset 31:0 write sets selected bits in portg, read yields undefined value bf88_619c portginv 31:0 write inverts selected bits in portg, read yields undefined value bf88_61a0 latg 31:24 ? ? ? ? ? ? ? ? 23:16 ? ? ? ? ? ? ? ? 15:8 latg15 (1) latg14 (1) latg13 (1) latg12 (1) ? ?latg9latg8 7:0 latg7 latg6 ? ? latg3 latg2 latg1 (1) latg0 (1) bf88_61a4 latgclr 31:0 write clears selected bits in latg, read yields undefined value bf88_61a8 latgset 31:0 write sets selected bits in latg, read yields undefined value bf88_61ac latginv 31:0 write inverts selected bits in latg, read yields undefined value bf88_61b0 odcg 31:24 ? ? ? ? ? ? ? ? 23:16 ? ? ? ? ? ? ? ? 15:8 odcg15 (1) odcg14 (1) odcg13 (1) odcg12 (1) ? ? odcg9 odcg8 7:0 odcg7 odcg6 ? ? odcg3 odcg2 odcg1 (1) odcg0 (1) bf88_61b4 odcgclr 31:0 write clears selected bits in odcg, read yields undefined value bf88_61b8 odcgset 31:0 write sets selected bits in odcg, read yields undefined value bf88_61bc odcginv 31:0 write inverts selected bits in odcg, read yields undefined value note 1: tris, port, lat and odc bit(s) are not implemented on 64-pin devices, and read as ? 0 ?. 2: on specific 100-pin devices, the instruct ion trace port is multiplexed with porta pins ra6, ra7; portg pins rg12, rg13 and rg14. at power-on reset, these pins are general purpose i/o pins. to maintain these pins as general pur- pose i/o pins, the user?s application code must maintain troen (ddpcon<2>) bit = 0 . to use these pins as instruction trace pins, troen must be set = 1 .
pic32mx3xx/4xx ds61143e - page 314 preliminary ? 2008 microchip technology inc. table 12-8: change notice and pull-up sfr summary virtual address name bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 bf88_61c0 cncon 31:24 ? ? ? ? ? ? ? ? 23:16 ? ? ? ? ? ? ? ? 15:8 on frz sidl ? ? ? ? ? 7:0 ? ? ? ? ? ? ? ? bf88_61c4 cnconclr 31:0 write clears selected bits in cncon, read yields undefined value bf88_61c8 cnconset 31:0 write sets selected bits in cncon, read yields undefined value bf88_61cc cnconinv 31:0 write inverts selected bits in cncon, read yields undefined value bf88_61d0 cnen 31:24 ? ? ? ? ? ? ? ? 23:16 ? ? cnen21 (1) cnen20 (1) cnen19 (1) cnen18 cnen17 cnen16 15:8 cnen<15:8> 7:0 cnen<7:0> bf88_61d4 cnenclr 31:0 write clears selected bits in cnen, read yields undefined value bf88_61d8 cnenset 31:0 write sets selected bits in cnen, read yields undefined value bf88_61dc cneninv 31:0 write inverts selected bits in cnen, read yields undefined value bf88_61e0 cnpue 31:24 ? ? ? ? ? ? ? ? 23:16 ? ? cnpue21 (1) cnpue20 (1) cnpue9 (1) cnpue18 cnpue17 cnpue16 15:8 cnpue<15:8> 7:0 cnpue<7:0> bf88_61e4 cnpueclr 31:0 write clears selected bits in cnpue, read yields undefined value bf88_61e8 cnpueset 31:0 write sets selected bits in cnpue, read yields undefined value bf88_61ec cnpueinv 31:0 write inverts selected bits in cnpue, read yields undefined value note 1: cnen and cnpue bit(s) are not implem ented on 64-pin devices, and read as ? 0 ?. table 12-9: change notice interrupt register summary virtual address name bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 bf88_1070 iec1 7:0 spi2rxie spi2txie spi2eie cmp2ie cmp1ie pmpie ad1ie cnie bf88_1040 ifs1 7:0 spi2rxif spi2txif spi2eif cmp2if cmp1if pmpif ad1if cnif bf88_10f0 ipc6 23:16 ? ? ? cnip<2:0> cnis<1:0> note: this summary table contains partial register definitions that only pertain to the gpio peripheral. refer to the ?pic32mx family reference manual? (ds61132) for a detailed description of these registers.
? 2008 microchip technology inc. preliminary ds61143e - page 315 pic32mx3xx/4xx register 12-1: trisx: tris registers r-x r-x r-x r-x r-x r-x r-x r-x ? ? ? ? ? ? ? ? bit 31 bit 24 r-x r-x r-x r-x r-x r-x r-x r-x ? ? ? ? ? ? ? ? bit 23 bit 16 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 trisx<15:8> bit 15 bit 8 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 trisx<7:0> bit 7 bit 0 legend: r = readable bit w = writable bit p = programmable bit r = reserved bit u = unimplemented bit -n = bit value at por: (?0?, ?1?, x = unknown) bit 31-16 reserved: write ? 0 ?; ignore read bit 15-0 trisx<15:0>: trisx register bits (1) 1 = corresponding port pin ?input? 0 = corresponding port pin ?output? note 1: depending on the device, certain register bits or the entire register may not be implemented. refer to table 12.1 for specific register and bit assignments.
pic32mx3xx/4xx ds61143e - page 316 preliminary ? 2008 microchip technology inc. register 12-2: portx: port registers r-x r-x r-x r-x r-x r-x r-x r-x ? ? ? ? ? ? ? ? bit 31 bit 24 r-x r-x r-x r-x r-x r-x r-x r-x ? ? ? ? ? ? ? ? bit 23 bit 16 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x rx<15:8> bit 15 bit 8 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x rx<7:0> bit 7 bit 0 legend: r = readable bit w = writable bit p = programmable bit r = reserved bit u = unimplemented bit -n = bit value at por: (?0?, ?1?, x = unknown) bit 31-16 reserved: write ? 0 ?; ignore read bit 15-0 portx<15:0>: portx register bits (1) read = value on port pins write = value written to the latx register, port latch and i/o pins note 1: depending on the device family variant, certain register bits or the entire register may not be implemented. refer to table 12.1 for specific register and bit assignments.
? 2008 microchip technology inc. preliminary ds61143e - page 317 pic32mx3xx/4xx register 12-3: latx: lat registers r-x r-x r-x r-x r-x r-x r-x r-x ? ? ? ? ? ? ? ? bit 31 bit 24 r-x r-x r-x r-x r-x r-x r-x r-x ? ? ? ? ? ? ? ? bit 23 bit 16 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x latx<15:8> bit 15 bit 8 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x latx<7:0> bit 7 bit 0 legend: r = readable bit w = writable bit p = programmable bit r = reserved bit u = unimplemented bit -n = bit value at por: (?0?, ?1?, x = unknown) bit 31-16 reserved: write ? 0 ?; ignore read bit 15-0 latx<15:0>: latx register bits (1) read = value on port latch, not i/o pins write = value written to port latch and i/o pins note 1: depending on the device, certain register bits or the entire register may not be implemented. refer to table 12.1 for specific register and bit assignments.
pic32mx3xx/4xx ds61143e - page 318 preliminary ? 2008 microchip technology inc. register 12-4: odcx: open dr ain configuration registers r-x r-x r-x r-x r-x r-x r-x r-x ? ? ? ? ? ? ? ? bit 31 bit 24 r-x r-x r-x r-x r-x r-x r-x r-x ? ? ? ? ? ? ? ? bit 23 bit 16 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 odcx<15:8> bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 odcx<7:0> bit 7 bit 0 legend: r = readable bit w = writable bit p = programmable r = reserved bit u = unimplemented bit, read as ?0? -n = bit value at por: (?0?, ?1?, x = unknown) bit 31-16 reserved: write ? 0 ?; ignore read bit 15-0 odcx<15:0>: odcx register bits (1) if a port pin is configured as an output (corresponding trisx bit = 0 ). 1 = port pin open-drain output enabled 0 = port pin open-drain output disabled if a port pin is configured as an input, odcx bits have no effect. note 1: depending on the device, certain register bits or the entire register may not be implemented. refer to table 12.1 for specific register and bit assignments.
? 2008 microchip technology inc. preliminary ds61143e - page 319 pic32mx3xx/4xx register 12-5: cncon: change notice control register r-x r-x r-x r-x r-x r-x r-x r-x ? ? ? ? ? ? ? ? bit 31 bit 24 r-x r-x r-x r-x r-x r-x r-x r-x ? ? ? ? ? ? ? ? bit 23 bit 16 r/w-0 r/w-0 r/w-0 r-x r-x r-x r-x r-x on frz sidl ? ? ? ? ? bit 15 bit 8 r-x r-x r-x r-x r-x r-x r-x r-x ? ? ? ? ? ? ? ? bit 7 bit 0 legend: r = readable bit w = writable bit p = programmable bit r = reserved bit u = unimplemented bit -n = bit value at por: (?0?, ?1?, x = unknown) bit 31-16 reserved: write ? 0 ?; ignore read bit 15 on: change notice module on bit 1 = cn module is enabled 0 = cn module is disabled bit 14 frz: freeze in debug exception mode bit 1 = freeze operation when cpu is in debug exception mode 0 = continue operation when cpu is in debug exception mode note: frz is writable in debug exception mode only, it is forced to ? 0 ? in normal mode. bit 13 sidl: stop in idle mode bit 1 = discontinue operation when device enters idle mode 0 = continue operation in idle mode bit 12-0 reserved: write ? 0 ?; ignore read
pic32mx3xx/4xx ds61143e - page 320 preliminary ? 2008 microchip technology inc. register 12-6: cnen: input change no tification interrupt enable register (1) r-x r-x r-x r-x r-x r-x r-x r-x ? ? ? ? ? ? ? ? bit 31 bit 24 r-x r-x r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? cnen21 cnen20 cnen19 cnen18 cnen17 cnen16 bit 23 bit 16 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 cnen15 cnen14 cnen13 cnen12 cnen11 cnen10 cnen9 cnen8 bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 cnen7 cnen6 cnen5 cnen4 cnen3 cnen2 cnen1 cnen0 bit 7 bit 0 legend: r = readable bit w = writable bit p = programmable bit r = reserved bit u = unimplemented bit -n = bit value at por: (?0?, ?1?, x = unknown) bit 31-22 reserved: write ? 0 ?; ignore read bit 21-0 cnen<21:0>: cnen register bits if a port pin is configured as an input (corresponding trisx bit = 1 ) 1 = port pin input change notice enabled 0 = port pin input change notice disabled if a port pin is configured as an output, cnenx bits have no effect note 1: depending on the device, certain register bits or the entire register may not be implemented. refer to table 12.1 for specific register and bit assignments.
? 2008 microchip technology inc. preliminary ds61143e - page 321 pic32mx3xx/4xx register 12-7: cnpue: input change notification pull-up enable (1) r-x r-x r-x r-x r-x r-x r-x r-x ? ? ? ? ? ? ? ? bit 31 bit 24 r-x r-x r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? cnpue21 cnpue20 cnpue19 cnpue18 cnpue17 cnpue16 bit 23 bit 16 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 cnpue15 cnpue14 cnpue13 cnpue12 cnpue11 cnpue10 cnpue9 cnpue8 bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 cnpue7 cnpue6 cnpue5 cnpue4 cnpue3 cnpue2 cnpue1 cnpue0 bit 7 bit 0 legend: r = readable bit w = writable bit p = programmable bit r = reserved bit u = unimplemented bit -n = bit value at por: (?0?, ?1?, x = unknown) bit 31-22 reserved: write ? 0 ?; ignore read bit 21-0 cnpue<21:0>: cnpue register bits if a port pin is configured as an input (corresponding trisx bit = 1 ). 1 = port pin pull-up enabled 0 = port pin pull-up disabled if a port pin is configured as an output, it is recommended to disable the corresponding cnpuex bit. note 1: depending on the device, certain register bits or the entire register may not be implemented. refer to table 12.1 for specific register and bit assignments.
pic32mx3xx/4xx ds61143e - page 322 preliminary ? 2008 microchip technology inc. 12.2 parallel i/o (pio) ports all port pins have three registers (tris, lat, and port) that are directly associated with their operation. tris is a data direction or tri-state control register that determines whether a digital pin is an input or an out- put. setting a trisx register bit = 1 configures the cor- responding i/o pin as an input; setting a trisx register bit = 0 configures the corresponding i/o pin as an out- put. all port i/o pins are defined as inputs after a device reset. certain i/o pins are shared with analog peripherals and default to analog inputs after a device reset. port is a register used to read the current state of the signal applied to the port i/o pins. writing to a portx register performs a write to the port?s latch, latx regis- ter, latching the data to the port?s i/o pins. lat is a register used to write data to the port i/o pins. the latx latch register holds the data written to either the latx or portx registers. reading the latx latch register reads the last value written to the corresponding port or latch register. not all port i/o pins are implemented on some devices, therefore, the corresponding portx, latx and trisx register bits will read as zeros. see section 12.1 ?port registers? . 12.2.1 clr, set and inv registers every i/o module register has a corresponding clr (clear), set (set) and inv (invert) register designed to provide fast atomic bit manipulations. as the name of the register implies, a value written to a set, clr or inv register effectively performs the implied operation, but only on the corresponding base register and only bits specified as ? 1 ? are modified. bits specified as ? 0 ? are not modified. reading set, clr and inv registers returns undefined values. to see the affects of a write operation to a set, clr or inv register, the base register must be read. to set portc bit 0, write to the latset register: latcset = 0x0001; to clear portc bit 0, write to the latclr register: latcclr = 0x0001; to toggle portc bit 0, write to the latinv register: latcinv = 0x0001; 12.2.2 digital inputs pins are configured as digital inputs by setting the cor- responding tris register bits = 1 . when configured as inputs, they are either ttl buffers or schmitt triggers. several digital pins share functionality with analog inputs and default to the analog inputs at por. setting the corresponding bit in the adp1cfg register = 1 enables the pin as a digital pin. digital only pins are capable of input voltages up to 5.5v. any pin that shares digital and analog functionality is limited to voltages up to v dd + 0.3v. . 12.2.3 analog inputs certain pins can be configured as analog inputs used by the adc and comparator modules. setting the cor- responding bits in the adp1cfg register = 0 enables the pin as an analog input pin and must have the corre- sponding tris bit set = 1 (input). if the tris bit is cleared = 0 (output), the digital output level (v oh or v ol ) will be converted. any time a port i/o pin is config- ured as analog, its digital input is disabled and the cor- responding portx register bit will read ? 0 ?. 12.2.4 digital outputs pins are configured as digital outputs by setting the cor- responding tris register bits = 0 . when configured as digital outputs, these pins are cmos drivers or can be configured as open drain outputs by setting the corre- sponding bits in the odcx open-drain configuration register. digital output pin voltage is limited to v dd . 12.2.5 analog outputs certain pins can be configured as analog outputs, such as the cv ref output voltage used by the comparator module. configuring the comparator reference mod- ule to provide this output will present the analog output voltage on the pin, independent of the tris register setting for the corresponding pin. note: using a portxinv register to toggle a bit is recommended because the operation is performed in hardware atomically, using fewer instructions as compared to the tra- ditional read-modify-write method shown below: portc ^= 0x0001; table 12-10: maximum input pin voltages input pin mode(s) v ih (max) digital only v ih = 5.5v digital + analog v ih = v dd + 0.03v analog v ih = v dd + 0.03v note: refer to section 30.0 ?electrical characteris- tics? regarding the v ih specification. note: analog levels on any pin that is defined as a digital input (including the anx pins) may cause the input buffer to consume current that exceeds the device specifications.
? 2008 microchip technology inc. preliminary ds61143e - page 323 pic32mx3xx/4xx 12.2.6 open-drain configuration in addition to the port, lat and tris registers for data control, each port pin configured as a digital output can also select between an active drive output and open-drain output. this is controlled by the open-drain control register, odcx, associated with each port. from por, when an io pin is configured as a digital output, its output is active drive by default. setting a bit in the odcx register = 1 configures the corresponding pin as an open-drain output. the open-drain feature allows the generation of outputs higher than v dd , e.g., 5v, on any desired digital-only pins by using external pull-up resistors. the maximum open-drain voltage allowed is the same as the maximum v ih specification, typically 5.5v. 12.2.7 peripheral multiplexing in many cases, i/o pins are multiplexed with more than one peripheral. a parallel i/o port pin that is multiplexed with a peripheral is, in general, subordinate to the peripheral. when a peripheral is enabled and actively driving the multiplexed pin, the use of the pin as a general purpose output pin is disabled. the i/o pin may be read, but the output driver for the parallel port bit will be disabled. if, however, a peripheral is enabled, but the peripheral is not actively driving a pin, that pin may be driven by a port. the peripheral?s output buffer data and control signals are provided to a pair of multiplexers. the multiplexers select whether the peripheral or the associated port has ownership of the output data and control signals of the i/o pin. the logic also prevents ?loop through?, in which a port?s digital output can drive the input of a peripheral that shares the same pin. figure 12-2 shows how ports are shared with other peripherals and the associated i/o pin to which they are connected. in general, the dominant output control of a multiplexed i/o pin can be determined by the order of the peripheral output names assigned to a pin (read from left to right). multiplexed peripheral inputs have no priority. for example, a pin labeled ?u1tx/rf3?, indicates the uart1 transmit output, if enabled, has a higher prece- dence over portf and therefore overrides the output control of this pin. 12.2.8 software input pin control some peripheral inputs assigned to an i/o pin may not take control of the i/o pin output driver. if the i/o pin associated with the peripheral is configured as an out- put, using the appropriate tris control bit, the user can manually affect the state of the peripheral?s input pin through its corresponding lat register. this behavior can be useful in some situations, especially for testing purposes, when no external signal is connected to the input pin. in general, the following peripherals allow their input pins to be controlled manually through the lat registers: ? external interrupt pins ? timer clock input pins ? input capture pins ? pwm fault pins most serial communication peripherals, when enabled, take full control of the i/o pin so that the input pins associated with the peripheral cannot be affected through the corresponding port registers. these peripherals include the following modules: ? spi ?i 2 c? ?uart notes: jtag program/debug port is multiplexed with porta pins ra0, ra1, ra4 and ra5 on 100-pin devices; portb pins rb10, rb11, rb12 and rb13 on 64-pin devices. at power-on-reset, these pins are con- trolled by the jtag port. to use these pins as general purpose i/o pins, the user?s application code must clear jtagen (ddpcon<3>) bit = 0. to maintain these pins for jtag program/debug, the user?s application code must maintain jtagen bit = 1. on specific 100-pin devices, the instruc- tion trace port is multiplexed with porta pins ra6, ra7; portg pins rg12, rg13 and rg14. at power-on reset, these pins are general purpose i/o pins. to maintain these pins as general purpose i/o pins, the user?s application code must maintain troen (ddp- con<2>) bit = 0 . to use these pins as instruction trace pins, troen must be set = 1 .
pic32mx3xx/4xx ds61143e - page 324 preliminary ? 2008 microchip technology inc. 12.2.9 input change notification certain pic32mx i/o port pins provide input change notification that can generate interrupt requests to the processor in response to a change-of-state (cos) on those selected input pins. the initial state of any enabled change notice (cn) pin must be established by reading the corresponding port register. this fea- ture is capable of detecting input cos even in sleep mode, when the clocks are disabled. depending on the device pin count, there are up to 22 external signals (cn0 through cn21) that may be selected (enabled) for generating an interrupt request on a cos. the following control registers are associated with the change notice module: ? cncon ? cnen ? cnpue the cncon control register on bit enables or disables the cn module and its ability to generate interrupts or respond to mismatch conditions. the cnen (change notice enable) register control bits enable each cn input. setting any of these bits enables a cn for the corresponding pins. the cnpue (change notice pull-up enable) register control bits enable a weak pull-up to a corresponding cn input pin. the pull-ups act as a current source that is connected to the pin, and eliminate the need for external resistors when push button or keypad devices are connected. table 12-11: change notice pin and pull-up table 12.2.10 change notice interrupts the change notice module is enabled as a source of interrupts via the respective cn interrupt enable bits: ? cnie (iec1<0>) ? cnif (ifs1<0>) the interrupt priority level bits and interrupt subpriority level bits must also be configured: ? cnip<2:0> (ipc6<20:18>) ? cnis<1:0> (ipc6<17:16>) to enable cn interrupts, the on bit (cncon<15>) must = 1 , one or more cn input pins must be enabled and the change notice interrupt enable bit, cnie, must = 1 . note: pull-up resistors on change notification pins should always be disabled whenever the port pin is configured as a digital output. change notice weak pull-up port pin 64-pin device 100-pin device pin# cn0 cnpue0 rc14 48 74 cn1 cnpue1 rc13 47 73 cn2 cnpue2 rb0 16 25 cn3 cnpue3 rb1 15 24 cn4 cnpue4 rb2 14 23 cn5 cnpue5 rb3 13 22 cn6 cnpue6 rb4 12 21 cn7 cnpue7 rb5 11 20 cn8 cnpue8 rg6 4 10 cn9 cnpue9 rg7 5 11 cn10 cnpue10 rg8 6 12 cn11 cnpue11 rg9 8 14 cn12 cnpue12 rb15 30 44 cn13 cnpue13 rd4 52 81 cn14 cnpue14 rd5 53 82 cn15 cnpue15 rd6 54 83 cn16 cnpue16 rd7 55 84 cn17 cnpue17 rf4 31 49 cn18 cnpue18 rf5 32 50 cn19 cnpue19 rd13 ? 80 cn20 cnpue20 rd14 ? 47 cn21 cnpue21 rd15 ? 48
? 2008 microchip technology inc. preliminary ds61143e - page 325 pic32mx3xx/4xx to prevent possible spurious interrupts when configur- ing change notice interrupts, the following steps are recommended: 1. disable cpu interrupts. 2. set desired cn i/o pin as input by setting corre- sponding trisx register bits = 1 . note: if the i/o pin is shared with an analog peripheral, it may be necessary to set the corre- sponding ad1pcfg bit = 1 to ensure that the i/o pin is a digital input. 3. enable change notice module on (cncon<15>) = 1 . 4. enable individual cn input pin(s); enable optional pull-up(s). 5. read corresponding port registers to clear mismatch condition on cn input pins. 6. configure the cn interrupt priority, cnip<2:0>, and subpriority cnis<1:0>. 7. clear cn interrupt flag, cnif = 0 . 8. enable cn interrupt enable, cnie = 1 . 9. enable cpu interrupts. the port must be read first to clear the mismatch con- dition, then the cn interrupt flag, cnif (ifs1<0>), can be cleared in software. failing to read the port before attempting to clear the cnif bit may not allow the cnif bit to be cleared. in addition to enabling the cn interrupt, an interrupt service routine (isr), is required. example 12-1 and example 12-2 show a partial code example of an isr. example 12-1: change notice configuration example note: it is the user?s responsibility to clear the corresponding interrupt flag bit before returning from an isr. /* the following code example illustrates a change notice interrupt configuration for pins cn1(portc.rc13), cn4(portb.rb2) and cn18(portf.rf5). */ unsigned int value; /* note: disable vector interrupts prior to configuration */ cncon = 0x8000; // enable change notice module cnen= 0x00040012; // enable cn1, cn4 and cn18 pins cnpue= 0x00040012; // enable weak pull ups for cn1, cn4 and cn18 pins /* read port(s) to clear mismatch on change notice pins */ value = portb; value = portc; value = portf; ips6set = 0x00140000; // set priority level=5 ips6set = 0x00030000; // set subpriority level=3 // could have also done this in single // operation by assigning ips6set = 0x00170000 ifs1clr = 0x0001; // clear the interrupt flag status bit iec1set = 0x0001; // enable change notice interrupts /* re-enable vector interrupts after configuration */
pic32mx3xx/4xx ds61143e - page 326 preliminary ? 2008 microchip technology inc. example 12-2: change notice isr example /* the following code example demonstrates a simple interrupt service routine for cn interrupts. the user?s code at this vector can perform any application-specific operations. the user?s code must read the cn corresponding port registers to clear the mismatch conditions before clearing the cn interrupt status flag. finally, the cn interrupt status flag must be cleared before exiting. */ void __isr(_change_notice_vector, ipl5) cn_interrupt_isr(void) { unsigned int value; value = portb // read portb to clear cn4 mismatch condition value = portc // read portc to clear cn1,cn0 mismatch condition ... perform application specific operations in response to the interrupt ifs1clr = 0x0001; // be sure to clear the cn interrupt status // flag before exiting the service routine. } note: the cn isr code example shows mplab? c32 c compiler-specific syntax. refer to your compiler manual regarding support for isrs.
? 2008 microchip technology inc. preliminary ds61143e-page 327 pic32mx3xx/4xx 13.0 timer1 this family of pic32mx devices features one synchronous/asynchronous 16-bit timer that can oper- ate as a free-running interval timer for various timing applications and counting external events. this timer can also be used with the low-power secondary oscillator, sosc, for real-time clock applications. the following modes are supported: ? synchronous internal timer ? synchronous internal gated timer ? synchronous external timer ? asynchronous external timer 13.1 additional supported features ? selectable clock prescaler ? timer operation during cpu idle and sleep mode ? fast bit manipulation using clr, set and inv registers ? asynchronous mode can be used with the low-power secondary oscillator to function as a real-time clock (rtc). note: this data sheet summarizes the features of the pic32mx3xx/4xx family of devices. it is not intended to be a compre- hensive reference source. refer to the ?pic32mx family reference manual? (ds61132) for a detailed description of this peripheral. table 13-1: timer1 features timer low-power oscillator asynchronous external clock 16-bit synchronous timer/counter 32-bit synchronous timer/counter gated timer special event trigger timer 1 yes yes yes no yes no
pic32mx3xx/4xx ds61143e-page 328 preliminary ? 2008 microchip technology inc. figure 13-1: timer1 block diagram (1) on (t1con<15>) sync sosci sosco/t1ck pr1 t1if equal 16-bit comparator tmr1 reset soscen event flag 1 0 tsync (t1con<2>) tgate (t1con<7>) tgate (t1con<7>) pbclk 1 0 tcs (t1con<1>) gate sync tckps<1:0> prescaler 2 1, 8, 64, 256 x 1 1 0 0 0 q qd (t1con<5:4>) note 1: the default state of the soscen (osccon<1>) during a device reset is controlled by the fsoscen bit in configuration word devcfg1.
? 2008 microchip technology inc. preliminary ds61143e-page 329 pic32mx3xx/4xx 13.2 timer registers table 13-2: timer1 sfr summary virtual address name bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 bf80_0600 t1con 31:24 ? ? ? ? ? ? ? ? 23:16 ? ? ? ? ? ? ? ? 15:8 on frz sidl twdis twip ? ? ? 7:0 tgate ?tckps<1:0> ?tsynctcs ? bf80_0604 t1conclr 31:0 write clears selected bits in t1con, read yields undefined value bf80_0608 t1conset 31:0 write sets selected bits in t1con, read yields undefined value bf80_060c t1coninv 31:0 write inverts selected bits in t1con, read yields undefined value bf80_0610 tmr1 31:24 ? ? ? ? ? ? ? ? 23:16 ? ? ? ? ? ? ? ? 15:8 tmr1<15:8> 7:0 tmr1<7:0> bf80_0614 tmr1clr 31:0 write clears selected bits in tmr1, read yields undefined value bf80_0618 tmr1set 31:0 write sets selected bits in tmr1, read yields undefined value bf80_061c tmr1inv 31:0 write inverts selected bits in tmr1, read yields undefined value bf80_0620 pr1 31:24 ? ? ? ? ? ? ? ? 23:16 ? ? ? ? ? ? ? ? 15:8 pr1<15:8> 7:0 pr1<7:0> bf80_0624 pr1clr 31:0 write clears selected bits in pr1, read yields undefined value bf80_0628 pr1set 31:0 write sets selected bits in pr1, read yields undefined value bf80_062c pr1inv 31:0 write inverts selected bits in pr1, read yields undefined value table 13-3: timer1 interrupt register summary (1) virtual address name bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 bf88_1060 iec0 7:0 int1ie oc1ie ic2ie t1ie int0ie cs1ie cs0ie ctie bf88_1030 ifs0 7:0 int1if oc1if ic2if t1if int0if cs1if cs0if ctif bf88_10a0 ipc1 7:0 ? ? ? t1ip<2:0> t1is<1:0> note 1: this summary table contains partial register definitions that only pertain to the timer1 peripheral. refer to the ?pic32mx family reference manual? (ds61132) for a detailed description of these registers.
pic32mx3xx/4xx ds61143e-page 330 preliminary ? 2008 microchip technology inc. register 13-1: t1con: ti mer1 control register r-x r-x r-x r-x r-x r-x r-x r-x ? ? ? ? ? ? ? ? bit 31 bit 24 r-x r-x r-x r-x r-x r-x r-x r-x ? ? ? ? ? ? ? ? bit 23 bit 16 r/w-0 r/w-0 r/w-0 r/w-0 r-0 r-x r-x r-x on frz sidl twdis twip ? ? ? bit 15 bit 8 r/w-0 r-x r/w-0 r/w-0 r-x r/w-0 r/w-0 r-x tgate ? tckps<1:0> ? tsync tcs ? bit 7 bit 0 legend: r = readable bit w = writable bit p = programmable bit r = reserved bit u = unimplemented bit -n = bit value at por: (?0?, ?1?, x = unknown) bit 31-16 reserved: write ? 0 ?; ignore read bit 15 on: timer on bit 1 = timer is enabled 0 = timer is disabled bit 14 frz: freeze in debug exception mode bit 1 = freeze operation when cpu is in debug exception mode 0 = continue operation when cpu is in debug exception mode note: frz is writable in debug exception mode only, it is forced to ? 0 ? in normal mode. bit 13 sidl: stop in idle mode bit 1 = discontinue operation when device enters idle mode 0 = continue operation in idle mode bit 12 twdis: asynchronous timer write disable bit in asynchronous timer mode: 1 = writes to asynchronous tmr1 are ignored until pending write operation completes 0 = back-to-back writes are enabled (legacy asynchronous timer functionality) in synchronous timer mode: this bit has no effect. bit 11 twip: asynchronous timer write in progress bit in asynchronous timer mode: 1 = asynchronous write to tmr1 register in progress 0 = asynchronous write to tmr1 register complete in synchronous timer mode: this bit is read as ? 0 ?. bit 10-8 reserved: write ? 0 ?; ignore read
? 2008 microchip technology inc. preliminary ds61143e-page 331 pic32mx3xx/4xx bit 7 tgate: gated time accumulation enable bit when tcs = 1 : this bit is ignored and read ? 0 ?. when tcs = 0 : 1 = gated time accumulation is enabled 0 = gated time accumulation is disabled bit 6 reserved: write ? 0 ?; ignore read bit 5-4 tckps<1:0>: timer input clock prescaler select bits 11 = 1:256 prescale value 10 = 1:64 prescale value 01 = 1:8 prescale value 00 = 1:1 prescale value bit 3 reserved: write ? 0 ?; ignore read bit 2 tsync: timer external clock input synchronization selection bit when tcs = 1 : 1 = external clock input is synchronized 0 = external clock input is not synchronized when tcs = 0 : this bit is ignored and read ? 0 ?. bit 1 tcs: timer clock source select bit 1 = external clock from t1cki pin 0 = internal peripheral clock bit 0 reserved: write ? 0 ?; ignore read register 13-1: t1con: timer1 control register (continued)
pic32mx3xx/4xx ds61143e-page 332 preliminary ? 2008 microchip technology inc. 13.3 modes of operation the 16-bit timer1 peripheral can operate as a synchronous timer using internal or external clock sources, or as a gated timer using internal clock source and external clock pin, or as an asynchronous timer using an external asynchronous clock source, such as the low-power secondary oscillator. each mode is easily configured and described in the following sections. 13.3.1 considerations for all timer 1 modes ? timer1 module is disabled and powered off when the on bit (t1con<15>) = 0 , thus providing max- imum power savings. all other txcon bits remain unchanged. ? updates to the t1con register should only be performed when the timer module is disabled, on bit (t1con<15>) = 0 . ? timer1 continues operating when the cpu goes into idle mode if the ?stop in idle mode? control bit is disabled, sidl (txcon<13>) bit = 0 . if enabled, sidl = 1 , the timer module stops operation while the cpu is in idle mode. ? setting or clearing the on bit (t1con<15>) and any other bits in t1con in the same instruction may cause undefined behavior. the user is advised to program the t1con register with the desired settings with one instruction, and then set the on bit in a subsequent instruction. 13.3.2 synchronous internal timer in this mode, the timer clock source is the internal pbclk (peripheral bus clock), tcs (txcon<1>) = 0 . clock synchronization is not required, therefore the timer1 synchronization bit, tsync (t1con<2>), is ignored. the tmr1 count register increments on every pbclk clock cycle when the timer clock prescale is 1:1. timer1 generates a timer match event after the tmr1 count register matches the pr1 period register value (mid-clock cycle on the falling edge), then resets to 0x0000 on the next pbclk clock cycle. see section 13.5 ?timer interrupts? regarding timer events and interrupts. for clock prescale = n (other than 1:1), the timer oper- ates at a clock rate = pbclk/n and the tmrx count register increments on every nth pbclk clock. for further details regarding the timer prescaler, refer to section 13.4.2 ?timer clock prescaler? . the following steps should be performed to properly configure the timer1 peripheral for timer mode operation. 1. clear on control bit (t1con<15>) = 0 to disable timer. 2. configure tckps control bits (t1con<5:4) to select desired timer clock prescale. 3. set tcs control bit (t1con<1>) = 0 to select the internal pbclk clock source. 4. clear tmr1 register. 5. load pr1 register with desired 16-bit match value. 6. if timer interrupts are to be used, refer to section 13.5 ?timer interrupts? for interrupt configuration steps. 7. set on control bit = 1 to enable timer. example 13-1: synchronous internal timer initialization t1con = 0x0 // stop and init timer tmr1 = 0x0; // clear timer register pr1 = 0xffff; // load period register t1conset = 0x8000;// start timer
? 2008 microchip technology inc. preliminary ds61143e-page 333 pic32mx3xx/4xx 13.3.3 synchronous external timer in this mode, the timer clock source is an external clock source or pulse applied to the t1ck pin, tcs (t1con<1>) = 1 . to provide synchronization, timer1 synchronization bit tsync (t1con<2>) must be set (= 1) . the 16-bit tmr1 count register increments on every synchronized rising edge of an external clock when the timer clock prescale is 1:1. timer1 generates a timer match event after the tmr1 count register matches the pr1 period register value (mid-clock cycle on the falling edge), then resets to 0x0000 on the next synchronized external clock cycle. the timer continues to increment and repeat the period match until the timer is disabled. for further details regarding timer events and interrupts, see section 13.5 ?timer interrupts? . for clock prescale = n (other than 1:1), the timer oper- ates at a clock rate = (external clock/n), therefore, the tmrx count register increments on every nth external synchronized clock cycle. for further details regarding timer prescaler, refer to section 13.4.2 ?timer clock prescaler? . 13.3.3.1 considerations ? when using an external clock source, regardless of the timer1 prescale value, 2-3 external clock cycles are required, after the on bit = 1 , before the tmr1 register begins incrementing. ? timer1 will not operate from a synchronized exter- nal clock source while the cpu is in sleep mode, since the synchronizing pb clock is disabled during sleep mode. the following steps should be performed to properly configure the timer1 peripheral for synchronous coun- ter mode operation. 1. clear control bit, on (t1con<15>) = 0 , to disable timer1. 2. select the desired timer prescaler using bits, tckps<1:0> (t1con<5:4). 3. set control bit, tcs (t1con<1>) = 1 , to select an external clock source. 4. set control bit, tsync (t1con<2>) = 1 , to enable synchronization. 5. clear timer register tmr1. 6. load period register pr1 with desired 16-bit match value. 7. if timer interrupts are used, refer to section 13.5 ?timer interrupts? for interrupt configuration steps. 8. set control bit, on (t1con<15>) = 1 , to enable timer1. example 13-2: synchronous external timer initialization 13.3.4 asynchronous external timer in this mode, the timer clock source is an external clock source or pulse applied to the t1ck pin, tcs (t1con<1>) = 1 . clock synchronization is not required, therefore, the timer1 clock synchronization bit should be cleared, tsync (t1con<2>) = 0 . the 16-bit tmr1 count register increments on every rising edge of an external clock when the timer clock prescale is 1:1. timer1 generates a timer match event after the tmr1 count register matches the pr1 register value (mid- clock cycle on the falling edge), then resets to 0x0000 on the next external clock cycle. the timer continues to increment and repeat the period match until the timer is disabled. for further details regarding timer events and interrupts, see section 13.5 ?timer interrupts? . for clock prescale = n (other than 1:1), the timer oper- ates at a clock rate = (external clock/n), therefore, the tmr1 count register increments on every nth exter- nal clock cycle. for further details regarding the timer prescaler, refer to section 13.4.2 ?timer clock prescaler? . 13.3.4.1 considerations ? regardless of the timer1 prescale setting, 2-3 external clocks are required after the on bit = 1 , before the tmr1 register begins incrementing. ? timer1 can operate while the cpu is in sleep mode. ? the timer1 interrupt can be used to wake the cpu from sleep mode. ? typical use is with the secondary low-power oscillator, sosc and rtcc real-time clock calendar peripheral. note: the sosc oscillator may be used by the cpu as a low-power clock source. timer 1 does not have exclusive usage to this oscillator. refer to the ? pic32mx family reference manual ? (ds61132) regarding the operation of the secondary low- power oscillator. t1con = 0x0; // stop timer and reset t1con = 0x0036 // set prescaler=1:256, // external clock, // synchronous mode tmr1 = 0x0; // clear timer register pr1 = 0x3fff; // load period register t1conset = 0x8000; // start timer
pic32mx3xx/4xx ds61143e-page 334 preliminary ? 2008 microchip technology inc. 13.4 reading and writing tmr1 register due to the asynchronous nature of timer1 operating in asynchronous clock mode, reading and writing to the tmr1 count register requires synchronization between the asynchronous clock source and the inter- nal pbclk (peripheral bus clock). timer1 features a timer write disable (twdis) control bit (t1con<12>) and a twip (timer write in progress) status bit (t1con<11>). these bits provide the user with 2 options for safely writing to the tmr1 count register while timer1 is enabled. these bits have no affect in synchronous clock modes. ? option 1 ? legacy timer1 write mode, twdis bit = 0 . to determine when it is safe to write to the tmr1 count register, it is recommended to poll the twip bit. when twip = 0 , it is safe to perform the next write operation to the tmr1 count regis- ter. when twip = 1 , the previous write operation to the tmr1 count register is still being synchro- nized and any additional write operations should wait until twip = 0 . ? option 2 ? new synchronized timer1 write mode, twdis bit = 1 . a write to the tmr1 count register can be performed at any time. however, if the pre- vious write operation to the tmr1 count register is still being synchronized, any additional write operations are ignored. writing to the tmr1 count register requires 2 to 3 asynchronous external clock cycles for the value to be synchronized into the tmr1 count register. reading from the tmr1 count register requires 2 pbclk cycle delays between the current unsynchro- nized value in the tmr1 count register and the synchronized value returned by the read operation. in other words, the value read is always 2 pbclk cycles behind the actual value in the tmr1 count register. the following steps should be performed to properly configure the timer1 peripheral for asynchronous counter mode operation. 1. clear control bit, on (t1con<15>) = 0 , to disable timer1. 2. select the desired timer prescaler using bits, tckps<1:0> (t1con<5:4). 3. set control bit, tcs (t1con<1>) = 1 , to select an external clock source. 4. set control bit, tsync (t1con<2>) = 0 , to disable synchronization. 5. clear timer register, tmr1. 6. load period register, pr1, with desired 16-bit match value. 7. if timer interrupts are used, refer to 13.5 ?timer interrupts? for interrupt configuration steps. 8. set control bit, on (t1con<15>) = 1 , to enable timer1. example 13-3: asynchronous external timer initialization t1con = 0x0; // stop time and reset t1con = 0x0012; // set prescaler at 1:8, // external clock source, // asynchronous mode tmr1 = 0x0; // clear timer register pr1 = 0x7fff; // load period register t1conset = 0x8000; // start timer
? 2008 microchip technology inc. preliminary ds61143e-page 335 pic32mx3xx/4xx 13.4.1 synchronous internal gated timer in this mode, the timer clock source can only be the internal pbclk (peripheral bus cock), tcs (t1con<1>) = 0 . the t1ck pin provides the gating mechanism to enable and disable the timer counting, tgate (t1con<7>) = 1 . clock synchronization is not required, therefore timer1 synchronization bit, tsync (t1con<2>), is ignored. the 16-bit tmr1 count reg- ister is enabled on the rising edge of the t1ck pin and increments on every internal pbclk cycle when the timer clock prescale is 1:1. the timer increments until the tmr1 count register matches the pr1 register value. the tmr1 count reg- ister resets to 0x0000 on the next pbclk clock cycle. a timer match event is not generated. the timer contin- ues to increment and repeat the period match until the falling edge of the t1ck pin or the timer is disabled. on the falling edge of the gate signal, a timer gate event is generated and the tmr1 count register stops count- ing, but is not reset to 0x0000. the tmr1 count regis- ter must be reset in software. for further details regarding timer events and interrupts, see section 13.5 ?timer interrupts? . for clock prescale = n (other than 1:1), the timer oper- ates at a clock rate = (pbclk/n); therefore, the tmr1 count register increments on every nth pbclk clock cycle. for further details regarding timer prescaler, refer to section 13.4.2 ?timer clock prescaler? . the following steps should be performed to properly configure the timer1 peripheral for gated timer mode operation: 1. clear control bit, on (t1con<15>) = 0 , to disable timer1. 2. select the desired timer prescaler using bits, tckps<1:0> (t1con<5:4>). 3. set control bit, tcs (t1con<1>) = 0 , to select the internal clock source. 4. set control bit tgate (t1con<6>) = 1 . 5. clear timer register, tmr1. 6. load period register, pr1, with desired 16-bit match value. 7. if timer interrupts are used, refer to section 13.5 ?timer interrupts? for interrupt configuration steps. 8. set control bit on, (t1con<15>) = 1 , to enable timer1. example 13-4: synchronous internal gated timer initialization 13.4.2 timer clock prescaler timer clock prescale bits, tckps<1:0> (t1con<5:4>), are used to divide the timer clock source, permitting the tmr register to increment on every 1, 8, 64, or 256 (pbclk or external) clock cycles. for example, if the clock prescale is 1:8, then the timer increments on every 8th timer clock cycle. associated with the clock prescale selection bits is a prescale counter. this prescale counter is cleared when any of the following conditions occur: ? any device reset, except a power-on reset ? the timer is disabled ? a write to the tmr register ? when the timer clock source is external and the timer clock prescale = n (other than 1:1), 2 to 3 external clock cycles are required, after the timer on bit is set = 1 , before the tmr1 count register increments. ? after a timer match event (tmr1 = pr1) and depending on the timer clock prescale setting n (other than 1:1), the timer will require n/2 addi- tional (pbclk or external) clock cycles before the tmr1 counter register reset to 0x0000. reading the tmr1 count register just after the timer match event, but before the tmr1 count register is rest, will return the timer match value. note: when the timer clock source is external and the timer clock prescale = n (other than 1:1), 2 to 3 external clock cycles are required to reset and synchronize the prescaler. t1con = 0x0; // stop timer and reset t1con = 0x0060; // enable gated mode, // prescaler at 1:64, // internal clock source tmr1 = 0x0; // clear timer register pr1 = 0xffff; // load period register t1conset = 0x8000;// start timer
pic32mx3xx/4xx ds61143e-page 336 preliminary ? 2008 microchip technology inc. 13.5 timer interrupts timer1 can generate an interrupt on a period match event or a gate event, caused by the falling edge of the external gate signal. timer1 sets the interrupt flag bit, t1if (ifs0<4>), whenever a timer1 event is generated. refer to a spe- cific timer mode for details regarding event conditions. when a timer1 event is generated, the interrupt flag bit is set within 1 pbclk + 2 sysclk cycles. if timer1 interrupt enable bit is set, t1ie (iec0<4>) = 1 , an interrupt is generated. the timer1 module is enabled as a source of interrupts through its respective interrupt enable bit, t1ie (iec0<4>). the timer1 interrupt flag, t1if (ifs0<4>), must be cleared in software. the interrupt priority level bits and interrupt subpriority level bits must be also be configured: ? t1ip<2:0> (ipc1<4:2>) ? t1is<1:0> (ipc1<1:0) setting timer1 interrupt priority level = 0 effectively disables the timer?s ability to generate an interrupt. in addition to enabling the timer1 interrupt, an interrupt service routine, isr, is generally required. below is a partial code example of an isr. example 13-5: timer interrupt and priorities example 13-6: timer isr note: it is the user?s responsibility to clear the corresponding interrupt flag bit before returning from an isr. t1con = 0x0 // stop the timer and reset control register // set prescaler at 1:1, internal clock source tmr1 = 0x0; // clear timer register pr1 = 0xffff; // load period register ipc1set = 0x000c; // set priority level=3 ipc1set = 0x0001; // set subpriority level=1 // could have also done this in single // operation by assigning ipc1set = 0x000d ifs0clr = 0x0010; // clear timer interrupt status flag iec0set = 0x0010; // enable timer interrupts t1conset = 0x8000; // start timer void __isr(_timer_1_vector, ipl3) t1_interrupt_isr(void) { ... perform application specific operations in response to the interrupt ifs0clr = 0x0010; // be sure to clear the timer 1 interrupt status } note: the timer isr code example shows mplab ? c32 c compiler specific syntax. refer to your compiler manual regarding support for isrs.
? 2008 microchip technology inc. preliminary ds61143e-page 337 pic32mx3xx/4xx 13.6 i/o pin configuration table 13-4 provides a summary of i/o pin resources associated with timer1. the table shows the settings required to make each i/o pin work with a specific timer module. table 13-4: i/o pin co nfiguration for use with the timer module required settings for module pin control i/o pin name required module enable (2) bit field (2) tris pin type buffer type description t1ck yes (1) on tcs, tgate input i st timer1 external clock/gate input legend: cmos = cmos compatible input or output st = schmitt trigger input with cmos levels i = input o = output note 1: this pin is only required for gated timer or external synchr onous clock modes. otherwise, this pin can be used for general purpose i/o and requires the user to set the corresponding tris control register bits. 2: this bit is located in the t1con register.
pic32mx3xx/4xx ds61143e-page 338 preliminary ? 2008 microchip technology inc. notes:
? 2008 microchip technology inc. preliminary ds61143e-page 339 pic32mx3xx/4xx 14.0 timers 2, 3, 4, 5 this family of pic32mx devices features four synchronous 16-bit timers (default) that can operate as a free-running interval timer for various timing applica- tions and counting external events. the following modes are supported: ? synchronous internal 16-bit timer ? synchronous internal 16-bit gated timer ? synchronous external 16-bit timer two 32-bit synchronous timers are available by combining timer2 with timer3 and timer4 with timer5. the 32-bit timers can operate in three modes: ? synchronous internal 32-bit timer ? synchronous internal 32-bit gated timer ? synchronous external 32-bit timer 14.1 additional supported features ? selectable clock prescaler ? timers operational during cpu idle ? time base for input capture and output compare modules (timer2 and timer3 only) ? adc event trigger (timer3 only) ? fast bit manipulation using clr, set and inv registers table 14-1 highlights the available features of these timers. note: this data sheet summarizes the features of the pic32mx3xx/4xx family of devices. it is not intended to be a comprehensive refer- ence source. refer to the ?pic32mx family reference manual? (ds61132) for a detailed description of this peripheral. note: throughout this chapter, references to registers txcon, tmrx, and prx use ?x? to represent timer2 through 5 in 16-bit modes. in 32-bit modes, ?x? represents timer2 or 4; ?y? represents timer3 or 5. table 14-1: timer features timers low-power oscillator asynchronous external clock 16-bit synchronous timer 32-bit synchronous timer (1) gated timer special event trigger 2, 4 no no yes yes yes no 3, 5 no no yes yes yes yes (2) note 1: 32-bit mode requires combining timers 2 and 3 or timers 4 and 5. 2: adc event trigger supported by timer3 only.
pic32mx3xx/4xx ds61143e-page 340 preliminary ? 2008 microchip technology inc. figure 14-1: timer2, 3, 4, 5 block diagram (16-bit) figure 14-2: timer2/3, 4/5 block diagram (32-bit) sync prx txif equal comparator x 16 tmrx reset event flag q qd tgate (txcon<7>) 1 0 gate txck sync on (txcon<15>) tgate (txcon<7>) tcs (txcon<1>) tckps (txcon<6:4>) prescaler 3 1, 2, 4, 8, 16, 32, 64, 256 x 1 1 0 0 0 pbclk (note 1) trigger adc event note 1: adc event trigger is available on timer3 only. 2: txck pins not available on 64-pin devices. (note 2) tmry tmrx tyif event equal 32-bit comparator pry prx reset lshalfword mshalfword flag note 1: in this diagram, the use of ?x? in registers txcon, tmrx, prx, txck refers to either timer2 or timer4; the use of ?y? in registers tycon, tmry, pry, tyif refers to either timer3 or timer5. 2: txck pins not available on 64-pin devices. 3: adc event trigger is available only on timer2/3 pair. tgate (txcon<7>) 0 1 pbclk gate txck sync sync adc event trigger on (txcon<15>) tgate (txcon<7>) tcs (txcon<1>) tckps (txcon<6:4>) prescaler 3 1, 2, 4, 8, 16, 32, 64, 256 1 0 0 0 q qd (note 3) x 1 (note 2)
? 2008 microchip technology inc. preliminary ds61143e-page 341 pic32mx3xx/4xx table 14-1: timer2 sfr summary virtual address name bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 bf80_0800 t2con 31:24 ? ? ? ? ? ? ? ? 23:16 ? ? ? ? ? ? ? ? 15:8 on frz sidl ? ? ? ? ? 7:0 tgate tckps<2:0> t32 ?tcs ? bf80_0804 t2conclr 31:0 write clears selected bits in t2con, read yields undefined value bf80_0808 t2conset 31:0 write sets selected bits in t2con, read yields undefined value bf80_080c t2coninv 31:0 write inverts selected bits in t2con, read yields undefined value bf80_0810 tmr2 31:24 ? ? ? ? ? ? ? ? 23:16 ? ? ? ? ? ? ? ? 15:8 tmr2<15:8> 7:0 tmr2<7:0> bf80_0814 tmr2clr 31:0 write clears selected bits in tmr2, read yields undefined value bf80_0818 tmr2set 31:0 write sets selected bits in tmr2, read yields undefined value bf80_081c tmr2inv 31:0 write inverts selected bits in tmr2, read yields undefined value bf80_0820 pr2 31:24 ? ? ? ? ? ? ? ? 23:16 ? ? ? ? ? ? ? ? 15:8 pr2<15:8> 7:0 pr2<7:0> bf80_0824 pr2clr 31:0 write clears selected bits in pr2, read yields undefined value bf80_0828 pr2set 31:0 write sets selected bits in pr2, read yields undefined value bf80_082c pr2inv 31:0 write inverts selected bits in pr2, read yields undefined value table 14-2: timer2 interrupt register summary (1) virtual address name bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 bf88_1060 iec0 15:8 int3ie oc3ie ic3ie t3ie int2ie oc2ie ic2ie t2ie bf88_1030 ifs0 15:8 int3if oc3if ic3if t3if int2if oc2if ic2if t2if bf88_10b0 ipc2 7:0 ? ? ? t2ip<2:0> t2is<1:0> note 1: this summary table contains partial register definitions t hat only pertain to the timer2 peripheral. refer to the ? pic32mx fam- ily reference manual ? (ds61132) for a detailed description of these registers. table 14-3: timer3 sfr summary virtual address name bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 bf80_0a00 t3con 31:24 ? ? ? ? ? ? ? ? 23:16 ? ? ? ? ? ? ? ? 15:8 on frz sidl ? ? ? ? ? 7:0 tgate tckps<2:0> ? ?tcs ? bf80_0a04 t3conclr 31:0 write clears selected bits in t3con, read yields undefined value bf80_0a08 t3conset 31:0 write sets selected bits in t3con, read yields undefined value bf80_0a0c t3coninv 31:0 write inverts selected bits in t3con, read yields undefined value bf80_0a10 tmr3 31:24 ? ? ? ? ? ? ? ? 23:16 ? ? ? ? ? ? ? ? 15:8 tmr3<15:8> 7:0 tmr3<7:0> bf80_0a14 tmr3clr 31:0 write clears selected bits in tmr3, read yields undefined value bf80_0a18 tmr3set 31:0 write sets selected bits in tmr3, read yields undefined value bf80_0a1c tmr3inv 31:0 write inverts selected bits in tmr3, read yields undefined value
pic32mx3xx/4xx ds61143e-page 342 preliminary ? 2008 microchip technology inc. bf80_0a20 pr3 31:24 ? ? ? ? ? ? ? ? 23:16 ? ? ? ? ? ? ? ? 15:8 pr3<15:8> 7:0 pr3<7:0> bf80_0a24 pr3clr 31:0 write clears selected bits in pr3, read yields undefined value bf80_0a28 pr3set 31:0 write sets selected bits in pr3, read yields undefined value bf80_0a2c pr3inv 31:0 write inverts selected bits in pr3, read yields undefined value table 14-4: timer3 interrupt register summary (1) virtual address name bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 bf88_1060 iec0 15:8 int3ie oc3ie ic3ie t3ie int2ie oc2ie ic2ie t2ie bf88_1030 ifs0 15:8 int3if oc3if ic3if t3if int2if oc2if ic2if t2if bf88_10c0 ipc3 7:0 ? ? ? t3ip<2:0> t3is<1:0> note 1: this summary table contains partial register definitions that only pertain to the timer 3 peripheral. refer to the pic32mx fam- ily reference manual (ds61132) for a detailed description of these registers. register 14-5: timer4 sfr summary virtual address name bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 bf80_0c00 t4con 31:24 ? ? ? ? ? ? ? ? 23:16 ? ? ? ? ? ? ? ? 15:8 on frz sidl ? ? ? ? ? 7:0 tgate tckps<2:0> t32 ?tcs ? bf80_0c04 t4conclr 31:0 write clears selected bits in t4con, read yields undefined value bf80_0c08 t4conset 31:0 write sets selected bits in t4con, read yields undefined value bf80_0c0c t4coninv 31:0 write inverts selected bits in t4con, read yields undefined value bf80_0c10 tmr4 31:24 ? ? ? ? ? ? ? ? 23:16 ? ? ? ? ? ? ? ? 15:8 tmr4<15:8> 7:0 tmr4<7:0> bf80_0c14 tmr4clr 31:0 write clears selected bits in tmr4, read yields undefined value bf80_0c18 tmr4set 31:0 write sets selected bits in tmr4, read yields undefined value bf80_0c1c tmr4inv 31:0 write inverts selected bits in tmr4, read yields undefined value bf80_0c20 pr4 31:24 ? ? ? ? ? ? ? ? 23:16 ? ? ? ? ? ? ? ? 15:8 pr4<15:8> 7:0 pr4<7:0> bf80_0c24 pr4clr 31:0 write clears selected bits in pr4, read yields undefined value bf80_0c28 pr4set 31:0 write sets selected bits in pr4, read yields undefined value bf80_0c2c pr4inv 31:0 write inverts selected bits in pr4, read yields undefined value register 14-6: timer4 interrupt register summary (1) virtual address name bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 bf88_1060 iec0 23:16 spi1eie oc5ie ic5ie t5ie int4ie oc4ie ic4ie t4ie bf88_1030 ifs0 23:16 spi1eif oc5if ic5if t5if int4if oc4if ic4if t4if bf88_10d0 ipc4 7:0 ? ? ? t4ip<2:0> t4is<1:0> note 1: this summary table contains partial register definitions that only pertain to the timer4 peripheral. refer to the ? pic32mx fam- ily reference manual ? (ds61132) for a detailed description of these registers. table 14-3: timer3 sfr summary (continued) virtual address name bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0
? 2008 microchip technology inc. preliminary ds61143e-page 343 pic32mx3xx/4xx table 14-7: timer5 sfr summary virtual address name bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 bf80_0e00 t5con 31:24 ? ? ? ? ? ? ? ? 23:16 ? ? ? ? ? ? ? ? 15:8 on frz sidl ? ? ? ? ? 7:0 tgate tckps<2:0> ? ?tcs ? bf80_0e04 t5conclr 31:0 write clears selected bits in t5con, read yields undefined value bf80_0e08 t5conset 31:0 write sets selected bits in t5con, read yields undefined value bf80_0e0c t5coninv 31:0 write inverts selected bits in t5con, read yields undefined value bf80_0e10 tmr5 31:24 ? ? ? ? ? ? ? ? 23:16 ? ? ? ? ? ? ? ? 15:8 tmr5<15:8> 7:0 tmr5<7:0> bf80_0e14 tmr5clr 31:0 write clears selected bits in tmr5, read yields undefined value bf80_0e18 tmr5set 31:0 write sets selected bits in tmr5, read yields undefined value bf80_0e1c tmr5inv 31:0 write inverts selected bits in tmr5, read yields undefined value bf80_0e20 pr5 31:24 ? ? ? ? ? ? ? ? 23:16 ? ? ? ? ? ? ? ? 15:8 pr5<15:8> 7:0 pr5<7:0> bf80_0e24 pr5clr 31:0 write clears selected bits in pr5, read yields undefined value bf80_0e28 pr5set 31:0 write sets selected bits in pr5, read yields undefined value bf80_0e2c pr5inv 31:0 write inverts selected bits in pr5, read yields undefined value table 14-8: timer5 interrupt register summary (1) virtual address name bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 bf88_1060 iec0 23:16 spi1eie oc5ie ic5ie t5ie int4ie oc4ie ic4ie t4ie bf88_1030 ifs0 23:16 spi1eif oc5if ic5if t5if int4if oc4if ic4if t4if bf88_10e0 ipc5 7:0 ? ? ? t5ip<2:0> t5is<1:0> note 1: this summary table contains partial register definitions that only pertain to the timer5 peripheral. refer to the ?pic32mx family reference manual ? (ds61132) for a detailed description of these registers.
pic32mx3xx/4xx ds61143e-page 344 preliminary ? 2008 microchip technology inc. 14.2 control registers register 14-9: t2con, t4con: timer2 and timer4 control register r-x r-x r-x r-x r-x r-x r-x r-x ? ? ? ? ? ? ? ? bit 31 bit 24 r-x r-x r-x r-x r-x r-x r-x r-x ? ? ? ? ? ? ? ? bit 23 bit 16 r/w-0 r/w-0 r/w-0 r-x r-x r-x r-x r-x on frz sidl ? ? ? ? ? bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r-x r/w-0 r-x tgate tckps<2:0> t32 ?tcs ? bit 7 bit 0 legend: r = readable bit w = writable bit p = programmable bit r = reserved bit u = unimplemented bit -n = bit value at por: (?0?, ?1?, x = unknown) bit 31-16 reserved: write ? 0 ?; ignore read bit 15 on: timer on bit 1 = timer is enabled 0 = timer is disabled bit 14 frz: freeze in debug exception mode bit 1 = freeze operation when cpu is in debug exception mode 0 = continue operation when cpu is in debug exception mode note: frz is writable in debug exception mode only, it is forced to ? 0 ? in normal mode. bit 13 sidl: stop in idle mode bit 1 = discontinue operation when device enters idle mode 0 = continue operation in idle mode bit 12-8 reserved: write ? 0 ?; ignore read bit 7 tgate: gated time accumulation enable bit when tcs = 1 : this bit is ignored and read ? 0 ?. when tcs = 0 : 1 = gated time accumulation is enabled 0 = gated time accumulation is disabled bit 6-4 tckps<2:0>: timer input clock prescaler select bits 111 = 1:256 prescale value 110 = 1:64 prescale value 101 = 1:32 prescale value 100 = 1:16 prescale value 011 = 1:8 prescale value 010 = 1:4 prescale value 001 = 1:2 prescale value 000 = 1:1 prescale value
? 2008 microchip technology inc. preliminary ds61143e-page 345 pic32mx3xx/4xx bit 3 t32: 32-bit timer mode select bits 1 = tmrx and tmry form a 32-bit timer 0 = tmrx and tmry form separate 16-bit timers bit 2 reserved: write ? 0 ?; ignore read bit 1 tcs: timer clock source select bit 1 = external clock from txck pin 0 = internal peripheral clock bit 0 reserved: write ? 0 ?; ignore read
pic32mx3xx/4xx ds61143e-page 346 preliminary ? 2008 microchip technology inc. register 14-10: t3con, t5con: timer3 and timer5 control register r-x r-x r-x r-x r-x r-x r-x r-x ? ? ? ? ? ? ? ? bit 31 bit 24 r-x r-x r-x r-x r-x r-x r-x r-x ? ? ? ? ? ? ? ? bit 23 bit 16 r/w-0 r/w-0 r/w-0 r-x r-x r-x r-x r-x on frz sidl ? ? ? ? ? bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r-x r-x r/w-0 r-x tgate tckps<2:0> ? ?tcs ? bit 7 bit 0 legend: r = readable bit w = writable bit p = programmable bit r = reserved bit u = unimplemented bit -n = bit value at por: (?0?, ?1?, x = unknown) bit 31-16 reserved: write ? 0 ?; ignore read bit 15 on: timer on bit 1 = module is enabled 0 = module is disabled bit 14 frz: freeze in debug exception mode bit 1 = freeze operation when cpu is in debug exception mode 0 = continue operation when cpu is in debug exception mode note: frz is writable in debug exception mode only, it is forced to ? 0 ? in normal mode. bit 13 sidl: stop in idle mode bit 1 = discontinue operation when device enters idle mode 0 = continue operation in idle mode bit 12-8 reserved: write ? 0 ?; ignore read bit 7 tgate: gated time accumulation enable bit when tcs = 1 : this bit is ignored and read ? 0 ?. when tcs = 0 : 1 = gated time accumulation is enabled 0 = gated time accumulation is disabled bit 6-4 tckps<1:0>: timer input clock prescaler select bits 111 = 1:256 prescale value 110 = 1:64 prescale value 101 = 1:32 prescale value 100 = 1:16 prescale value 011 = 1:8 prescale value 010 = 1:4 prescale value 001 = 1:2 prescale value 000 = 1:1 prescale value bit 3-2 reserved: write ? 0 ?; ignore read
? 2008 microchip technology inc. preliminary ds61143e-page 347 pic32mx3xx/4xx bit 1 tcs: timer clock source select bit 1 = external clock from txck pin 0 = internal peripheral clock bit 0 reserved: write ? 0 ?; ignore read
pic32mx3xx/4xx ds61143e-page 348 preliminary ? 2008 microchip technology inc. 14.3 modes of operation the 16-bit (default) and 32-bit mode timer peripherals can operate as synchronous timer/counters using inter- nal or external clock sources, or as synchronous gated timers using an internal clock source and external clock/gate pins. each mode is easily configured and described in the following sections. 14.3.1 considerations for all timer modes ? a timer module is disabled and powered off when the on bit (txcon<15>) = 0 , thus providing maximum power savings. all other txcon bits remain unchanged. ? updates to the txcon register should only be performed when the timer module is disabled, on bit (txcon<15>) = 0 . ? a timer continues operating when the cpu goes into idle mode if the ?stop in idle mode? control bit is disabled, sidl (txcon<13>) bit = 0 . if enabled, sidl = 1 , the timer module stops operation while the cpu is in idle mode. ? setting or clearing the on bit (txcon<15>) and any other bits in the txcon register during a single instruction may cause undefined behavior. the user is advised to program the txcon register with the desired settings with one instruc- tion, and then set the on bit in a subsequent instruction. 14.3.2 16-bit internal clock counter/timer mode in this mode, the timer clock source is the internal pbclk (peripheral bus clock), tcs (txcon<1>) = 0 . the 16-bit tmrx count register increments on every internal pbclk cycle when the timer clock prescale is 1:1. the timer generates a timer match event after the tmrx count register matches the prx period register value, then resets to 0x0000 on the next pbclk clock cycle. the timer continues to increment and repeat the period match until the timer is disabled. for further details regarding timer events and interrupts, see section 14.4 timer interrupts . for clock prescale = n (other than 1:1), the timer oper- ates at a clock rate = (pbclk/n); therefore, the tmrx count register increments on every nth pbclk clock cycle. for further details regarding timer prescaler, refer to section 14.3.9 timer clock prescaler . the following steps should be performed to properly configure the 16-bit timer peripherals for timer mode operation: 1. clear on control bit, (txcon<15>) = 0 , to disable timer. 2. configure tckps control bits, (txcon<6:4), to select desired timer clock prescale. 3. set tcs control bit, (txcon<1>) = 0 , to select the internal pbclk clock source. 4. clear tmrx register. 5. load prx register with desired 16-bit match value. 6. if timer interrupts are to be used, refer to section 14.4 timer interrupts for interrupt configuration steps. 7. set on control bit = 1 to enable timer. example 14-1: 16-bit internal clock counter/timer initialization t2con = 0x0; //stop and init timer tmr2 = 0x0; //clear timer register pr2 = 0xffff; //load period register t2conset = 0x8000; // start timer
? 2008 microchip technology inc. preliminary ds61143e-page 349 pic32mx3xx/4xx 14.3.3 16-bit synchronous external clock counter/timer mode in this mode, the timer clock source is an external clock source or pulse applied to the txck pin, tcs (txcon<1>) = 1 . the 16-bit tmrx count register increments on every rising edge of an external clock when the timer clock prescale is 1:1. the timer generates a timer match event after the tmrx count register matches the prx register value, then resets to 0x0000 on the next external clock cycle. the timer continues to increment and repeat the period match until the timer is disabled. for further details regarding timer events and interrupts, see section 14.4 timer interrupts . for clock prescale = n (other than 1:1), the timer operates at a clock rate = (external clock/n); there- fore, the tmrx count register increments on every nth external clock cycle. for further details regarding the timer prescaler, refer to section 14.3.9 timer clock prescaler . the following steps should be performed to properly configure the timer peripheral for synchronous counter mode operation: 1. clear control bit, on (txcon<15>) = 0 , to disable timer. 2. select the desired timer prescaler using bits, tckps<2:0> (txcon<6:4). 3. set control bit, tcs (txcon<1>) = 1 , to select an external clock source. 4. clear timer register, tmrx. 5. load period register, prx, with desired 16-bit match value. 6. if timer interrupts are used, refer to section 14.4 timer interrupts for interrupt configuration steps. 7. set control bit, on (txcon<15>) = 1 , to enable timer. example 14-2: 16-bit synchronous external clock counter/timer initialization 14.3.4 16-bit gated clock counter/ timer mode in this mode, the timer clock source can only be the internal pbclk (peripheral bus clock), tcs (txcon<1>) = 0 . the txck pin provides the gating mechanism to enable and disable the timer counting, tgate (txcon<7>) = 1 . the 16-bit tmrx count reg- ister is enabled on the rising edge of the txck pin and increments on every internal pbclk cycle when the timer clock prescale is 1:1. the timer increments until the tmrx count register matches the prx register value. the tmrx count reg- ister resets to 0x0000 on the next pbclk clock cycle. a timer match event is not generated. the timer contin- ues to increment and repeat the period match until the falling edge of the txck pin or the timer is disabled. on the falling edge of the gate signal, a timer gate event is generated and the tmrx count register stops count- ing, but is not reset to 0x0000. the tmrx count regis- ter must be reset in software. for further details regarding timer events and interrupts, see section 14.4 timer interrupts . for clock prescale = n (other than 1:1), the timer oper- ates at a clock rate = (pbclk/n); therefore, the tmrx count register increments on every nth pbclk clock cycle. for further details regarding timer prescaler, refer to section 14.3.9 timer clock prescaler . the following steps should be performed to properly configure the timer peripheral for gated timer mode operation: 1. clear control bit, on (txcon<15>) = 0 , to disable timer. 2. select the desired timer prescaler using bits, tckps<2:0> (txcon<6:4>). 3. set control bit, tcs (txcon<1>) = 0 , to select the internal clock source. 4. set control bit, tgate (txcon<7>) = 1 . 5. clear timer register, tmrx. 6. load period register, prx, with desired 16-bit match value. 7. if timer interrupts are to be used, refer to section 14.4 timer interrupts for interrupt configuration steps. 8. set control bit, on (txcon<15>) = 1 , to enable timer. note: txck pins not available on 64-pin devices. t3con = 0x0; //stop and init timer t3conset = 0x0072; //prescaler=1:256, //external clock tmr3 = 0x0; //clear timer register pr3 = 0x3fff; //load period register t3conset = 0x8000;//start timer note: txck pins not available on 64-pin devices.
pic32mx3xx/4xx ds61143e-page 350 preliminary ? 2008 microchip technology inc. example 14-3: 16-bit gated clock counter/timer initialization 14.3.5 32-bit internal clock counter/timer mode in this mode, t32 (txcon<3>) = 1 and the timer clock source is the internal pbclk (peripheral bus clock), tcs (txcon<1>) = 0 . the 32-bit tmrxy count regis- ter increments on every internal pbclk cycle when the timer clock prescale is 1:1. the timer generates a timer match event after the tmrxy count register matches the prxy period regis- ter value, then resets to 0x00000000 on the next pbclk clock cycle. the timer continues to increment and repeat the period match until the timer is disabled. for further details regarding timer events and interrupts, see section 14.4 timer interrupts . for clock prescale = n (other than 1:1), the timer oper- ates at a clock rate = (pbclk/n); therefore, the tmrxy count register increments on every nth pbclk clock cycle. for further details regarding the timer prescaler, refer to section 14.3.9 timer clock prescaler . 14.3.6 considerations ? 32-bit timer pairs can be created using timer2 with timer3, or timer4 with timer5. ? with timer2 or timer4 enabled, setting the t32 bit (t2con<3> or t4con<3>) = 1 automatically enables the corresponding timer3 or timer5 module. for this reason, it is not necessary to manually enable timer3 or timer5. ? t2con and t4con control registers are used for configuring the 32-bit timer operations; writes to t3con and t5con are ignored. ? t2ck and t4ck input pins are utilized for the 32- bit gated timer or external synchronous counter operations; t3ck and t5ck are ignored. ? 32-bit timer interrupts use timer3 or timer5 inter- rupt enable bits and interrupt flag bits; timer2 and timer4 interrupt enable and interrupt flag bits are ignored. ? load tmrxy pair by writing the 32-bit value to tmrx. ? load prxy pair by writing the 32-bit value to prx. the following steps should be performed to properly configure the 32-bit timer peripherals for timer mode operation. 1. clear control bit, on (txcon<15>) = 0 , to disable timer. 2. set control bit, t32 (txcon<3>). 3. select the desired timer prescaler using bits tckps<2:0> (txcon<6:4>). 4. set control bit, tcs (txcon<1>) = 0 , to select the internal clock source. 5. clear timer register, tmrxy. 6. load period register, prxy, with desired 32-bit match value. 7. if timer interrupts are used, refer to section 14.4 timer interrupts for interrupt configuration steps. 8. set control bit, on (txcon<15>) = 1 , to enable timer. example 14-4: 32-bit internal clock counter/timer initialization t4con = 0x0; //stop and init timer t4con = 0x00e0; //enable gated mode, //prescaler=1:64, //internal clock tmr4 = 0; //clear timer register pr4 = 0xffff; //load period register t4conset = 0x8000;//start timer t4con = 0x0; //stop timer4 and clear t5con = 0x0; //stop timer5 and clear t4conset = 0x0038; // enable 32-bit mode, // prescaler at 1:8, // internal clock tmr4 = 0x0; // clear tmr4 and tmr5 // same as tmr4 = 0x0 pr4 = 0xffffffff; // load pr4 and pr5 // with 32-bit value // same as pr4=0xffffffff t4conset = 0x8000; // start timer
? 2008 microchip technology inc. preliminary ds61143e-page 351 pic32mx3xx/4xx 14.3.7 32-bit synchronous external clock counter/timer mode in this mode, t32 (txcon<3>) = 1 and the timer clock source is an external clock source or pulse applied to the txck pin, tcs (txcon<1>) = 1 . the 32-bit tmrxy count register increments on every synchronized rising edge of an external clock when the timer clock prescale is 1:1. the timer generates a timer match event after the tmrxy count register matches the prxy register value, then resets to 0x00000000 on the next external clock cycle. the timer continues to increment and repeat the period match until the timer is disabled. for further details regarding timer events and interrupts, see section 14.4 timer interrupts . for clock prescale = n (other than 1:1), the timer operates at a clock rate = (external clock/n); there- fore, the tmrxy count register increments on every nth external clock cycle. for further details regarding timer prescaler, refer to section 14.3.9 timer clock prescaler . the following steps should be performed to properly configure the 32-bit timer peripheral for synchronous counter mode operation: 1. clear control bit, on (txcon<15>) = 0 , to disable timer. 2. set control bit, t32 (txcon<3>). 3. select the desired timer prescaler using bits tckps<2:0> (txcon<6:4>). 4. set control bit, tcs (txcon<1>) = 1 , to select an external clock source. 5. clear timer register, tmrx. 6. load period register, prx, with desired 32-bit match value. 7. if timer interrupts are used, refer to section 14.4 timer interrupts for interrupt configuration steps. 8. set control bit, on (txcon<15>) = 1 , to enable timer. example 14-5: 32-bit synchronous external clock counter/timer initialization 14.3.8 32-bit gated clock counter/timer mode in this mode, the timer clock source is the internal pbclk (peripheral bus clock), tcs (txcon<1>) = 0 . the txck pin provides the gating mechanism to enable and disable the timer counting, tgate (txcon<7>) = 1 . the 32-bit tmrxy count register is enabled on the rising edge of the txck pin and incre- ments on every internal pbclk cycle when the timer clock prescale is 1:1. the timer increments until the tmrxy count register matches the prxy register value. the tmrxy count register resets to 0x00000000 on the next pbclk clock cycle. a timer match event is not generated. the timer continues to increment and repeat the period match until the falling edge of the txck pin or the timer is dis- abled. on the falling edge of the gate signal, a timer gate event is generated and the tmrxy count register stops counting, but is not reset to 0x00000000. the tmrxy count register must be reset in software. for further details regarding timer events and interrupts, see section 14.4 timer interrupts . for clock prescale = n (other than 1:1), the timer oper- ates at a clock rate = (pbclk/n); therefore, the tmrxy count register increments on every nth timer clock cycle. for further details regarding timer prescaler, refer to section 14.3.9 timer clock prescaler . the following steps should be performed to properly configure the timer peripheral for gated timer mode operation: 1. clear control bit, on (txcon<15>) = 0 , to disable timer. 2. set control bit, t32 (txcon<3>). 3. select the desired timer prescaler using bits tckps<2:0> (txcon<6:4>). 4. set control bit, tcs (txcon<1>) = 0 , to select the internal clock source. 5. set control bit, tgate (txcon<7>) = 1 . 6. clear timer register, tmrx. 7. load period register, prx, with desired 32-bit match value. 8. set control bit, on (txcon<15>) = 1 , to enable timer. note: txck pins not available on 64-pin devices. t2con = 0x0; //stop timer2 and clear t3con = 0x0; //stop timer3 and clear t2conset = 0x006a //32-bit mode, //external clock, //prescale=1:64 tmr2 = 0x0; // clear tmr2 and tmr3 // same as tmr2 = 0x0 pr2 = 0xffffffff; // load pr2 and pr3 // same as pr2=0xffffffff t2conset = 0x8000; // start timer note: txck pins not available on 64-pin devices.
pic32mx3xx/4xx ds61143e-page 352 preliminary ? 2008 microchip technology inc. example 14-6: 32-bit gated clock counter/timer initialization 14.3.9 timer clock prescaler timer clock prescale bits, tckps<1:0> (txcon<6:4>), are used to divide the timer clock source permitting the tmr register to increment on every 1, 2, 4, 8, 16, 32, 64, or 256 (pbclk or external) clock cycles. for example, if the clock prescale is 1:8, then the timer increments on every 8th timer clock cycle. 14.3.10 considerations associated with the clock prescale selection bits is a prescale counter. the timer prescale counter is cleared when any of the following conditions occur: 1. any device reset, except a power-on reset. 2. the timer is disabled. 3. any write to the tmr register. ? when the timer clock source is external and the timer clock prescale = n (other than 1:1), 2 to 3 external clock cycles are required, after the timer on bit is set = 1 , before the tmrx count register increments. ? after a timer match event (tmrx = prx) and depending on the timer clock prescale setting n (other than 1:1), the timer will require n additional (pbclk or external) clock cycles before the tmrx counter register resets to 0x0000. reading the tmrx count register just after the timer match event, but before the tmrx count register is reset, will return the timer match value. note: when the timer clock source is external and the timer clock prescale = n (other than 1:1), 2 to 3 external clock cycles are required to reset and synchronize the prescaler. t4con = 0x0; //stop timer4 and clear t5con = 0x0; //stop timer5 and clear t4conset = 0x00c8; //32-bit mode, //gate enable, //internal clock, //1:16 prescale tmr4 = 0x0; //clear tmr4 and tmr5 //same as tmr4 = 0x0 pr4 = 0xffffffff; //load pr4 and pr5 regs //same as pr4 =0xffffffff t4conset = 0x8000; //start 32-bit timer
? 2008 microchip technology inc. preliminary ds61143e-page 353 pic32mx3xx/4xx 14.4 timer interrupts a timer can generate an interrupt on a period match event or a gate event, caused by the falling edge of the external gate signal. a timer sets its corresponding interrupt flag bit, txif, whenever the timer event is generated. refer to a specific timer mode for details regarding these event conditions. when a timer event is generated, the inter- rupt flag bit is set within 1 pbclk + 2 sysclk cycles. if the timer interrupt enable bit is set, txie = 1 , an interrupt is generated. the timer module is enabled as a source of interrupts via the respective timer interrupt enable bit, txie (iecx). the timer interrupt flag, txif (ifsx), must be cleared in software. the interrupt priority level bits and interrupt subpriority level bits must be also be configured: ? txip<2:0> (ipcx<4:2>) ? txis<1:0> (ipcx<1:0) setting the timer?s interrupt priority level = 0 effectively disables the timer?s ability to generate an interrupt. in addition to enabling the timer interrupt, an interrupt service routine, isr, is required. example 14-7 through example 14-9 show a partial code example of an isr. example 14-7: 16-bit timer interrupt and priorities example 14-8: 32-bit timer interrupt and priorities t2con = 0x0; // stop timer and clear control register, // prescaler at 1:1,internal clock source tmr2 = 0x0; // clear timer register pr2 = 0xffff; // load period register ipc2set = 0x0000000c; // set priority level=3 ipc2set = 0x00000001; // set subpriority level=1 // could have also done this in single // operation by assigning ipc2set = 0x0000000d ifs0clr = 0x00000100; // clear timer interrupt status flag iec0set = 0x00000100; // enable timer interrupts t2conset = 0x8000; // start timer t4con = 0x0; // stop 16-bit timer4 and clear control register t5con = 0x0; // stop 16-bit timer5 and clear control register t4conset = 0x0038; // enable 32-bit mode, prescaler at 1:8, // internal clock source tmr4= 0x0; // clear contents of the tmr4 and tmr5 // registers in one 32-bit load operation pr4 = 0xffffffff; // load pr4 and pr5 registers with 32-bit value // 0xffffffff in one 32-bit load operation ipc5set = 0x00000004; // set priority level=1 and ipc5set = 0x00000001; // set subpriority level=1 // could have also done this in single // operation by assigning ipc5set = 0x00000005 ifs0clr = 0x10000000; // clear the timer5 interrupt status flag iec0set = 0x10000000; // enable timer5 interrupts t4conset = 0x8000; // start timer
pic32mx3xx/4xx ds61143e-page 354 preliminary ? 2008 microchip technology inc. example 14-9: timer isr 14.5 i/o pin configuration the table below provides a summary of i/o pin resources associated with the timer modules. the table shows the settings required to make an i/o pin available for a specific timer module. note: the timer isr code example shows mplab ? c32 compiler specific syntax. refer to your compiler manual regarding support for isrs. void __isr(_timer_2_vector, ipl3) t2_interrupt_isr(void) { ... perform application specific operations in response to the interrupt ifs0clr = 0x00000100; // be sure to clear the timer2 interrupt status } void__isr(timer_5_vector. ipl1) t5_interrupt_isr(void) { ...perform application specific operations in response to the interrupt ifs0clr = 0x10000000; // be sure to clear the timer5 interrupt status } table 14-2: i/o pin configuration for use with timer modules required settings for module pin control i/o pin name required module enable (2) bit field (2) tris pin type buffer type description t2ck yes (1) on tcs, tgate input i st timer2 external clock/gate input t3ck yes 1) on tcs, tgate input i st timer3 external clock/gate input t4ck yes (1) on tcs, tgate input i st timer4 external clock/gate input t5ck yes (1) on tcs, tgate input i st timer5 external clock/gate input legend: cmos = cmos compatible input or output st = schmitt trigger input with cmos levels i = input o = output note 1: these pins are only required for modes usi ng gated timer or external clock inputs. otherwise, these pins can be used for general purpose i/o and require the user to set the corresponding tris register bits. txck pins not available on 64-pin devices. 2: these bits are located in the txcon register.
? 2008 microchip technology inc. preliminary ds61143e-page 355 pic32mx3xx/4xx 15.0 input capture the input capture module is useful in applications requiring frequency (period) and pulse measurement. the pic32mx3xx/4xx devices support up to five input capture channels. the input capture module captures the 16-bit or 32-bit value of the selected time base registers when an event occurs at the icx pin. the events that cause a capture event are listed below in three categories: 1. simple capture event modes - capture timer value on every falling edge of input at icx pin - capture timer value on every rising edge of input at icx pin 2. capture timer value on every edge (rising and falling) 3. capture timer value on every edge (rising and falling), specified edge first. 4. prescaler capture event modes - capture timer value on every 4th rising edge of input at icx pin - capture timer value on every 16th rising edge of input at icx pin each input capture channel can select between one of two 16-bit timers (timer2 or timer3) for the time base, or two 16-bit timers (timer2 and timer3) together to form a 32-bit timer. the selected timer can use either an internal or external clock. other operational features include: ? device wake-up from capture pin during cpu sleep and idle modes ? interrupt on input capture event ? 4-word fifo buffer for capture values - interrupt optionally generated after 1, 2, 3 or 4 buffer locations are filled ? input capture can also be used to provide additional sources of external interrupts figure 15-1: input capture block diagram note: this data sheet summarizes the features of the pic32mx3xx/4xx family of devices. it is not intended to be a comprehensive refer- ence source. refer to the ?pic32mx family reference manual? (ds61132) for a detailed description of this peripheral. prescaler 1, 4, 16 edge detect fifo control interrupt event generation icxbuf<31:16> interrupt timer 3 timer 2 icxcon icm<2:0> icm<2:0> icfedge ici<1:0> icbne icov icx input 0 1 icxbuf<15:0> data space interface peripheral data bus icc32 ictmr
pic32mx3xx/4xx ds61143e-page 356 preliminary ? 2008 microchip technology inc. table 15-1: input capture1 register summary table 15-2: input capture1 interrupt register summary (1) table 15-3: input capture2 register summary table 15-4: input capture2 interrupt register summary (1) virtual address name bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 bf80_2000 ic1con 31:24 ? ? ? ? ? ? ? ? 23:16 ? ? ? ? ? ? ? ? 15:8 on frz sidl ? ? ? icfedge icc32 7:0 ictmr ici<1:0> icov icbne icm<2:0> bf80_2004 ic1conclr 31:0 write clears selected bits in ic1con, read yields an undefined value bf80_2008 ic1conset 31:0 write sets selected bits in ic1con, read yields an undefined value bf80_200c ic1coninv 31:0 write inverts selected bits in ic1con, read yields an undefined value bf80_2010 ic1buf 31:24 ic1buf<31:24> 23:16 ic1buf<23:16> 15:8 ic1buf<15:8> 7:0 ic1buf<7:0> virtual address name bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 bf88_1060 iec0 7:0 int1ie oc1ie ic1ie t1ie int0ie cs1ie cs0ie ctie bf88_1030 ifs0 7:0 int1if oc1if ic1if t1if int0if cs1if cs0if ctif bf88_10a0 ipc1 15:8 ? ? ? ic1ip<2:0> 15:8 ? note 1: this summary table contains partial register definitions that only pertain to the input capture1 peripheral. refer to the ? pic32mx family reference manual ? (ds61132) for a detailed description of these registers. virtual address name bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 bf80_2200 ic2con 31:24 ? ? ? ? ? ? ? ? 23:16 ? ? ? ? ? ? ? ? 15:8 on frz sidl ? ? ? icfedge icc32 7:0 ictmr ici<1:0> icov icbne icm<2:0> bf80_2204 ic2conclr 31:0 write clears selected bits in ic2con, read yields an undefined value bf80_2208 ic2conset 31:0 write sets selected bits in ic2con, read yields an undefined value bf80_220c ic2coninv 31:0 write inverts selected bits in ic2con, read yields an undefined value bf80_2210 ic2buf 31:24 ic2buf<31:24> 23:16 ic2buf<23:16> 15:8 ic2buf<15:8> 7:0 ic2buf<7:0> virtual address name bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 bf88_1060 iec0 15:8 int3ie oc3ie ic3ie t3ie int2ie oc2ie ic2ie t2ie bf88_1030 ifs0 15:8 int3if oc3if ic3if t3if int2if oc2if ic2if t2if bf88_10b0 ipc2 15:8 ? ? ? ic2ip<2:0> ic2is<1:0> note 1: this summary table contains partial register definitions that only pertain to the input capture5 peripheral. refer to the ?pic32mx family reference manual? (ds61132) for a detailed description of these registers.
? 2008 microchip technology inc. preliminary ds61143e-page 357 pic32mx3xx/4xx table 15-5: input capture3 register summary table 15-6: input capture3 interrupt register summary (1) table 15-7: input capture4 register summary table 15-8: input capture4 interrupt register summary (1) virtual address name bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 bf80_2400 ic3con 31:24 ? ? ? ? ? ? ? ? 23:16 ? ? ? ? ? ? ? ? 15:8 on frz sidl ? ? ? icfedge icc32 7:0 ictmr ici<1:0> icov icbne icm<2:0> bf80_2404 ic3conclr 31:0 write clears selected bits in ic3con, read yields an undefined value bf80_2408 ic3conset 31:0 write sets selected bits in ic3con, read yields an undefined value bf80_240c ic3coninv 31:0 write inverts selected bits in ic3con, read yields an undefined value bf80_2410 ic3buf 31:24 ic3buf<31:24> 23:16 ic3buf<23:16> 15:8 ic3buf<15:8> 7:0 ic3buf<7:0> virtual address name bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 bf88_1060 iec0 15:8 int3ie oc3ie ic3ie t3ie int2ie oc2ie ic2ie t2ie bf88_1030 ifs0 15:8 int3if oc3if ic3if t3if int2if oc2if ic2if t2if bf88_10c0 ipc3 15:8 ? ? ? ic3ip<2:0> ic3is<1:0> note 1: this summary table contains partial register definitions that only pertain to the input capture3 peripheral. refer to the ? pic32mx family reference manual ? (ds61132) for a detailed description of these registers. virtual address name bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 bf80_2600 ic4con 31:24 ? ? ? ? ? ? ? ? 23:16 ? ? ? ? ? ? ? ? 15:8 on frz sidl ? ? ? icfedge icc32 7:0 ictmr ici<1:0> icov icbne icm<2:0> bf80_2604 ic4conclr 31:0 write clears selected bits in ic4con, read yields an undefined value bf80_2608 ic4conset 31:0 write sets selected bits in ic4con, read yields an undefined value bf80_260c ic4coninv 31:0 write inverts selected bits in ic4con, read yields an undefined value bf80_2610 ic4buf 31:24 ic4buf<31:24> 23:16 ic4buf<23:16> 15:8 ic4buf<15:8> 7:0 ic4buf<7:0> virtual address name bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 bf88_1060 iec0 23:16 spi1eie oc5ie ic5ie t5ie int4ie oc4ie ic4ie t4ie bf88_1030 ifs0 23:16 spi1eif oc5if ic5if t5if int4if oc4if ic4if t4if bf88_10d0 ipc4 15:8 ? ? ? ic4ip<2:0> ic4is<1:0> note 1: this summary table contains partial register definitions that only pertain to the input capture4 peripheral. refer to the ?pic32mx family reference manual ? (ds61132) for a detailed description of these registers.
pic32mx3xx/4xx ds61143e-page 358 preliminary ? 2008 microchip technology inc. table 15-9: input capture5 register summary table 15-10: input capture5 interrupt register summary (1) virtual address name bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 bf80_2800 ic5con 31:24 ? ? ? ? ? ? ? ? 23:16 ? ? ? ? ? ? ? ? 15:8 on frz sidl ? ? ? icfedge icc32 7:0 ictmr ici<1:0> icov icbne icm<2:0> bf80_2804 ic5conclr 31:0 write clears selected bits in ic5con, read yields an undefined value bf80_2808 ic5conset 31:0 write sets selected bits in ic5con, read yields an undefined value bf80_280c ic5coninv 31:0 write inverts selected bits in ic5con, read yields an undefined value bf80_2810 ic5buf 31:24 ic5buf<31:24> 23:16 ic5buf<23:16> 15:8 ic5buf<15:8> 7:0 ic5buf<7:0> virtual address name bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 bf88_1060 iec0 23:16 spi1eie oc5ie ic5ie t5ie int4ie oc4ie ic4ie t4ie bf88_1030 ifs0 23:16 spi1eif oc5if ic5if t5if int4if oc4if ic4if t4if bf88_10e0 ipc5 15:8 ? ? ? ic5ip<2:0> ic5is<1:0> note 1: this summary table contains partial register definitions that only pertain to the input capture5 peripheral. refer to the ?pic32mx family reference manual ? (ds61132) for a detailed description of these registers.
? 2008 microchip technology inc. preliminary ds61143e-page 359 pic32mx3xx/4xx register 15-1: ic x con: input capture x control register r-x r-x r-x r-x r-x r-x r-x r-x ? ? ? ? ? ? ? ? bit 31 bit 24 r-x r-x r-x r-x r-x r-x r-x r-x ? ? ? ? ? ? ? ? bit 23 bit 16 r/w-0 r/w-0 r/w-0 r-x r-x r-x r/w-0 r/w-0 on frz sidl ? ? ? icfedge icc32 bit 15 bit 8 r/w-0 r/w-0 r/w-0 r-0 r-0 r/w-0 r/w-0 r/w-0 ictmr ici<1:0> icov icbne icm<2:0> bit 7 bit 0 legend: r = readable bit w = writable bit p = programmable bit r = reserved bit u = unimplemented bit -n = bit value at por: (?0?, ?1?, x = unknown) bit 31-16 reserved: write ? 0 ?; ignore read bit 15 on: on bit 1 = module enabled 0 = disable and reset module, disable clocks, disable interrupt generation, and allow sfr modifications bit 14 frz: freeze in debug mode control bit 1 = freeze module operation when in debug mode 0 = do not freeze module operation when in debug mode note: frz is writable in debug exception mode only, it is forced to ? 0 ? in normal mode. bit 13 sidl: stop in idle control bit 1 = halt in cpu idle mode 0 = continue to operate in cpu idle mode bit 12-10 reserved: write ? 0 ?; ignore read bit 9 icfedge: first capture edge select bit ( only used in mode 6, icxm = 110 ) 1 = capture rising edge first 0 = capture falling edge first bit 8 icc32: 32-bit capture select bit 1 = 32-bit timer resource capture 0 = 16-bit timer resource capture bit 7 ictmr: timer select bit (does not affect timer selection when icxc32 (icxcon<8>) is ? 1 ?) 0 = timer3 is the counter source for capture 1 = timer2 is the counter source for capture bit 6-5 ici<1:0>: interrupt control bits 11 = interrupt on every fourth capture event 10 = interrupt on every third capture event 01 = interrupt on every second capture event 00 = interrupt on every capture event
pic32mx3xx/4xx ds61143e-page 360 preliminary ? 2008 microchip technology inc. bit 4 icov: input capture overflow status flag bit (read-only) 1 = input capture overflow occurred 0 = no input capture overflow occurred bit 3 icbne: input capture buffer not empty status bit (read-only) 1 = input capture buffer is not empty; at least one more capture value can be read 0 = input capture buffer is empty bit 2-0 icm<2:0>: input capture mode select bits 111 = interrupt only mode 110 = simple capture event mode ? every edge, specified edge first and every edge thereafter 101 = prescaled capture event mode ? every 16 th rising edge 100 = prescaled capture event mode ? every 4 th rising edge 011 = simple capture event mode ? every rising edge 010 = simple capture event mode ? every falling edge 001 = edge detect mode ? every edge (rising and falling) 000 = capture disable mode register 15-1: ic x con: input capture x control register (continued)
? 2008 microchip technology inc. preliminary ds61143e-page 361 pic32mx3xx/4xx register 15-2: ic x buf: input capture x buffer register r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 icxbuf<31:24> bit 31 bit 24 r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 icxbuf<23:16> bit 23 bit 16 r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 icxbuf<15:8> bit 15 bit 8 r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 icxbuf<7:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit -n = bit value at por: (?0?, ?1?, x = unknown) bit 31-0 icxbuf<31:0>: buffer register bits value of the current captured input timer count
pic32mx3xx/4xx ds61143e-page 362 preliminary ? 2008 microchip technology inc. 15.1 timer selection the input capture module can select between one of two 16-bit timers for the time base, or two 16-bit timers together to form a 32-bit timer. setting ictmr (icxcon<7>) to ? 0 ? selects the timer3 for capture. setting ictmr (icxcon<7>) to 1 selects the timer2 for capture. an input capture channel configured to support 32-bit capture, may use a 32-bit timer resource for capture. by setting icc32 (icxcon<8>) to ? 1 ?, a 32-bit timer resource is captured. the 32-bit timer resource is routed into the module using the existing 16-bit timer inputs. the timers clock can be setup using the internal periph- eral clock source, or using a synchronized external clock source applied at the txck pin. 15.2 simple capture event modes these modes are specified by setting the icm (icxcon<2:0>) bits to ? 010 ?, ? 011 ?, or ? 110 ?. setting icm = ? 011 ? configures the module to capture the timer value on any rising edge of the capture input. icm = ? 010 ? configures the module to capture the timer on any falling edge of the capture input. setting icm = ? 110 ? configures the channel to capture the timer on every transition of the capture input, beginning with the edge specified by icfedge (icxcon<9>). in simple cap- ture event mode, the prescaler is not used. see figure 15-2 for simplified timing diagrams of a simple capture event. an input capture interrupt event is generated after one, two, three or four timer count captures, as configured by ici (icxcon<6:5>). figure 15-2: simple capture event timing diagram capture every rising edge 15.3 prescaled capture event modes in prescaled capture event mode, the input capture module triggers a capture event on either every fourth or every sixteenth rising edge. these modes are selected by setting the icm (icxcon<2:0>) bits to ? 100 ? or ? 101 ?, respectively. note: since the capture input must be synchro- nized to the peripheral clock, the module captures the timer count value, which is valid 2-3 peripheral clock cycles (t pb ) after the capture event. n n+1 n+2 m m+1 m+2 m+3 m+4 m+5 n + 2 m + 3 peripheral clock timer count icx input synchronized capture capture data capture interrupt note: since the capture input must be synchro- nized to the peripheral clock, the timer count value is captured, which is valid 2-3 peripheral clock periods after the capture event.
? 2008 microchip technology inc. preliminary ds61143e-page 363 pic32mx3xx/4xx figure 15-3 depicts a capture event when the input capture module is in prescaler capture event mode. figure 15-3: prescaler captu re event timing diagram 15.4 edge detect (hall sensor) mode in edge detect mode, the input capture module cap- tures a timer count value on every edge of the capture input. edge detect mode is selected by setting the icm bit to ? 001 ?. in this mode, the capture prescaler is not used and the capture overflow bit, icov (icxcon<4>) is not updated. in this mode, the interrupt control bits (ici, icxcon<6:5>) are ignored and an interrupt event is generated for every timer count capture 15.5 interrupt only mode when the input capture module is set for interrupt only mode (icm = ? 111 ?) and the device is in sleep or idle mode, the capture input functions as an interrupt pin. any rising edge on the capture input triggers an interrupt. no timer values are captured and the fifo buffer is not updated. when the device leaves sleep or idle mode, the interrupt signal is deasserted. in this mode, since no timer values are captured, the timer select bit ictmr (icxcon<7>) is ignored and there is no need to configure the timer source. a wake- up interrupt is generated on the first rising edge, there- fore the interrupt control bits ici (icxcon<6:5>) are also ignored. the prescaler is not used in this mode. note: it is recommended that the user disable (i.e., clear on bit, icxcon<15>) the capture module before switching to prescaler cap- ture event mode. simply switching to pres- caler capture event mode from another active mode does not reset the prescaler and may cause an inadvertent capture event. n n + 1 n + 2 n + 3 n + 4 1 2 3 4 n + 2 t icx _ in _ l t icx _ in _ h t pb peripheral clock timer count capture input prescaler count prescaler output synchronized capture capture data capture interrupt
pic32mx3xx/4xx ds61143e-page 364 preliminary ? 2008 microchip technology inc. example 15-1: input capture example code /* the following code segment initialized the timer and setup the input capture module. */ ... //initialize timer 2 t2con = 0x0 // stop and init timer tmr2 = 0x0; // clear timer register pr2 = 0x7000; // load period register t2conset = 0x8000;// start timer // init ic1 module ic1con = 0x8081;//enable module, use timer 2, //capture mode 1 (capture every edge) ... //read the capture data if available int cap_data; while( ic1conbits.icbne ) // while data available in capture fifo { cap_data = ic1buf; ... //process data } ...
? 2008 microchip technology inc. preliminary ds61143e-page 365 pic32mx3xx/4xx 16.0 output compare the output compare module (ocmp) is used to gen- erate a single pulse or a train of pulses in response to selected time base events. for all modes of operation, the ocmp module compares the values stored in the ocxr and/or the ocxrs registers to the value in the selected timer. when a match occurs, the ocmp mod- ule generates an event based on the selected mode of operation. the following are some of the key features: ? multiple output compare modules in a device ? programmable interrupt generation on compare event ? single and dual compare modes ? single and continuous output pulse generation ? pulse-width modulation (pwm) mode ? hardware-based pwm fault detection and auto- matic output disable ? programmable selection of 16-bit or 32-bit time bases. ? can operate from either of two available 16-bit time bases or a single 32-bit time base. figure 16-1: output comp are module block diagram note: this data sheet summarizes the features of the pic32mx3xx/4xx family of devices. it is not intended to be a comprehensive refer- ence source. refer to the ?pic32mx family reference manual? (ds61132) for a detailed description of this peripheral. ocxr (1) comparator output logic q s r ocm<2:0> output enable ocx (1) set flag bit ocxif (1) ocxrs (1) mode select 3 note 1: where ?x? is shown, reference is made to the regi sters associated with the respective output compare channels 1 through 5. 2: the ocfa pin controls the oc1-oc4 channels. the ocfb pin controls the oc5 channel. 3: each output compare channel can use one of two selectable 16-bit time bases or a single 32-bit timer base. 0 1 octsel 0 1 16 16 ocfa or ocfb (see note 2 ) tmr register inputs from time bases (see note 3 ). period match signals from time bases (see note 3 ).
pic32mx3xx/4xx ds61143e-page 366 preliminary ? 2008 microchip technology inc. 16.1 output compare registers table 16-1: output compare sfr summary virtual address name bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 bf80_3000 oc1con 31:24 ? ? ? ? ? ? ? ? 23:16 ? ? ? ? ? ? ? ? 15:8 on frz sidl ? ? ? ? ? 7:0 ? ? oc32 ocflt octsel ocm<2:0> bf80_3004 oc1conclr 31:0 write clears selected bits in oc1con, read yields an undefined value. bf80_3008 oc1conset 31:0 write sets selected bits in oc1con, read yields an undefined value. bf80_300c oc1coninv 31:0 write inverts selected bits in oc1con, read yields an undefined value. bf80_3010 oc1r 31:24 oc1r<31:24> 23:16 oc1r<23:16> 15:8 oc1r<15:8> 7:0 oc1r<7:0> bf80_3014 oc1rclr 31:0 write clears selected bits in oc1r, read yields an undefined value. bf80_3018 oc1rset 31:0 write sets selected bits in oc1r, read yields an undefined value. bf80_301c oc1rinv 31:0 write inverts selected bits in oc1r, read yields an undefined value. bf80_3020 oc1rs 31:24 oc1rs<31:24> 23:16 oc1rs<23:16> 15:8 oc1rs<15:8> 7:0 oc1rs<7:0> bf80_3024 oc1rsclr 31:0 write clears selected bits in oc1rs, read yields an undefined value. bf80_3028 oc1rsset 31:0 write sets selected bits in oc1rs, read yields an undefined value. bf80_302c oc1rsinv 31:0 write inverts selected bits in oc1rs, read yields an undefined value. table 16-2: output compare1 interrupt register summary (1) virtual address name bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 bf88_1060 iec0 7:0 int1ie oc1ie ic1ie t1ie int0ie cs1ie cs0ie ctie bf88_1030 ifs0 7:0 int1if oc1if ic1if t1if int0if cs1if cs0if ctif bf88_10a0 ipc1 23:16 ? ? ? oc1ip<2:0> oc1is<1:0> note 1: this summary table contains partial register definitions that only pertain to the output compare1 peripheral. refer to the ? pic32mx family reference manual ? (ds61132) for a detailed description of these registers.
? 2008 microchip technology inc. preliminary ds61143e-page 367 pic32mx3xx/4xx table 16-3: output compare2 sfr summary virtual address name bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 bf80_3200 oc2con 31:24 ? ? ? ? ? ? ? ? 23:16 ? ? ? ? ? ? ? ? 15:8 on frz sidl ? ? ? ? ? 7:0 ? ? oc32 ocflt octsel ocm<2:0> bf80_3204 oc2conclr 31:0 write clears selected bits in oc2con, read yields an undefined value. bf80_3208 oc2conset 31:0 write sets selected bits in oc2con, read yields an undefined value. bf80_320c oc2coninv 31:0 write inverts selected bits in oc2con, read yields an undefined value. bf80_3210 oc2r 31:24 oc2r<31:24> 23:16 oc2r<23:16> 15:8 oc2r<15:8> 7:0 oc2r<7:0> bf80_3214 oc2rclr 31:0 write clears selected bits in oc2r, read yields an undefined value. bf80_3218 oc2rset 31:0 write sets selected bits in oc2r, read yields an undefined value. bf80_321c oc2rinv 31:0 write inverts selected bits in oc2r, read yields an undefined value. bf80_3220 oc2rs 31:24 oc2rs<31:24> 23:16 oc2rs<23:16> 15:8 oc2rs<15:8> 7:0 oc2rs<7:0> bf80_3224 oc2rsclr 31:0 write clears selected bits in oc2rs, read yields an undefined value. bf80_3228 oc2rsset 31:0 write sets selected bits in oc2rs, read yields an undefined value. bf80_322c oc2rsinv 31:0 write inverts selected bits in oc2rs, read yields an undefined value. table 16-4: output compare2 interrupt register summary (1) virtual address name bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 bf88_1060 iec0 15:8 int3ie oc3ie ic3ie t3ie int2ie oc2ie ic2ie t2ie bf88_1030 ifs0 15:8 int3if oc3if ic3if t3if int2if oc2if ic2if t2if bf88_10b0 ipc2 23:16 ? ? ? oc2ip<2:0> oc2is<1:0> note 1: this summary table contains partial register definitions that only pertain to the output compare2 peripheral. refer to the pic3 2mx family ref- erence manual (ds61132) for a detailed description of these registers.
pic32mx3xx/4xx ds61143e-page 368 preliminary ? 2008 microchip technology inc. table 16-5: output compare3 sfr summary virtual address name bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 bf80_3400 oc3con 31:24 ? ? ? ? ? ? ? ? 23:16 ? ? ? ? ? ? ? ? 15:8 on frz sidl ? ? ? ? ? 7:0 ? ? oc32 ocflt octsel ocm<2:0> bf80_3404 oc3conclr 31:0 write clears selected bits in oc3con, read yields an undefined value. bf80_3408 oc3conset 31:0 write sets selected bits in oc3con, read yields an undefined value. bf80_340c oc3coninv 31:0 write inverts selected bits in oc3con, read yields an undefined value. bf80_3410 oc3r 31:24 oc3r<31:24> 23:16 oc3r<23:16> 15:8 oc3r<15:8> 7:0 oc3r<7:0> bf80_3414 oc3rclr 31:0 write clears selected bits in oc3r, read yields an undefined value. bf80_3418 oc3rset 31:0 write sets selected bits in oc3r, read yields an undefined value. bf80_341c oc3rinv 31:0 write inverts selected bits in oc3r, read yields an undefined value. bf80_3420 oc3rs 31:24 oc3rs<31:24> 23:16 oc3rs<23:16> 15:8 oc3rs<15:8> 7:0 oc3rs<7:0> bf80_3424 oc3rsclr 31:0 write clears selected bits in oc3rs, read yields an undefined value bf80_3428 oc3rsset 31:0 write sets selected bits in oc3rs, read yields an undefined value bf80_342c oc3rsinv 31:0 write inverts selected bits in oc3rs, read yields an undefined value table 16-6: output compare3 interrupt register summary (1) virtual address name bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 bf88_1060 iec0 15:8 int3ie oc3ie ic3ie t3ie int2ie oc2ie ic2ie t2ie bf88_1030 ifs0 15:8 int3if oc3if ic3if t3if int2if oc2if ic2if t2if bf88_10c0 ipc3 23:16 ? ? ? oc3ip<2:0> oc3is<1:0> note 1: this summary table contains partial register definitions that only pertain to the output compare3 peripheral. refer to the ? pic32mx family reference manual ? (ds61132) for a detailed description of these registers.
? 2008 microchip technology inc. preliminary ds61143e-page 369 pic32mx3xx/4xx table 16-7: output compare4 sfr summary virtual address name bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 bf80_3600 oc4con 31:24 ? ? ? ? ? ? ? ? 23:16 ? ? ? ? ? ? ? ? 15:8 on frz sidl ? ? ? ? ? 7:0 ? ? oc32 ocflt octsel ocm<2:0> bf80_3604 oc4conclr 31:0 write clears selected bits in oc4con, read yields an undefined value bf80_3608 oc4conset 31:0 write sets selected bits in oc4con, read yields an undefined value bf80_360c oc4coninv 31:0 write inverts selected bits in oc4con, read yields an undefined value bf80_3610 oc4r 31:24 oc4r<31:24> 23:16 oc4r<23:16> 15:8 oc4r<15:8> 7:0 oc4r<7:0> bf80_3614 oc4rclr 31:0 write clears selected bits in oc4r, read yields an undefined value bf80_3618 oc4rset 31:0 write sets selected bits in oc4r, read yields an undefined value bf80_361c oc4rinv 31:0 write inverts selected bits in oc4r, read yields an undefined value bf80_3620 oc4rs 31:24 oc4rs<31:24> 23:16 oc4rs<23:16> 15:8 oc4rs<15:8> 7:0 oc4rs<7:0> bf80_3624 oc4rsclr 31:0 write clears selected bits in oc4rs, read yields an undefined value bf80_3628 oc4rsset 31:0 write sets selected bits in oc4rs, read yields an undefined value bf80_362c oc4rsinv 31:0 write inverts selected bits in oc4rs, read yields an undefined value table 16-8: output compare4 interrupt register summary (1) virtual address name bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 bf88_1060 iec0 23:16 spi1eie oc5ie ic5ie t5ie int4ie oc4ie ic4ie t4ie bf88_1030 ifs0 23:16 spi1eif oc5if ic5if t5if int4if oc4if ic4if t4if bf88_10d0 ipc4 23:16 ? ? ? oc4ip<2:0> oc4is<1:0> note 1: this summary table contains partial register definitions that only pertain to the output compare4 peripheral. refer to the ?pic32mx family reference manual ? (ds61132) for a detailed description of these registers.
pic32mx3xx/4xx ds61143e-page 370 preliminary ? 2008 microchip technology inc. table 16-9: output compare5 sfr summary virtual address name bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 bf80_3800 oc5con 31:24 ? ? ? ? ? ? ? ? 23:16 ? ? ? ? ? ? ? ? 15:8 on frz sidl ? ? ? ? ? 7:0 ? ? oc32 ocflt octsel ocm<2:0> bf80_3804 oc5conclr 31:0 write clears selected bits in oc5con, read yields an undefined value bf80_3808 oc5conset 31:0 write sets selected bits in oc5con, read yields an undefined value bf80_380c oc5coninv 31:0 write inverts selected bits in oc5con, read yields an undefined value bf80_3810 oc5r 31:24 oc5r<31:24> 23:16 oc5r<23:16> 15:8 oc5r<15:8> 7:0 oc5r<7:0> bf80_3814 oc5rclr 31:0 write clears selected bits in oc5r, read yields an undefined value bf80_3818 oc5rset 31:0 write sets selected bits in oc5r, read yields an undefined value bf80_381c oc5rinv 31:0 write inverts selected bits in oc5r, read yields an undefined value bf80_3820 oc5rs 31:24 oc5rs<31:24> 23:16 oc5rs<23:16> 15:8 oc5rs<15:8> 7:0 oc5rs<7:0> bf80_3824 oc5rsclr 31:0 write clears selected bits in oc5rs, read yields an undefined value bf80_3828 oc5rsset 31:0 write sets selected bits in oc5rs, read yields an undefined value bf80_382c oc5rsinv 31:0 write inverts selected bits in oc5rs, read yields an undefined value table 16-10: output compare 5 interrupt register summary (1) virtual address name bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 bf88_1060 iec0 23:16 spi1eie oc5ie ic5ie t5ie int4ie oc4ie ic4ie t4ie bf88_1030 ifs0 23:16 spi1eif oc5if ic5if t5if int4if oc4if ic4if t4if bf88_10e0 ipc5 23:16 ? ? ? oc5ip<2:0> oc5is<1:0> note 1: this summary table contains partial register definitions that only pertain to the output compare5 peripheral. refer to the ?pic32mx family reference manual ? (ds61132) for a detailed description of these registers.
? 2008 microchip technology inc. preliminary ds61143e-page 371 pic32mx3xx/4xx table 16-11: timer register summary virtual address name bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 bf80_0800 t2con 15:8 on frz sidl ? ? ? ? ? 7:0 tgate tckps<2:0> t32 ?tcs ? bf80_0810 tmr2 15:8 tmr2<15:8> 7:0 tmr2<7:0> bf80_0820 pr2 15:8 pr2<15:8> 7:0 pr2<7:0> bf80_0a00 t3con 15:8 on frz sidl ? ? ? ? ? 7:0 tgate tckps<2:0> ? ?tcs ? bf80_0a10 tmr3 15:8 tmr3<15:8> 7:0 tmr3<7:0> bf80_0a20 pr3 15:8 pr3<15:8> 7:0 pr3<7:0> note 1: this summary table contains partial register definitions that only pertain to the timer 2 and timer 3 peripherals. refer to the ?pic32mx family reference manual ? (ds61132) for a detailed description of these registers.
pic32mx3xx/4xx ds61143e-page 372 preliminary ? 2008 microchip technology inc. register 16-1: ocxcon: output compare x control register r-x r-x r-x r-x r-x r-x r-x r-x ? ? ? ? ? ? ? ? bit 31 bit 24 r-x r-x r-x r-x r-x r-x r-x r-x ? ? ? ? ? ? ? ? bit 23 bit 16 r/w-0 r/w-0 r/w-0 r-x r-x r-x r-x r-x on frz sidl ? ? ? ? ? bit 15 bit 8 r-x r-x r/w-0 r-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? oc32 ocflt octsel ocm<2:0> bit 7 bit 0 legend: r = readable bit w = writable bit p = programmable bit r = reserved bit u = unimplemented bit -n = bit value at por: (?0?, ?1?, x = unknown) bit 31-16 reserved: write ? 0 ?; ignore read bit 15 on: output compare peripheral on bit 1 = output compare peripheral is enabled. the status of other bits in the register are not affected by setting this bit 0 = output compare peripheral is disabled and not drawing current. sfr modifications are allowed. the status of other bits in this register are not affected by clearing this bit bit 14 frz: freeze in debug exception mode bit 1 = freeze operation when cpu enters in debug exception mode 0 = continue operation when cpu enters in debug exception mode note: frz is only writable in debug exception mode; it is forced to ? 0 ? in normal mode. bit 13 sidl: stop in idle mode bit 1 = discontinue operation when cpu enters in idle mode 0 = continue operation in idle mode bit 12-6 reserved: write ? 0 ?; ignore read bit 5 oc32: 32-bit compare mode bit 1 = ocxr<31:0> and/or ocxrs<31:0> are used for comparisions to the 32-bit timer source 0 = ocxr<15:0> and ocxrs<15:0> are used for comparisons to the 16-bit timer source bit 4 ocflt: pwm fault condition status bit (1) 1 = pwm fault condition has occurred (cleared in hw only) 0 = no pwm fault condition has occurred note: this bit is only used when ocm<2:0> = 111 . bit 3 octsel: output compare timer select bit 1 = timer3 is the clock source for compare x 0 = timer2 is the clock source for compare x note: octsel must be set to ? 1 ? when using 32-bit mode (oc32 = 1 ). note 1: reads as ? 0 ? in modes other than pwm mode.
? 2008 microchip technology inc. preliminary ds61143e-page 373 pic32mx3xx/4xx bit 2-0 ocm<2:0>: output compare mode select bits 111 = pwm mode on ocx, fault pin enabled 110 = pwm mode on ocx, fault pin disabled 101 = initialize ocx pin low, generate continuous output pulses on ocx pin 100 = initialize ocx pin low, generate single output pulse on ocx pin 011 = compare event toggles ocx pin 010 = initialize ocx pin high, compare event forces ocx pin low 001 = initialize ocx pin low, compare event forces ocx pin high 000 = output compare peripheral is disabled register 16-1: ocxcon: output compare x control register note 1: reads as ? 0 ? in modes other than pwm mode.
pic32mx3xx/4xx ds61143e-page 374 preliminary ? 2008 microchip technology inc. register 16-2: ocxr: output compare x compare primary register r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ocr<31:24> bit 31 bit 24 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ocr<23:16> bit 23 bit 16 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ocr<15>8> bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ocr<7:0> bit 7 bit 0 legend: r = readable bit w = writable bit p = programmable bit r = reserved bit u = unimplemented bit -n = bit value at por: (?0?, ?1?, x = unknown) bit 31-16 ocxr<31:16>: upper 16 bits of 32-bit compare value when oc32 (ocxcon<5>) = 1 bit 15-0 ocxr<15:0>: lower 16 bits of 32-bit compare value or entire 16 bits of 16-bit compare value
? 2008 microchip technology inc. preliminary ds61143e-page 375 pic32mx3xx/4xx register 16-3: ocxrs: output co mpare x compare secondary register r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ocrs<31:24> bit 31 bit 24 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ocrs<23:16> bit 23 bit 16 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ocrs<5>8> bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ocrs<7:0> bit 7 bit 0 legend: r = readable bit w = writable bit p = programmable bit r = reserved bit u = unimplemented bit -n = bit value at por: (?0?, ?1?, x = unknown) bit 31-16 ocxrs<31:16>: upper 16 bits of 32-bit compare value, when oc32 (ocxcon<5>) = 1 bit 15-0 ocxrs<15:0>: lower 16 bits of 32-bit compare value or entire 16 bits of 16-bit compare value
pic32mx3xx/4xx ds61143e-page 376 preliminary ? 2008 microchip technology inc. 16.2 setup for single output change there are three modes of operation that change the state of the output pin; these modes can be referred to as drive high, drive low and toggle. the configuration for these modes is identical, the mode is selected by the ocm bits. for this example, tx will represent timer2. drive high: when the ocm control bits (ocxcon<2:0>) are set to ? 001 ?, the selected output compare channel initializes the ocx pin to the low state and drives the output pin high when a compare event occurs. drive low: when the ocm control bits (ocxcon<2:0>) are set to ? 010 ?, the selected output compare channel initializes the ocx pin to the high state and drives the output pin low when a compare event occurs. toggle: when the ocm control bits (ocxcon<2:0>) are set to ? 011 ?, the selected output compare channel ocx pin is not initialized. the ocx pin is driven to the opposite state when a compare event occurs. to generate a output change signal, the following steps are required (these steps assume the timer source is initially turned off, but this is not a requirement for the module operation): 1. determine the timer clock cycle time. take into account the frequency of the external clock to the timer source (if one is used) and the timer prescaler settings. 2. calculate time to the rising edge of the output pulse relative to the timer start value (0000h). 3. determine if the output compare module will be used in 16 or 32-bit mode based on the previous calculations. 4. configure the timer to be used as the time base for 16 or 32-bit mode by writing to the t32 bit (txcon). 5. configure the output compare channel for 16 or 32-bit operation by writing to the oc32 bit (ocxcon<5>). 6. write the value computed in step 2 above into the compare register, ocxr. 7. set timer period register, prx, to the value equal to or greater than the value in ocxrs, the secondary compare register. 8. set the ocm bits to the desired mode of operation and the octsel (ocxcon<3>) bit to the desired timer source. the ocx pin state will now be driven low. 9. set the on (txcon<15>) bit to ? 1 ? which enables the compare time base to count. 10. upon the first match between tmrx and ocxr, the ocx pin will be driven high. 11. when the incrementing timer, tmrx, matches the secondary compare register, ocxrs, the second and trailing edge (high-to-low) of the pulse is driven onto the ocx pin. no additional pulses are driven onto the ocx pin and it remains at low. as a result of the second compare match event, the ocxif interrupt flag bit is set, which will result in an interrupt if it is enabled, by setting the ocxie bit. for further information on peripheral interrupts, refer to section 8.0 ?interrupts? . 12. to initiate another single pulse output, change the timer and compare register settings, if needed, and then issue a write to set the ocm bits to the desired mode of operation. disabling and re- enabling of the timer and clearing the timer register are not required, but may be advantageous for defining a pulse from a known event time boundary. 16.3 setup for single output pulse generation when the ocm control bits (ocxcon<2:0>) are set to ? 100 ?, the selected output compare channel initializes the ocx pin to the low state and generates a single out- put pulse. to generate a single output pulse, the following steps are required (these steps assume the timer source is initially turned off, but this is not a requirement for the module operation): for this example tx will represent timer2. 1. determine the timer clock cycle time. take into account the frequency of the external clock to the timer source (if one is used) and the timer prescaler settings. 2. calculate time to the rising edge of the output pulse relative to the timer start value (0000h). 3. calculate the time to the falling edge of the pulse based on the desired pulse width and the time to the rising edge of the pulse. 4. determine if the output compare module will be used in 16 or 32-bit mode based on the previous calculations. 5. configure the timer to be used as the time base for 16 or 32-bit mode by writing to the t32 bit (txcon). 6. configure the output compare channel for 16 or 32-bit operation by writing to the oc32 bit (ocxcon<5>). 7. write the values computed in steps 2 and 3 above into the compare register, ocxr, and the secondary compare register, ocxrs, respectively. 8. set timer period register, prx, to the value equal to or greater than the value in the ocxrs, the secondary compare register.
? 2008 microchip technology inc. preliminary ds61143e-page 377 pic32mx3xx/4xx 9. set the ocm bits to ? 100 ? and the octsel (ocxcon<3>) bit to the desired timer source. the ocx pin state will now be driven low. 10. set the on (txcon<15>) bit to ? 1 ? which enables the compare time base to count. 11. upon the first match between tmrx and ocxr, the ocx pin will be driven high. 12. when the incrementing timer matches the sec- ondary compare register, ocxrs, the second and trailing edge (high-to-low) of the pulse is driven onto the ocx pin. no additional pulses are driven onto the ocx pin and it remains at low. as a result of the second compare match event, the ocxif interrupt flag bit is set, which will result in an interrupt if it is enabled, by setting the ocxie bit. for further information on peripheral interrupts, refer to section 8.0 ?interrupts? . 13. to initiate another single pulse output, change the timer and compare register settings, if needed, and then issue a write to set the ocm bits to ? 100 ?. disabling and re-enabling of the timer and clear- ing the tmrx register are not required, but may be advantageous for defining a pulse from a known event time boundary. example 16-1: example code // the following code example will set the output compare 1 module for interrupts on the // single pulse event and select timer 2 as the clock source for the compare time base. t2con = 0x0010; // configure timer 2 for a prescaler of 2 oc1con = 0x0000; // turn off oc1 while doing setup. oc1con = 0x0004; // configure for single pulse mode oc1r = 0x3000; // initialize primary compare register oc1rs = 0x3003; // initialize secondary compare register pr2 = 0x3003; // set period (pr2 is now 32-bits wide) // configure int if0clr = 0x00000080; // clear the oc1 interrupt flag ie0set = 0x00000080; // enable oc1 interrupt ipc1set = 0x0030000; // set oc1 interrupt subpriority to 3, // the highest level ipc1set = 0x00000003; // set subpriority to 3, maximum t2conset = 0x8000; // enable timer2 oc1conset = 0x8000; // enable the oc1 module // example code for output compare 1 isr: void__isr (_output_compare__1_vector, ipl4) oc1_inthandler(void) { // insert user code here ifs0clr = 0x00000080; // clear the oc1 interrupt flag }
pic32mx3xx/4xx ds61143e-page 378 preliminary ? 2008 microchip technology inc. 16.4 setup for continuous output pulse generation when the ocm control bits (ocxcon<2:0>) are set to ? 101 ?, the selected output compare channel initializes the ocx pin to the low state and generates output pulses on each and every compare match event. for the user to configure the module for the generation of a continuous stream of output pulses, the following steps are required (these steps assume the timer source is initially turned off, but this is not a requirement for the module operation). for this example, tx will represent timer2. 1. determine the timer clock cycle time. take into account the frequency of the external clock to the timer source (if one is used) and the timer prescaler settings. 2. calculate time to the rising edge of the output pulse relative to the tmrx start value (0000h). 3. calculate the time to the falling edge of the pulse based on the desired pulse width and the time to the rising edge of the pulse. 4. determine if the output compare module will be used in 16 or 32-bit mode based on the previous calculations. 5. configure the timer to be used as the time base for 16 or 32-bit mode by writing to the t32 bit (txcon). 6. configure the output compare channel for 16 or 32-bit operation by writing to the oc32 bit (ocxcon<5>). 7. write the values computed in step 2 and 3 above into the compare register, ocxr, and the secondary compare register, ocxrs, respectively. 8. set timer period register, prx, to the value equal to or greater than the value in ocxrs, the secondary compare register. 9. set the ocm bits to ? 101 ? and the octsel bit to the desired timer source. the ocx pin state will now be driven low. 10. enable the compare time base by setting the on (txcon<15>) bit to ? 1 ?. 11. upon the first match between tmrx and ocxr, the ocx pin will be driven high. 12. when the compare time base, tmry, matches the secondary compare register, ocxrs, the second and trailing edge (high-to-low) of the pulse is driven onto the ocx pin. 13. as a result of the second compare match event, the ocxif interrupt flag bit set. 14. when the compare time base and the value in its respective period register match, the tmrx register resets to 0x0000 and resumes counting. 15. steps 8 through 11 are repeated and a continuous stream of pulses is generated, indefinitely. the ocxif flag is set on each ocxrs-tmrx compare match event. 16.5 pulse-width modulation mode there are two modes of pwm operation for this device: pwm and pwm with fault input. the configuration of both modes is identical with the exception of the value written to the ocm bits to select the desired mode. the following steps should be taken when configuring the output compare module for pwm operation: 1. calculate the pwm period. 2. calculate the pwm duty cycle. 3. determine if the output compare module will be used in 16 or 32-bit mode based on the previous calculations. 4. configure the timer to be used as the time base for 16 or 32-bit mode by writing to the t32 bit (txcon). 5. configure the output compare channel for 16 or 32-bit operation by writing to the oc32 bit (ocxcon<5>). 6. set the pwm period by writing to the selected timer period register (pr). 7. set the pwm duty cycle by writing to the ocxrs register. 8. write the ocxr register with the initial duty cycle. 9. enable interrupts, if required, for the timer and output compare modules. the output compare interrupt is required for pwm fault pin utilization. 10. configure the output compare module for one of two pwm operation modes by writing to the out- put compare mode bits ocm<2:0> (ocxcon<2:0>). 11. set the tmrx prescale value and enable the time base by setting on (txcon<15>) = 1 . note: the ocxr register should be initialized before the output compare module is first enabled. the ocxr register becomes a read-only duty cycle register when the module is operated in the pwm modes. the value held in ocxr will become the pwm duty cycle for the first pwm period. the contents of the duty cycle buffer register, ocxrs, will not be transferred into ocxr until a time base period match occurs.
? 2008 microchip technology inc. preliminary ds61143e-page 379 pic32mx3xx/4xx 16.5.1 pwm with fault protection input pin when the output compare mode bits, ocm<2:0> (ocxcon<2:0>), are set to ? 111 ?, the selected output compare channel is configured for the pwm mode of operation. all functions of the pwm are applicable with the addition of fault protection input. fault protection is provided via the ocfa and ocfb pins. the ocfa pin is associated with output compare channels 1 through 4, while the ocfb pin is associated with output compare channel 5. if a logic ? 0 ? is detected on the ocfa/ocfb pin, the selected pwm output pin(s) is placed in a high- impedance state. the user may elect to provide a pull- down or pull-up resistor on the pwm pin to provide a desired state if a fault condition occurs. the shutdown of the pwm output is immediate and is not tied to the device clock source. this state will remain until the following changes occur: ? the external fault condition has been removed ? pwm mode is re-enabled by writing to the mode bits ocm<2:0>. as a result of the fault condition, the respective inter- rupt flag ocxif is asserted and an interrupt will be gen- erated, if it is enabled. upon detection of the fault condition, the ocflt bit (ocxcon<4>) is asserted high (logic ? 1 ?). this bit is a read-only bit and will only be cleared once the external fault condition has been removed and the pwm mode is re-enabled, by writing to the appropriate mode bits, ocm<2:0>. 16.5.2 pwm period the pwm period is specified by writing to pr, the timer period register. the pwm period can be calculated using equation 16-1. equation 16-1: calculating the pwm period 16.5.3 pwm duty cycle the pwm duty cycle is specified by writing to the ocxrs register. the ocxrs register can be written to at any time, but the duty cycle value is not latched into ocxr until a match between the pr and timer occurs (i.e., the period is complete). this provides a double buffer for the pwm duty cycle and is essential for glitch- less pwm operation. in the pwm mode, ocxr is a read-only register. some important boundary parameters of the pwm duty cycle include: ? if the duty cycle register, ocxr, is loaded with 0000h, the ocx pin will remain low (0% duty cycle). ? if ocxr is greater than pr (timer period register), the pin will remain high (100% duty cycle). ? if ocxr is equal to pr, the ocx pin will be low for one time base count value and high for all other count values. see example 16-2 for pwm mode timing details. table shows example pwm frequencies and resolutions for a device peripheral bus operating at 10 mhz. equation 16-2: calculation fo r maximum pwm resolution note: a pry value of n will produce a pwm period of n + 1 time base count cycles. for example, a value of 7 written into the pry register will yield a period consisting of 8 time base cycles. pwm period = [(pr+ 1) ? t pb ? (tmr prescale value)] pwm frequency = 1/[pwm period] ( ) maximum pwm resolution (bits) = f pb f pwm ? tmry ? prescaler log 10 log 10 (2) bits
pic32mx3xx/4xx ds61143e-page 380 preliminary ? 2008 microchip technology inc. example 16-2: pwm period and duty cycle calculation example 16-3: pwm mode pulse setup an d interrupt servicing (32-bit mode) desired pwm frequency is 52.08 khz, f pb = 10 mhz timer 2 prescale setting: 1:1 1/52.08 khz = (pr2 + 1) ? f bp ? (timer2 prescale value) 19.20 s = (pr2 + 1) ? 0.1 s ? (1) pr2 = 191 find the maximum resolution of the duty cycle that can be used with a 52.08 khz pwm frequency and a 10 mhz peripheral bus clock rate. 1/52.08 khz = 2 pwm resolution ? 1/10 mhz ? 1 19.20 s=2 pwm resolution ? 100 nsec ? 1 192 = 2 pwm resolution log 10 (192) = (pwm resolution) ? log 10 (2) pwm resolution= 7.6 bits note: if the pr value exceeds 16 bits the module must be used in 32-bit mode to maintain the calculated pwm resolution. if reduced resolution is acceptable the timer prescaler may be increased and the calculation repeated until the result is a 16-bit value. increasing the timer prescaler to allow operation in 16-bit mode may result in reduced pwm resolution. // the following code example will set the output compare 1 module // for pwm mode with fault pin disabled, a 50% duty cycle and a // pwm frequency of 52.08 khz at f pb = 40 mhz. timer2 is selected as // the clock for the pwm time base and output compare 1 interrupts // are enabled. oc1con = 0x0000; // turn off oc1 while doing setup. oc1r = 0x00600000; // initialize primary compare register oc1rs = 0x00600000; // initialize secondary compare register oc1con = 0x0006; // configure for pwm mode, fault pin disabled pr2 = 0x00600000; // set period // configure int ifs0 &= ~0x00000080; // clear the oc1 interrupt flag iec0 |= 0x00000080; // enable oc1 interrupt ipc1 |= 0x001c0000; // set oc1 interrupt priority to 7, // the highest level ipc1 |= 0x00000003; // set subpriority to 3, maximum t2con |= 0x8000; // enable timer2 oc1con |= 0x8000; // turn on oc1 module // example code for output compare 1 isr: void__isr (_output_compare_1_vector, ipl4) oc1_inthandler(void) { // insert user code here ifs0clr = 0x00000080; // clear the interrupt flag }
? 2008 microchip technology inc. preliminary ds61143e-page 381 pic32mx3xx/4xx table 16-12: example pwm frequencies and resolutions with peripheral bus clock of 10 mhz (16-bit mode) pwm frequency 19.5 hz 153 hz 305 hz 2.44 khz 9.77 khz 78.1 khz 313 khz timer prescaler ratio 8 1 1 1 1 1 1 period register value (hex) 0xfa65 0xff4e 0x8011 0x1001 0x03fe 0x007f 0x001e resolution (bits) (decimal) 16 16 15 12 10 7 5 table 16-13: example pwm frequencies and resolutions with peripheral bus clock of 30 mhz (16-bit mode) pwm frequency 58 hz 458 hz 916 hz 7.32 khz 29.3 khz 234 khz 938 khz timer prescaler ratio 8 1 1 1 1 1 1 period register value (hex) 0xfc8e 0xffdd 0x7fee 0x1001 0x03fe 0x007f 0x001e resolution (bits) (decimal) 16 16 15 12 10 7 5 table 16-14: example pwm frequencies and resolutions with peripheral bus clock of 50 mhz (16-bit mode) pwm frequency 58 hz 458 hz 916 hz 7.32 khz 29.3 khz 234 khz 938 khz timer prescaler ratio 64 8 1 1 1 1 1 period register value (hex) 0x349c 0x354d 0xd538 0x1aad 0x06a9 0x00d4 0x0034 resolution (bits) (decimal) 13.7 13.7 15.7 12.7 10.7 7.7 5.7 table 16-15: example pwm frequencies and resolutions with peripheral bus clock of 50 mhz (16-bit mode) pwm frequency 100 hz 200 hz 500 hz 1 khz 2 khz 5 khz 10 khz timer prescaler ratio 8881811 period register value (hex) 0xf423 0x7a11 0x30d3 0xc34f 0x0c34 0x270f 0x1387 resolution (bits) (decimal) 15.9 14.9 13.6 15.6 11.6 13.3 12.3 table 16-16: example pwm frequencies and resolutions with peripheral bus clock of 50 mhz (16-bit mode) pwm frequency 100 hz 200 hz 500 hz 1 khz 2 khz 5 khz 10 khz timer prescaler ratio 8421111 period register value (hex) 0xf423 0xf423 0xc34f 0x0c34f 0x61a7 0x270f 0x1387 resolution (bits) (decimal) 15.9 15.9 15.6 15.6 14.6 13.3 12.3 table 16-17: example pwm frequencies and resolutions with peripheral bus clock of 50 mhz (32-bit mode) pwm frequency 100 hz 200 hz 500 hz 1 khz 2 khz 5 khz 10 khz period register value (hex) 1111181 resolution (bits) (decimal) 0x0007a11f 0x0003d08f 0x0001869f 0x0000c34f 0x000061a7 0x000004e1 0x00001387 resolution (bits) 18.9 17.9 16.6 15.6 14.6 10.3 12.3
pic32mx3xx/4xx ds61143e-page 382 preliminary ? 2008 microchip technology inc. 16.6 output compare register i/o pin control when the output compare module is enabled, the i/o pin direction is controlled by the compare module. the compare module returns the i/o pin control back to the appropriate pin lat and tris control bits when it is disabled. when the pwm with fault protection input mode is enabled, the ocfx fault pin must be configured as an input by setting the respective tris sfr bit. the ocfx fault input pin is not automatically configured as an input when pwm with fault input mode is selected. table 16-18: pins associated with output compare modules 1- 5 pin name module control controlling bit field required tris bit setting pin type buffer type description oc1 on (2) ocm<2:0> (1,3) ? d, o ? output compare/pwm channel 1 oc2 on (2) ocm<2:0> (1,3) ? d, o ? output compare/pwm channel 2 oc3 on (2) ocm<2:0> (1,3) ? d, o ? output compare/pwm channel 3 oc4 on (2) ocm<2:0> (1,3) ? d, o ? output compare/pwm channel 4 oc5 on (2) ocm<2:0> (1,3) ? d, o ? output compare/pwm channel 5 ocfa on (2) ocm<2:0> (1,3) input d, i st pwm fault protection a input (for channels 1-4) (4) ocfb on (2) ocm<2:0> (1,3) input d, i st pwm fault protection b input (for channel 5) (4) legend: st = schmitt trigger input with cmos levels, i = input, o = output, a = analog, d = digital note 1: all pins are subject to device pin priority control. 2: on (ocxcon<15>) = 1 . when the module is turned off, pins controlled by the module are released. 3: mode select bits ocm<2:0> (cmxcon<2:0>). 4: use of pwm fault input is optional and is controlled by the ocm bits.
? 2008 microchip technology inc. preliminary ds61143e-page 383 pic32mx3xx/4xx 17.0 serial peripheral interface (spi) the serial peripheral interface (spi) module is a syn- chronous serial interface useful for communicating with external peripherals and other microcontroller devices. these peripheral devices may be serial eeproms, shift registers, display drivers, a/d converters, etc. the pic32mx spi module is compatible with motorola ? spi and siop interfaces. following are some of the key features of this module: ? master and slave modes support ? four different clock formats ? framed spi protocol support ? user configurable 8-bit, 16-bit and 32-bit data width ? separate spi data registers for receive and transmit ? programmable interrupt event on every 8-bit, 16-bit and 32-bit data transfer ? operation during cpu sleep and idle mode ? fast bit manipulation using clr, set and inv registers note: this data sheet summarizes the features of the pic32mx3xx/4xx family of devices. it is not intended to be a comprehensive refer- ence source. refer to the ?pic32mx family reference manual? (ds61132) for a detailed description of this peripheral. table 17-1: spi features available spi modes spi master spi slave frame master frame slave 8-bit, 16-bit and 32-bit modes selectable clock pulses and edges selectable frame sync pulses and edges slave select pulse normal mode yes yes ? ? yes yes ? yes framed mode yes yes yes yes yes yes yes no
pic32mx3xx/4xx ds61143e-page 384 preliminary ? 2008 microchip technology inc. figure 17-1: spi modu le block diagram internal data bus sdix sdox ss x/f sync sckx spixsr bit 0 shift control edge select enable master clock baud rate slave select sync control clock control transmit spixrxb receive and frame note: access spixtxb and spixrxb registers via spixbuf register. registers share address spixbuf spixtxb spixbuf generator pbclk write read
? 2008 microchip technology inc. preliminary ds61143e-page 385 pic32mx3xx/4xx 17.1 spi registers table 17-2: spi1 sfr summary table 17-3: spi1 interrupt register summary virtual address name bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 bf80_5800 spi1con 31:24 frmen frmsync frmpol ? ? ? ? ? 23:16 ? ? ? ? ? ?spife ? 15:8 on frz sidl dissdo mode32 mode16 smp cke 7:0 ssen ckp msten ? ? ? ? ? bf80_5804 spi1conclr 31:0 write clears selected bits in spi1con, read yields an undefined value bf80_5808 spi1conset 31:0 write sets selected bits in spi1con, read yields an undefined value bf80_580c spi1coninv 31:0 write inverts selected bits in spi1con, read yields an undefined value bf80_5810 spi1stat 31:24 ? ? ? ? ? ? ? ? 23:16 ? ? ? ? ? ? ? ? 15:8 ? ? ? ? spibusy ? ? ? 7:0 ? spirov ? ? spitbe ? ?spirbf bf80_5814 spi1statclr 31:0 write clears selected bits in spi1stat, read yields an undefined value bf80_5820 spi1buf 31:24 data<31:24> 23:16 data<23:16> 15:8 data<15:8> 7:0 data<7:0> bf80_5830 spi1brg 31:24 ? ? ? ? ? ? ? ? 23:16 ? ? ? ? ? ? ? ? 15:8 ? ? ? ? ? ? ?brg<8> 7:0 brg<7:0> bf80_5834 spi1brgclr 31:0 write clears selected bits in spi1brg, read yields an undefined value bf80_5838 spi1brgset 31:0 write sets selected bits in spi1brg, read yields an undefined value bf80_583c spi1brginv 31:0 write inverts selected bits in spi1brg, read yields an undefined value virtual address name bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 bf88_1060 iec0 31:24 i2c1mie i2c1sie i2c1bie u1txie u1rxie u1eie spi1rxie spi1txie 23:16 spi1eie oc5ie ic5ie t5ie int4ie oc4ie ic4ie t4ie bf88_1030 ifs0 31:24 i2c1mif i2c1sif i2c1bif u1txif u1rxif u1eif spi1rxif spi1txif 23:16 spi1eif oc5if ic5if t5if int4if oc4if ic4if t4if bf88_10e0 ipc5 31:24 ? ? ? spi1ip<2:0> spi1is<1:0> note: this summary table contains partial register definitions that only pertain to the spi1 peripheral. refer to the ? pic32mx family reference manual ? (ds61132) for a detailed description of these registers.
pic32mx3xx/4xx ds61143e-page 386 preliminary ? 2008 microchip technology inc. table 17-4: spi2 sfr summary table 17-5: spi2 interrupt register summary virtual address name bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 bf80_5a00 spi2con 31:24 frmen frmsync frmpol ? ? ? ? ? 23:16 ? ? ? ? ? ?spife ? 15:8 on frz sidl dissdo mode32 mode16 smp cke 7:0 ssen ckp msten ? ? ? ? ? bf80_5a04 spi2conclr 31:0 write clears selected bits in spi2con, read yields an undefined value bf80_5a08 spi2conset 31:0 write sets selected bits in spi2con, read yields an undefined value bf80_5a0c spi2coninv 31:0 write inverts selected bits in spi2con, read yields an undefined value bf80_5a10 spi2stat 31:24 ? ? ? ? ? ? ? ? 23:16 ? ? ? ? ? ? ? ? 15:8 ? ? ? ? spibusy ? ? ? 7:0 ? spirov ? ? spitbe ? ?spirbf bf80_5a14 spi2statclr 31:0 write clears selected bits in spi2stat, read yields an undefined value bf80_5a20 spi2buf 31:24 data<31:24> 23:16 data<23:16> 15:8 data<15:8> 7:0 data<7:0> bf80_5a30 spi2brg 31:24 ? ? ? ? ? ? ? ? 23:16 ? ? ? ? ? ? ? ? 15:8 ? ? ? ? ? ? ?brg<8> 7:0 brg<7:0> bf80_5a34 spi2brgclr 31:0 write clears selected bits in spi2brg, read yields an undefined value bf80_5a38 spi2brgset 31:0 write sets selected bits in spi2brg, read yields an undefined value bf80_5a3c spi2brginv 31:0 write inverts selected bits in spi2brg, read yields an undefined value virtual address name bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 bf88_1070 iec1 7:0 spi2rxie spi2txie spi2eie cmp2ie cmp1ie pmpie ad1ie cnie bf88_1040 ifs1 7:0 spi2rxif spi2txif spi2eif cmp2if cmp1if pmpif ad1if cnif bf88_1100 ipc7 23:16 ? ? ? spi2ip<2:0> sp2is<1:0> note: this summary table contains partial register defin itions that only pertain to the spi2 peripheral. refer to the ? pic32mx family reference manual ? (ds61132) for a detailed description of these registers.
? 2008 microchip technology inc. preliminary ds61143e-page 387 pic32mx3xx/4xx register 17-1: spixcon: spi control register r/w-0 r/w-0 r/w-0 r-x r-x r-x r-x r-x frmen frmsync frmpol ? ? ? ? ? bit 31 bit 24 r-x r-x r-x r-x r-x r-x r/w-0 r-x ? ? ? ? ? ? spife ? bit 23 bit 16 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 on frz sidl dissdo mode32 mode16 smp cke bit 15 bit 8 r/w-0 r/w-0 r/w-0 r-x r-x r-x r-x r-x ssen ckp msten ? ? ? ? ? bit 7 bit 0 legend: r = readable bit w = writable bit p = programmable bit r = reserved bit u = unimplemented bit -n = bit value at por: (?0?, ?1?, x = unknown) bit 31 frmen: framed spi support bit 1 = framed spi support is enabled (ssx pin used as fsync input/output) 0 = framed spi support is disabled bit 30 frmsync: frame sync pulse direction control on ssx pin bit (framed spi mode only) 1 = frame sync pulse input (slave mode) 0 = frame sync pulse output (master mode) bit 29 frmpol: frame sync polarity bit (framed spi mode only) 1 = frame pulse is active-high 0 = frame pulse is active-low bit 28-18 reserved: write ? 0 ?; ignore read bit 17 spife: frame sync pulse edge select bit (framed spi mode only) 1 = frame synchronization pulse coincides with the first bit clock 0 = frame synchronization pulse precedes the first bit clock bit 16 reserved: write ? 0 ?; ignore read bit 15 on: spi peripheral on bit 1 = spi peripheral is enabled 0 = spi peripheral is disabled bit 14 frz: freeze in debug exception mode bit 1 = freeze operation when cpu enters debug exception mode 0 = continue operation when cpu enters debug exception mode note: frz is writable in debug exception mode only, it is forced to ? 0 ? in normal mode. bit 13 sidl: stop in idle mode bit 1 = discontinue operation when cpu enters in idle mode 0 = continue operation in idle mode bit 12 dissdo: disable sdox pin bit 1 = sdox pin is not used by the module. pin is controlled by associated port register 0 = sdox pin is controlled by the module
pic32mx3xx/4xx ds61143e-page 388 preliminary ? 2008 microchip technology inc. bit 11-10 mode<32,16>: 32/16-bit communication select bits 1x = 32-bit data width 01 = 16-bit data width 00 = 8-bit data width bit 9 smp: spi data input sample phase bit master mode (msten = 1 ): 1 = input data sampled at end of data output time 0 = input data sampled at middle of data output time slave mode (msten = 0 ): smp value is ignored when spi is used in slave mode. the module always uses smp = 0 . bit 8 cke: spi clock edge select bit 1 = serial output data changes on transition from active clock state to idle clock state (see ckp bit) 0 = serial output data changes on transition from idle clock state to active clock state (see ckp bit) note: the cke bit is not used in the framed spi mode. the user should program this bit to ? 0 ? for the framed spi mode (frmen = 1 ). bit 7 ssen: slave select enable (slave mode) bit 1 = ssx pin used for slave mode 0 = ssx pin not used for slave mode, pin controlled by port function. bit 6 ckp: clock polarity select bit 1 = idle state for clock is a high level; active state is a low level 0 = idle state for clock is a low level; active state is a high level bit 5 msten: master mode enable bit 1 = master mode 0 = slave mode bit 4-0 reserved: write ? 0 ?; ignore read
? 2008 microchip technology inc. preliminary ds61143e-page 389 pic32mx3xx/4xx register 17-2: spixstat: spi status register r-x r-x r-x r-x r-x r-x r-x r-x ? ? ? ? ? ? ? ? bit 31 bit 24 r-x r-x r-x r-x r-x r-x r-x r-x ? ? ? ? ? ? ? ? bit 23 bit 16 r-x r-x r-x r-x r-0 r-x r-x r-x ? ? ? ? spibusy ? ? ? bit 15 bit 8 r-x r/w-0 r-x r-x r-0 r-x r-x r-0 ? spirov ? ? spitbe ? ? spirbf bit 7 bit 0 legend: r = readable bit w = writable bit p = programmable bit r = reserved bit u = unimplemented bit -n = bit value at por: (?0?, ?1?, x = unknown) bit 31-12 reserved: write ? 0 ?; ignore read bit 11 spibusy: spi activity status bit 1 = spi peripheral is currently busy with some transactions 0 = spi peripheral is currently idle bit 10-7 reserved: write ? 0 ?; ignore read bit 6 spirov: receive overflow flag bit 1 = a new data is completely received and discarded. the user software has not read the previous data in the spixbuf register. 0 = no overflow has occurred this bit is set in hardware; can only be cleared (= 0 ) in software. bit 5-4 reserved: write ? 0 ?; ignore read bit 3 spitbe: spi transmit buffer empty status bit 1 = transmit buffer, spixtxb is empty 0 = transmit buffer, spixtxb is not empty automatically set in hardware when spi transfers data from spixtxb to spixsr. automatically cleared in hardware when spixbuf is written to, loading spixtxb. bit 2 reserved: write ? 0 ?; ignore read bit 1 reserved: write ? 0 ?; ignore read bit 0 spirbf: spi receive buffer full status bit 1 = receive buffer, spixrxb is full 0 = receive buffer, spixrxb is not full automatically set in hardware when spi transfers data from spixsr to spixrxb. automatically cleared in hardware when spixbuf is read from, reading spixrxb.
pic32mx3xx/4xx ds61143e-page 390 preliminary ? 2008 microchip technology inc. 17.2 master and slave modes the pic32mx3xx/4xx spi module operates in normal master or slave modes and offers the following addi- tional modes: ? framed master ? framed slave ? 8, 16, 32-bit data width transfers ? slave select (slave mode only) below is a typical system master ? slave connection diagram. 17.2.1 8, 16, and 32-bit operation the pic32mx3xx/4xx spi module allows three types of data widths when transmitting and receiving data over an spi bus. the selection of data width deter- mines the minimum length of spi data. two control bits, mode32 and mode16 (spixcon<11:10>), define the mode of operation. to change the mode of operation on the fly, the spi mod- ule must be idle, i.e., not performing any transactions. if the spi module is switched off (spixcon<15> = 0 ), the new mode will be available when the module is again switched on. the number of clock pulses at the sckx pin are depen- dent on the selected mode of operation. for 8-bit mode, 8 clocks; for 16-bit mode, 16 clocks; and for 32-bit mode, 32 clocks are required. figure 17-2: spi mast er/slave connection serial receive buffer (spixrxb) shift register (spixsr) lsb msb sdix sdox processor 2 sckx ssx ( 1 ) serial transmit buffer (spixtxb) serial receive buffer (spixrxb) ( 2 ) shift register (spixsr) msb lsb sdox sdix pic32mx3xx/4xx serial clock . ssen (spixcon<7>) = 1 and msten (spixcon<5>) = 0 note 1: using the ssx pin in slave mode of operation is optional. 2: user must write transmit data to spixbuf and read received data from spixbuf. the spixtxb and spixrxb registers are memory mapped to spixbuf. gpio/ssx sckx serial transmit buffer (spixtxb) ( 2 ) msten (spixcon<5> )= 1 spi buffer (spixbuf) spi buffer (spixbuf) [spi master] [spi slave]
? 2008 microchip technology inc. preliminary ds61143e-page 391 pic32mx3xx/4xx 17.2.2 master mode in master mode, data from the spixbuf register is transmitted synchronously on the sdo (output) pin while synchronous data is received from the slave device on the sdi (input) pin. in this mode, the master controls the synchronous data transfer with the sck clock pin by generating 8, 16 or 32 clock pulses, depending on the selected data size. 17.2.2.1 master mode operations in master mode the sck and sdo pins are outputs and the sdi pin is an input. setting the control bit, dissdo (spixcon<12>), disables transmission at the sdo pin if receive only mode of operation is desired. refer to table 17-7. the sdi (input) must be configured to properly sample the data received from the slave device by configuring the sample bit, smp (spixcon<9>). in master mode, the sck clock edge and polarity must be configured properly for the master and slave device to correctly transfer data synchronously. refer to the timing diagram shown in figure 17-3 to determine the appropriate settings. in master mode, the data transfers can be 8, 16, or 32 bits and are configured using control bits, mode<32,16> (spixcon<11:10>). refer to section 17.2.1 ?8, 16, and 32-bit operation? . in master mode, the system clock is divided and then used as the serial clock. the division is based on the settings in the spixbrg register. refer to section 17.2.5 ?spi master mode clock fre- quency? . 17.2.2.2 master spixcon configuration the following bits must be configured as shown for the master mode of operation when configuring the spixcon register: ? enable master mode msten (spixcon<5>) = 1 . ? disable framed spi support frmen (spixcon<31>) = 0 the remaining bits are shown with example configurations and may be configured as desired: ? enable module control of sdo pin ? dissdo (spixcon<12>) = 0 ? configure sck clock polarity to idle high ? ckp (spixcon<6>) = 1 ? configure sck clock edge transition from idle to active ? cke (spixcon<8>) = 0 ? select 16-bit data width ? mode<32,16> (spixcon<11:10>) = 01 ? sample data input at middle ? smp (spixcon<9>) = 0 ? enable spi module when cpu idle ? sidl (spixcon<13>) = 0 17.2.2.3 master mode initialization the following steps should be performed to setup the spi module for the master mode of operation: 1. if interrupts are used, disable the spi interrupts in the respective iec0/1 register. 2. stop and reset the spi module by clearing the on bit. 3. clear the receive buffer. 4. if interrupts are used, the following additional steps are performed: ? clear the spix interrupt flags/events in the respective ifs0/1 register. ? set the spix interrupt enable bits in the respective iec0/1 register. ? write the spix interrupt priority and subprior- ity bits in the respective ipc5/7 register. 5. write the baud rate register, spixbrg. 6. clear the spirov bit (spixstat<6>). 7. write the selected configuration settings to the spixcon register. 8. enable spi operation by setting the on bit (spixcon<15>). 9. write the data to be transmitted to the spixbuf register. transmission (and reception) will start as soon as data is written to the spixbuf register. note 1: when using the slave select mode, the ssx or another gpio pin is used to con- trol the slave?s ssx input. the pin must be controlled in software. 2: the user must turn off the spi device prior to changing the cke or ckp bits. otherwise, the behavior of the device is not ensured. 3: the spi device must be turned off prior to changing the mode from slave to master. 4: the spixsr register cannot be written to directly by the user. all writes to the spixsr register are performed through the spixbuf register.
pic32mx3xx/4xx ds61143e-page 392 preliminary ? 2008 microchip technology inc. figure 17-3: spi master mode op eration in 8-bit mode (mode32 = 0 , mode16 = 0 ) sckx (ckp = 0 sckx (ckp = 1 sckx (ckp = 0 sckx (ckp = 1 4 clock modes input sample (2) input sample sdix (2) bit 7 bit 0 sdox bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 7 bit 0 sdix spixrxif (smp = 1 ) (smp = 0 ) (smp = 1 ) cke = 1 ) cke = 0 ) cke = 0 ) cke = 0 ) (smp = 0 ) user writes to spixbuf sdox bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (cke = 0 ) (cke = 1 ) approx. 2 sysclk latency to set spixrxif flag bit note 1: four spi clock modes are shown here to demonstrate the functionality of bits ckp (spixcon<6>) and cke (spixcon<8>). only one of the four modes can be chosen for operation. 2: the sdi and input samples shown here for two different values of the smp bit (spixcon<9>) are strictly for demonstration purposes. only one of t he two configurations of the smp bit can be chosen during operation. 3: if there are no pending transmissions, spixtxb is transferred to spixsr as soon as the user writes to spixbuf. 4: the operation for 8-bit mode is shown. the 16-bit and 32-bit modes are similar. spixsr moved into spixrxb user reads spixbuf (clock output at the sckx pin in master mode) (1) (spixstat<0>) spitbe spixtxb to spixsr (3) user writes new data during transmission spirbf two modes available for smp control bit (4)
? 2008 microchip technology inc. preliminary ds61143e-page 393 pic32mx3xx/4xx example 17-1: initialization for 16-bit spi master mode 17.2.3 slave mode in slave mode, data from the spixbuf register is transmitted synchronously on the sdo (output) pin while synchronous data is received from the master device on the sdi (input) pin. in this mode, the master device controls the synchronous data transfer with the sck clock pin by generating 8, 16 or 32 clock pulses, depending on the selected data size. 17.2.3.1 slave mode operations the sdo pin is an output and the spi pin is an input. setting the control bit, dissdo (spixcon<12>), disables transmission at the sdo pin if receive only mode of operation is desired. refer to table 17-7. the sdi (input) must be configured to properly sample the data received from the slave device by configuring the sample bit, smp (spixcon<9>). refer to timing diagram shown in figure 17-4 to deter- mine the appropriate settings. data transfers can be 8, 16, or 32 bits and are configured using control bits. mode<32,16> (spixcon<11:10>). refer to section 17.2.1 ?8, 16, and 32-bit operation? for details. slave select synchronization: the ssx pin allows a synchronous slave mode. if the ssen (spixcon<7>) bit is set, transmission and reception is enabled in slave mode only if the ssx pin is driven to a low state. if the ssen bit is not set, the ssx pin does not affect the module operation in slave mode. 17.2.3.2 slave spixcon configuration the following bits must be configured as shown for the slave mode of operation when configuring the spixcon register: ? enable slave mode ? msten (spixcon<5>) = 0 . ? disable framed spi support ? frmen (spixcon<31>) = 0 the remaining bits are shown with example configura- tions and may be configured as desired: ? enable module control of sdo pin ? dissdo (spixcon<12>) = 0 ? configure sck clock polarity to idle high ? ckp (spixcon<6>) = 1 ? configure sck clock edge transition from idle to active ? cke (spixcon<8>) = 0 ? disable slave select pin ? ssen (spixcon<7>) = 0 ? select 16-bit data width ? mode<32,16> (spixcon<11:10>) = 01 ? sample data input at middle ? smp (spixcon<9>) = 0 ? enable spi module when cpu idle ? sidl (spixcon<13>) = 0 /* the following code example will initialize the spi1 in master mode. it assumes that none of the spi1 input pins are shared with an analog input. if so, the ad1pcfg and corresponding tris registers have to be properly configured. */ int rdata; iec0clr=0x03800000; // disable all interrupts spi1con = 0; // stops and resets the spi1. rdata=spi1buf; // clears the receive buffer ifs0clr=0x03800000; // clear any existing event ipc5clr=0x1f000000; // clear the priority ipc5set=0x0d000000; // set ipl=3, subpriority 1 iec0set=0x03800000; // enable rx, tx and error interrupts spi1brg=0x1; // use f pb /4 clock frequency spi1statclr=0x40; // clear the overflow spi1con=0x8220; // spi on, 8 bits transfer, smp=1, master mode // from now on, the device is ready to transmit and receive data spi1buf=?a?; // transmit an a character
pic32mx3xx/4xx ds61143e-page 394 preliminary ? 2008 microchip technology inc. 17.2.3.3 slave mode initialization the following steps are used to set up the spi module for the slave mode of operation: 1. if interrupts are used, disable the spi interrupts in the respective iec0/1 register. 2. stop and reset the spi module by clearing the on bit. 3. clear the receive buffer. 1. if using interrupts, the following additional steps are performed: ? clear the spix interrupt flags/events in the respective ifs0/1 register. ? set the spix interrupt enable bits in the respective iec0/1 register. ? write the spix interrupt priority and subprior- ity bits in the respective ipc5/7 register. 2. clear the spirov bit (spixstat<6>). 3. write the selected configuration settings to the spixcon register with msten () = 0 . 4. enable spi operation by setting the on bit (spixcon<15>). 5. transmission (and reception) will start as soon as the master provides the serial clock. note 1: the user must turn off the spi device prior to changing the cke or ckp bits. otherwise, the behavior of the device is not ensured. 2: the spi device must be turned off prior to changing the mode from master to slave. 3: the spixsr register cannot be written into directly by the user. all writes to the spixsr register are performed through the spixbuf register.
? 2008 microchip technology inc. preliminary ds61143e-page 395 pic32mx3xx/4xx figure 17-4: spi slave mode operation in 8-bit mode with slave select pin disabled (mode32 = 0 , mode16 = 0 , ssen = 0 ) sckx input ( 1 ) (ckp = 1 sckx input ( 1 ) (ckp = 0 input sample sdix input bit 7 bit 0 sdox bit 7 bit 6 bit5 bit4 bit 3 bit 2 bit 1 bit 0 spixrxif (smp = 0 ) cke = 0 ) cke = 0 ) (smp = 0 ) user writes to spixbuf ( 2 ) spixsr to spixrxb spitbe spirbf output note 1: two spi clock modes shown only to demonstrate ckp ( spixcon<6>) and cke (spixcon<8>) bit functionality. any combination of ckp and cke bits can be chosen for module operation. 2: if there are no pending transmissions or a transmission in pr ogress, spixbuf is transferred to spixsr as soon as the user writes to spixbuf. 3: the operation for 8-bit mode is shown. the 16-bit and 32-bit modes are similar. approx. 2 sysclk latency to set spixrxif flag bit ( 3 )
pic32mx3xx/4xx ds61143e-page 396 preliminary ? 2008 microchip technology inc. example 17-2: for 16-bit spi slave mode initialization /* the following code example will initialize the spi1 in slave mode with ssen. it assumes that the spi1 ss input pin on rb2 is shared with the an2 analog input. it thus properly configures the corresponding ad1pcfg and tris registers bits. */ int rdata; iec0clr=0x03800000; // disable all interrupts spi1con = 0; // stops and resets the spi1. trisbset = 0x4; // set rb2 as a digital input ad1pcfgset = 0x4; // analog input pin in digital mode rdata=spi1buf; // clears the receive buffer ifs0clr=0x03800000; // clear any existing event ipc5clr=0x1f000000; // clear the priority ipc5set=0x0d000000; // set ipl=3, subpriority 1 iec0set=0x03800000; // enable rx, tx and error interrupts spi1statclr=0x40; // clear the overflow spi1con=0x8000; // spi on, 8 bits transfer, slave mode // from now on, the device is ready to receive and transmit data
? 2008 microchip technology inc. preliminary ds61143e-page 397 pic32mx3xx/4xx 17.2.4 framed spi modes the module supports a very basic framed spi protocol while operating in either master or slave modes. the following features are provided in the spi module to support framed spi modes: ? the control bit, frmen (spixcon<31>), enables framed spi mode and causes the ssx pin to be used as a frame synchronization pulse input or output pin. the state of the ssen (spixcon<7>) is ignored. ? the control bit, frmsync (spixcon<30>), determines whether the ssx pin is an input or an output (i.e., whether the module receives or generates the frame synchronization pulse). ? the frmpol (spixcon<29>) determines the frame synchronization pulse polarity for a single spi clock cycle. the following framed spi modes are supported by the spi module: ? frame master mode: the spi module generates the frame synchronization pulse and provides this pulse to other devices at the ssx pin. ? frame slave mode: the spi module uses a frame synchronization pulse received at the ssx pin. the framed spi modes are supported in conjunction with the master and slave modes. thus, the following framed spi configurations are available: ? spi master mode and frame master mode ? spi master mode and frame slave mode ? spi slave mode and frame master mode ? spi slave mode and frame slave mode these four modes determine whether or not the spi module generates the serial clock and the frame synchronization pulse. figure 17-5: spi master, fram e master connection diagram serial receive buffer (spixrxb) (3) shift register (spixsr) msb lsb sdox sdix pic32mx3xx/4xx serial receive buffer (spixrxb) shift register (spixsr) lsb msb sdix sdox processor 2 serial clock note 1: in framed spi modes, the ssx pin is used to transmit/receive the frame synchronization pulse. 2: framed spi modes require the use of all four pins, i.e., using the ssx pin is not optional. 3: the spixtxb and spixrxb registers are memory mapped to the spixbuf register. sckx ssx ssx sckx serial transmit buffer (spixtxb) (3) serial transmit buffer (spixtxb) frame sync pulse (1, 2) spi buffer (spixbuf) spi buffer (spixbuf) [spi master, frame master] [spi slave, frame slave]
pic32mx3xx/4xx ds61143e-page 398 preliminary ? 2008 microchip technology inc. 17.2.4.1 spi master mode and frame master mode operations this framed spi mode is enabled by setting bits msten (spixcon<5>) and frmen (spixcon<31>) to ? 1 ?, and bit frmsync (spixcon<30>) to ? 0 ?. in this mode, the serial clock will be output continuously at the sckx pin, regardless of whether the module is transmitting. when spixbuf is written, the ssx pin will be driven active, high or low depending on bit frmpol (spixcon<29>), on the next transmit edge of the sckx clock. the ssx pin will be active for one sckx clock cycle. the module will start transmitting data on the same or on the next transmit edge of the sckx, depending on the spife (spixcon<17>) setting, as shown in figure 17-6. a connection diagram indicating signal directions for this operating mode is shown in figure 17-5. the sck, sdo and ssx pins are outputs, the sdi pin is an input. setting the control bit, dissdo (spixcon<12>), disables transmission at the sdo pin if receive only mode of operation is desired; refer to table 17-7. the sdi (input) must be configured to properly sample the data received from the slave device by configuring the sample bit, smp (spixcon<9>). in master mode, the sck clock edge and polarity must be configured properly for the master and slave device to correctly transfer data synchronously. refer to timing diagram shown in figure 17-3 to deter- mine the appropriate settings. 17.2.4.2 master spixcon configuration the following bits must be configured as shown for the master mode of operation when configuring the spixcon register: ? enable master mode ? msten (spixcon<5>) = 1 ? enable framed spi support ? frmen (spixcon<31>) = 1 ? select ssx pin as frame master (output) ? frmsync(spixcon<30>) = 0 the remaining bits are shown with example configurations and may be configured as desired: ? enable module control of sdo pin ? sdo (spixcon<12>) = 0 ? configure sck clock polarity to idle high ? ckp (spixcon<6>) = 1 ? configure sck clock edge transition from idle to active ? cke (spixcon<8>) = 0 ? select ssx active-low pin polarity ? frmpol (spixcon<29>) = 0 ? select 16-bit data width ? mode<32,16> (spixcon<11:10>) = 01 ? sample data input at middle ? smp (spixcon<9>) = 0 ? enable spi module when cpu idle ? sidl (spixcon<13>) = 0 17.2.4.3 framed master mode initialization the following steps are used to set up the spi module for the master mode of operation: 1. if interrupts are used, disable the spi interrupts in the respective iec0/1 register. 2. stop and reset the spi module by clearing the on bit. 3. clear the receive buffer. 4. if using interrupts, the following additional steps are performed: ? clear the spix interrupt flags/events in the respective ifs0/1 register. ? set the spix interrupt enable bits in the respective iec0/1 register. ? write the spix interrupt priority and subprior- ity bits in the respective ipc5/7 register. 5. clear the spirov bit (spixstat<6>). 6. write the selected configuration settings to the spixcon register. 7. enable spi operation by setting the on bit (spixcon<15>). note 1: the user must turn off the spi device prior to changing the cke or ckp bits. otherwise, the behavior of the device is not ensured. 2: the spixsr register cannot be written into directly by the user. all writes to the spixsr register are performed through the spixbuf register.
? 2008 microchip technology inc. preliminary ds61143e-page 399 pic32mx3xx/4xx figure 17-6: spi master, frame master mode32 = 0 , mode16 = 1 , spife = 0 , frmpol = 1 sckx ssx sdox (ckp = 0 ) bit 15 bit 14 bit 13 bit 12 sdix bit 15 bit 14 bit 13 bit 12 write to spixbuf receive samples at sdix pulse generated at ssx sckx (ckp = 1 )
pic32mx3xx/4xx ds61143e-page 400 preliminary ? 2008 microchip technology inc. 17.2.4.4 spi master mode and frame slave mode operations this framed spi mode is enabled by setting bits msten (spixcon<5>), frmen (spixcon<31>), and frmsync (spixcon<30>) to ? 1 ?. the ssx pin is an input, and it is sampled on the sample edge of the spi clock. when it is sampled active, high, or low depending on bit frmpol (spixcon<29>), data will be transmitted on the subsequent transmit edge of the spi clock, as shown in figure 17-7. the interrupt flag spixif is set when the transmission is complete. the user must make sure that the correct data is loaded into the spixbuf for transmission before the signal is received at the ssx pin. a connection diagram indicating signal directions for this operating mode is shown in figure 17-8. the sck and sdo pins are outputs, the sdi and ssx pins are inputs. setting the control bit, dissdo (spixcon<12>), disables transmission at the sdo pin if receive only mode of operation is desired; refer to table 17-7. the sdi pin must be configured to properly sample the data received from the slave device by configuring the sample bit, smp (spixcon<9>). in master mode, the sck clock edge and polarity must be configured properly for the master and slave device to correctly transfer data synchronously. refer to timing diagram shown in figure 17-3 to determine the appropriate settings. 17.2.4.5 master spixcon configuration the following bits must be configured as shown for the master mode of operation when configuring the spixcon register: ? enable master mode ? msten (spixcon<5>) = 1 ? enable framed spi support ? frmen (spixcon<31>) = 1 ? select ssx pin as frame slave (input) ? frmsync (spixcon<30>) = 1 the remaining bits are shown with example configurations and may be configured as desired: ? enable module control of sdo pin ? dissdo (spixcon<12>) = 0 ? configure sck clock polarity to idle high ? ckp (spixcon<6>) = 1 ? configure sck clock edge transition from idle to active ? cke (spixcon<8>) = 0 ? select ssx active low pin polarity ? frmpol (spixcon<29>) = 0 ? select 16-bit data width ? mode<32,16> (spixcon<11:10>) = 01 ? sample data input at middle ? smp (spixcon<9>) = 0 ? enable spi module when cpu idle ? sidl (spixcon<13>) = 0 17.2.4.6 framed slave mode initialization the following steps are used to set up the spi module for the slave mode of operation: 1. if interrupts are used, disable the spi interrupts in the respective iec0/1 register. 2. stop and reset the spi module by clearing the on bit. 3. clear the receive buffer. 4. if using interrupts, the following additional steps are performed: ? clear the spix interrupt flags/events in the respective ifs0/1 register. ? set the spix interrupt enable bits in the respective iec0/1 register. ? write the spix interrupt priority and subpriority bits in the respective ipc5/7 register. 5. clear the spirov bit (spixstat<6>). 6. write the selected configuration settings to the spixcon register. 7. enable spi operation by setting the on bit (spixcon<15>). note 1: the user must turn off the spi device prior to changing the cke or ckp bits. otherwise, the behavior of the device is not ensured. 2: the spixsr register cannot be written into directly by the user. all writes to the spixsr register are performed through the spixbuf register. 3: receiving a frame sync pulse will start a transmission, regardless of whether or not data was written to spixbuf. if a write was not performed, zeros will be transmitted.
? 2008 microchip technology inc. preliminary ds61143e-page 401 pic32mx3xx/4xx figure 17-7: spi master , frame slave mode32 = 0 , mode16 = 1 , spife = 0 , frmpol = 1 figure 17-8: spi master, f rame slave connection diagram receive samples at sdix sck fsync sdo (ckp = 0 ) bit 15 bit 14 bit 13 bit 12 sdi sample ssx pin for frame sync pulse bit 15 bit 14 bit 13 bit 12 write to spixbuf sckx (ckp = 1 ) sdox sdix serial clock note 1: in framed spi modes, the ssx pin is used to transmit/receive the frame synchronization pulse. 2: framed spi modes require the use of all four pins (i.e., using the ssx pin is not optional). ssx sckx frame sync sdix sdox ssx sckx pic32mx3xx/4xx [spi master, frame slave] processor 2 [spi slave, frame master] pulse ( 1 , 2 )
pic32mx3xx/4xx ds61143e-page 402 preliminary ? 2008 microchip technology inc. 17.2.4.7 spi slave mode and frame master mode this framed spi mode is enabled by setting bit msten (spixcon<5>) to ? 0 ?, bit frmen (spixcon<31>) to ? 1 ? and bit frmsync (spixcon<30>) to ? 0 ?. the input spi clock will be con- tinuous in slave mode. the ssx pin will be an output when bit frmsync is low. therefore, when spibuf is written, the module will drive the ssx pin active, high or low depending on bit frmpol (spixcon<29>), on the next transmit edge of the spi clock. the ssx pin will be driven active for one spi clock cycle. data transmission will start on the next spi clock transmit edge. a connection diagram indicating signal directions for this operating mode is shown in figure 17-9. the sdo and s sx pins are outputs and the sck and sdi pins are inputs. setting the control bit, dissdo (spixcon<12>), disables transmission at the sdo pin if receive only mode of operation is desired; refer to table 17-7. the sdi pin must be configured to properly sample the data received from the slave device by configuring the sample bit, smp (spixcon<9>). refer to timing diagram shown in figure 17-6 to determine the appropriate settings. 17.2.4.8 slave spixcon configuration the following bits must be configured as shown for the slave mode of operation when configuring the spixcon register: ? enable slave mode ? msten (spixcon<5>) = 1 ? enable framed spi support ? frmen (spixcon<31>) = 1 ? select ssx pin as frame master (output) ? frmsync(spixcon<30>) = 0 the remaining bits are shown with example configurations and may be configured as desired: ? enable module control of sdo pin ? dissdo (spixcon<12>) = 0 ? configure sck clock polarity to idle high ? ckp (spixcon<6>) = 1 ? configure sck clock edge transition from idle to active ? cke (spixcon<8>) = 0 ? select ssx active low pin polarity ? frmpol (spixcon<29>) = 0 ? select 16-bit data width ? mode<32,16> (spixcon<11:10>) = 01 ? sample data input at middle ? smp (spixcon<9>) = 0 ? enable spi module when cpu idle ? sidl (spixcon<13>) = 0 17.2.4.9 framed master mode initialization the following steps are used to set up the spi module for the slave mode of operation: 1. if interrupts are used, disable the spi interrupts in the respective iec0/1 register. 2. stop and reset the spi module by clearing the on bit. 3. clear the receive buffer. 4. if using interrupts, the following additional steps are performed: ? clear the spix interrupt flags/events in the respective ifs0/1 register. ? set the spix interrupt enable bits in the respective iec0/1 register. ? write the spix interrupt priority and subpriority bits in the respective ipc5/7 register. 5. clear the spirov bit (spixstat<6>). 6. write the selected configuration settings to the spixcon register. 7. enable spi operation by setting the on bit (spixcon<15>). 8. transmission (and reception) will start as soon as the master provides the serial clock. note 1: the user must turn off the spi device prior to changing the cke or ckp bits. otherwise, the behavior of the device is not ensured. 2: the spixsr register cannot be written into directly by the user. all writes to the spixsr register are performed through the spixbuf register.
? 2008 microchip technology inc. preliminary ds61143e-page 403 pic32mx3xx/4xx figure 17-9: spi slave, frame master connection diagram 17.2.4.10 spi slave mode and frame slave mode this framed spi mode is enabled by setting bits msten (spixcon<5>) to ? 0 ?, frmen (spixcon<31>) to ? 1 ?, and frmsync (spixcon<30>) to ? 1 ?. therefore, both the sckx and ssx pins will be inputs. the ssx pin will be sampled on the sample edge of the spi clock. when ssx is sam- pled active, high or low depending on bit, frmpol (spixcon<29>), data will be transmitted on the next transmit edge of sckx. a connection diagram indicating signal directions for this operating mode is shown in figure 17-10. the sdo pins is an output and the sck, sdi and ssx pins are inputs. setting the control bit, dissdo (spixcon<12>), disables transmission at the sdo pin if receive only mode of operation is desired; refer to table 17-7. the sdi pin must be configured to properly sample the data received from the slave device by configuring the sample bit, smp (spixcon<9>). refer to timing diagram shown in figure 17-7 to determine the appropriate settings. 17.2.4.11 slave spixcon configuration the following bits must be configured as shown for the slave mode of operation when configuring the spixcon register: ? enable slave mode ? msten (spixcon<5>) = 0 ? enable framed spi support ? frmen (spixcon<31>) = 1 ? select ssx pin as frame slave (input) ? frmsync(spixcon<30>) = 1 the remaining bits are shown with example configurations and may be configured as desired: ? enable module control of sdo pin ? dissdo (spixcon<12>) = 0 ? configure sck clock polarity to idle high ? ckp (spixcon<6>) = 1 ? configure sck clock edge transition from idle to active ? cke (spixcon<8>) = 0 ? select ssx active-low pin polarity ? frmpol (spixcon<29>) = 0 ? select 16-bit data width ? mode<32,16> (spixcon<11:10>) = ? 01 ? ? sample data input at middle ? smp (spixcon<9>) = 0 ? enable spi module when cpu idle ? sidl (spixcon<13>) = 0 serial clock note 1: in framed spi modes, the ssx pin is used to transmit/receive the frame synchronization pulse. 2: framed spi modes require the use of all four pins (i.e., using the ssx pin is not optional). sdox sdix ssx sckx pic32mx3xx/4xx [spi slave, frame master] sdix sdox ssx sckx processor 2 [spi master, frame slave] frame sync pulse ( 1 )( 2 )
pic32mx3xx/4xx ds61143e-page 404 preliminary ? 2008 microchip technology inc. 17.2.4.12 framed slave mode initialization the following steps are used to set up the spi module for the slave mode of operation: 1. if interrupts are used, disable the spi interrupts in the respective iec0/1 register. 2. stop and reset the spi module by clearing the on bit. 3. clear the receive buffer. 4. if using interrupts, the following additional steps are performed: ? clear the spix interrupt flags/events in the respective ifs0/1 register. ? set the spix interrupt enable bits in the respective iec0/1 register. ? write the spix interrupt priority and subpriority bits in the respective ipc5/7 register. 5. clear the spirov bit (spixstat<6>). 6. write the selected configuration settings to the spixcon register. 7. enable spi operation by setting the on bit (spixcon<15>). 8. transmission (and reception) will start as soon as the master provides the serial clock. figure 17-10: spi slave, fram e slave connection diagram note 1: the user must turn off the spi device prior to changing the cke or ckp bits. otherwise, the behavior of the device is not ensured. 2: the spixsr register cannot be written into directly by the user. all writes to the spixsr register are performed through the spixbuf register. 3: receiving a frame sync pulse will start a transmission, regardless of whether or not data was written to spixbuf. if a write was not performed, zeros will be transmitted. serial clock note 1: in framed spi modes, the ssx pin is used to transmit/receive the frame synchronization pulse. 2: framed spi modes require the use of all four pins (i.e., using the ssx pin is not optional). 3: slave select is not available when using frame mode as a slave device. sdox sdix ssx sckx pic32mx3xx/4xx [spi slave, frame slave] sdix sdox ssx sckx processor 2 [spi master, frame master] frame sync pulse ( 1 )( 2 )( 3 )
? 2008 microchip technology inc. preliminary ds61143e-page 405 pic32mx3xx/4xx 17.2.5 spi master mode clock frequency in master mode, the spi module clock source is the peripheral bus clock (pbclk) and the sck clock baud rate is derived from the pbclk clock and the spixbrg register. equation 17-1 defines the sckx clock frequency as a function of the spixbrg register settings. equation 17-1: spi clock frequency note that the maximum possible baud rate is f pb /2 (spixbrg = 0 ) and the minimum possible baud rate is f pb /1024. sample spi clock frequencies are shown in the table table 17-6. 17.2.6 spi error handling when a new data word has been shifted into shift reg- ister spixsr and the previous contents of receive reg- ister spixrxb have not been read by the user software, the spirov bit (spixstat<6>) will be set. the module will not transfer the received data from spixsr to the spixrxb. further data reception is dis- abled until the spirov bit is cleared. the spirov bit is not cleared automatically by the module and must be cleared by the user software. note: the sckx signal clock is not free running for nonframed spi modes. it will only run for 8, 16 or 32 pulses when the spixbuf is loaded with data. it will however, be continuous for framed modes. 2 * (spixbrg+1) f pb f sck = table 17-6: sample sckx frequencies spixbrg setting0 15316385127 f pb = 50 mhz 25.00 mhz 1.56 mhz 781.25 khz 390.63 khz 290.7 khz 195.31 khz f pb = 40 mhz 20.00 mhz 1.25 mhz 625.00 khz 312.50 khz 232.56 khz 156.25 khz f pb = 25 mhz 12.50 mhz 781.25 khz 390.63 khz 195.31 khz 145.35 khz 97.66 khz f pb = 20 mhz 10.00 mhz 625.00 khz 312.50 khz 156.25 khz 116.28 khz 78.13 khz f pb = 10 mhz 5.00 mhz 312.50 khz 156.25 khz 78.13 khz 58.14 khz 39.06 khz
pic32mx3xx/4xx ds61143e-page 406 preliminary ? 2008 microchip technology inc. 17.3 spi interrupts the spi module has the ability to generate interrupts reflecting the events that occur during the data commu- nication. the following types of interrupts can be generated: ? receive data available interrupts, signalled by spi1rxif (ifs0<25>), spi2rxif (ifs1<7>). this event occurs when there is new data assembled in the spixbuf receive buffer. ? transmit buffer empty interrupts, signalled by spi1txif (ifs0<24>), spi2txif (ifs1<6>). this event occurs when there is space available in the spixbuf transmit buffer and new data can be written. ? receive buffer overflow interrupts, signalled by spi1eif (ifs0<23>), spi2eif(ifs1<5>). this event occurs when there is an overflow condition for the spixbuf receive buffer, i.e., new receive data assembled but the previous one is not read. an spi device is enabled as a source of interrupts via the respective spi interrupt enable bits: ? spi1rxie (iec0<25>) and spi2rxie (iec1<7>) ? spi1txie (iec0<24>) and spi2txie (iec1<6>) ? spi1eie (iec0<23>) and spi2eie (iec1<5>) the interrupt priority level bits and interrupt subpriority level bits must be also be configured: ? spi1ip (ipc5<28:26>), spi1is (ipc5<25:24>) ? spi2ip (ipc7<28:26>), spi2is (ipc7<25:24>) in addition to enabling the spi interrupts, an interrupt service routine, isr, is required. example 17-3 is a partial code example of an isr. example 17-3: spi initialization with interrupts enabled note: it is the user?s responsibility to clear the corresponding interrupt flag bit before returning from an isr. /* the following code example illustrates an spi1 interrupt configuration. when the spi1 interrupt is generated, the cpu will jump to the vector assigned to spi1 interrupt. it assumes that none of the spi1 input pins are shared with an analog input. if so, the ad1pcfg and corresponding tris registers have to be properly configured. */ int rdata; iec0clr=0x03800000; // disable all spi interrupts spi1con = 0; // stops and resets the spi1. rdata=spi1buf; // clears the receive buffer ifs0clr=0x03800000; // clear any existing event ipc5clr=0x1f000000; // clear the priority ipc5set=0x0d000000; // set ipl=3, subpriority 1 iec0set=0x03800000; // enable rx, tx and error interrupts spi1brg=0x1; // use f pb /4 clock frequency spi1statclr=0x40; // clear the overflow spi1con=0x8220; // spi on, 8 bits transfer, smp=1, master mode
? 2008 microchip technology inc. preliminary ds61143e-page 407 pic32mx3xx/4xx example 17-4: spi1 isr /* the following code example demonstrates a simple interrupt service routine for spi1 interrupts. the user?s code at this vector should perform any application specific operations and must clear the spi1 interrupt flags before exiting. */ void __isr(_spi_1_vector, ipl3) __spi1interrupt(void) { // ... perform application specific operations in response to the interrupt ifs0clr = 0x03800000; // be sure to clear the spi1 interrupt flags // before exiting the service routine. } note: the spi1 isr code example shows mplab ? c32 c compiler-specific syntax. refer to your compiler manual regarding support for isrs.
pic32mx3xx/4xx ds61143e-page 408 preliminary ? 2008 microchip technology inc. 17.4 i/o pin control enabling the spi modules will configure the i/o pin direction as defined by the spi control bits (see table 17-7). the port tris and latch registers will be overridden. table 17-7: i/o pin configuration for use with spi modules required settings for module pin control io pin name required module control (3) bit field (3) tris (4) pin type buffer type description sck1, sck2 yes on and msten ?x o cmos spi1, spi2 module clock output in master mode. sck1, sck2 yes on and msten ?x (5) icmos spi1, spi2 module clock input in slave mode. sdi1, sdi2 yes on ? x (5) i cmos spi1, spi2 module data receive pin. sdo1, sdo2 yes (1) on dissdo x o cmos spi1, spi2 module data transmit pin. ss1 , ss2 yes (2) on and frmen and msten ssen x (5) i cmos spi1, spi2 module slave select control pin. ss1 , ss2 yes on and frmen and frmsync ?x (5) i cmos spi1, spi2 frame sync pulse input in frame mode. ss1 , ss2 yes on and frmen and frmsync ? x o cmos spi1,spi2 frame sync pulse output in frame mode. legend: cmos = cmos compatible input or output; st = schmitt trigger input with cmos levels; i = input; o = output; x = don?t care note 1: the sdo pins are only required when spi data output is needed. otherwise, these pins can be used for general purpose i/o and require the user to set the corresponding tris control register bits. 2: the slave select pins are only required when a select signal to the slave device is needed. otherwise, these pins can be used for general purpose i/o and require the user to set the corresponding tris control register bits. 3: these bits are contained in the spixcon register. 4: the setting of the tris bit is irrelevant. 5: if the input pin is shared with an analog input, then the ad1pcfg and the corresponding tris register have to be properly set to configure this input as digital.
? 2008 microchip technology inc. preliminary ds61143e-page 409 pic32mx3xx/4xx 18.0 inter-integrated circuit (i 2 c?) the inter-integrated circuit (i 2 c) module provides complete hardware support for both slave and multi- master modes of the i 2 c serial communication standard. figure 18-1 shows the i 2 c module block diagram. the pic32mx3xx/4xx devices have up to two i 2 c interface modules, denoted as i2c1 and i2c2. each i 2 c module has a 2-pin interface: the sclx pin is clock and the sdax pin is data. each i 2 c module ?i2cx? (x = 1 or 2) offers the following key features: ?i 2 c interface supporting both master and slave operation. ?i 2 c slave mode supports 7 and 10-bit address. ?i 2 c master mode supports 7 and 10-bit address. ?i 2 c port allows bidirectional transfers between master and slaves. ? serial clock synchronization for i 2 c port can be used as a handshake mechanism to suspend and resume serial transfer (sclrel control). ?i 2 c supports multi-master operation; detects bus collision and arbitrates accordingly. ? provides support for address bit masking. 18.1 operating modes the hardware fully implements all the master and slave functions of the i 2 c standard and fast mode specifications, as well as 7 and 10-bit addressing. the i 2 c module can operate either as a slave or a master on an i 2 c bus. the following types of i 2 c operation are supported: ?i 2 c slave operation with 7 or 10-bit address ?i 2 c master operation with 7 or 10-bit address for details about the communication sequence in each of these modes, please refer to the ? pic32mx3xx/4xx reference manual ? (ds61132). 18.2 i 2 c registers the i2cxcon register allows control of the module?s operation. the i2cxcon register is readable and writ- able. i2cxstat register contains status flags indicating the module?s state during operation. i2cxrcv is the receive register. when the incoming data is shifted completely, it is moved to the i2cxrcv register. i2cxtrn is the transmit register to which bytes are written during a transmit operation. the i2cxadd register holds the slave address. a status bit, add10, indicates 10-bit addressing mode. the i2cxbrg acts as the baud rate generator (brg) reload value. in receive operations, i2cxrsr and i2cxrcv together form a double-buffered receiver. when i2cxrsr receives a complete byte, it is transferred to i2cxrcv and an interrupt pulse is generated. the i2cxrsr shift register is not directly accessable to the programmer. 18.3 i 2 c interrupts the i 2 c module generates three interrupt signals: slave interrupt (i2cxsif), master interrupt (i2cxmif) and bus collision interrupt (i2cxbif). 18.4 baud rate generator in i 2 c master mode, the reload value for the baud rate generator (brg) resides in the i2cxbrg register. when the brg is loaded with this value, the brg counts down to ? 0 ? and stops until another reload has taken place. if clock arbitration is taking place, for instance, the brg is reloaded when the sclx pin is sampled high. as per the i 2 c standard, f scl may be 100 khz or 400 khz. however, the user can specify any baud rate up to 1 mhz. i2cxbrg values of ? 0 ? or ? 1 ? are illegal. equation 18-1: serial clock rate pbclk is the peripheral clock speed. fscl is the desired i 2 c bus speed. note: this data sheet summarizes the features of the pic32mx3xx/4xx family of devices. it is not intended to be a comprehensive refer- ence source. refer to the ?pic32mx family reference manual? (ds61132) for a detailed description of this peripheral. pbclk i2c x brg = fscl x 2 - 2 [ ]
pic32mx3xx/4xx ds61143e-page 410 preliminary ? 2008 microchip technology inc. figure 18-1: i 2 c? block diagram ( x = 1 or 2) internal data bus sclx sdax shift match detect i2cxadd start and stop bit detect clock address match clock stretching i2cxtrn lsb shift clock brg down counter reload control pbclk start and stop bit generation acknowledge generation collision detect i2cxcon i2cxstat control logic read lsb write read i2cxbrg i2cxrsr write read write read write read write read write read i2cxmsk i2cxrcv
? 2008 microchip technology inc. preliminary ds61143e-page 411 pic32mx3xx/4xx 18.5 i 2 c module addresses the i2cxadd register contains the slave mode addresses. the register is a 10-bit register. if the a10m bit (i2cxcon<10>) is ? 0 ?, the address is interpreted by the module as a 7-bit address. when an address is received, it is compared to the 7 least significant bits of the i2cxadd register. if the a10m bit is ? 1 ?, the address is assumed to be a 10-bit address. when the first address byte is received, it will be compared with the binary value, ? 11110 a9 a8 r/w = 0 (where a9 and a8 are most significant bits of the 10-bit address stored in i2cxadd). if that value matches, the next address byte will be compared with the least significant 8 bits of i2cxadd, as specified in the 10-bit addressing protocol. table 18-1: 7-bit i 2 c? slave addresses supported by pic32mx3xx/4xx 18.6 slave address masking the i2cxmsk register (register 18-4) designates address bit positions as ?don?t care? (= 1 ) for both 7-bit and 10-bit addressing modes. setting a particular bit location (= 1 ) in the i2cxmsk register, causes the slave module to respond, whether the corresponding address bit value is a ? 0 ? or ? 1 ?. for example, when i2cxmsk is set to ? 00110000 ?, the slave module will detect both addresses, ? 0000000 ? and ? 00100000 ?. 18.7 strict addressing support the control bit, strict, enables the module to support the strict addressing. it enables the module to enforce all reserved addresses if they fall within the reserved address table. if the user wants to enforce the reserved address space, the strict (i2cxcon<11>) bit must be set to ? 1 ?. once the bit is set, the device will not acknowledge reserved addresses, regardless of the address mask settings. 18.8 general call address support the general call address is used to address all devices. when this address is used, all devices should, in theory, respond with an acknowledgement. the general call address is one of eight addresses reserved for specific purposes by the i 2 c protocol. it consists of all ? 0 ?s with r/w = 0 . the general call address is recognized when the general call enable (gcen) bit is set (i2cxcon<7> = 1 ). when the interrupt is serviced, the source for the interrupt can be checked by reading the contents of the i2cxrcv to determine if the address was device-specific or a general call address. upon detection of general call address, gcstat (i2cxstat<9>) bit is set. this method is available in both 7-bit and 10-bit addressing modes. 18.9 automatic clock stretch in slave modes, the module can synchronize buffer reads and writes to the master device by clock stretching. 18.9.1 transmit clock stretching both 10-bit and 7-bit transmit modes implement clock stretching by asserting the sclrel bit after the falling edge of the ninth clock, if the tbf bit is cleared, indicating the buffer is empty. in slave transmit modes, clock stretching is always performed, irrespective of the stren bit. the user?s isr must set the sclrel bit before transmission is allowed to continue. by holding the sclx line low, the user has time to service the isr and load the contents of the i2cxtrn before the master device can initiate another transmit sequence. 18.9.2 receive clock stretching the stren bit in the i2cxcon register can be used to enable clock stretching in slave receive mode. when the stren bit is set, the sclx pin will be held low at the end of each data receive sequence. the user?s isr must set the sclrel bit before recep- tion is allowed to continue. by holding the sclx line low, the user has time to service the isr and read the contents of the i2cxrcv before the master device can initiate another receive sequence. this will prevent buf- fer overruns from occurring. 18.10 software controlled clock stretching (stren = 1 ) when the stren bit is ? 1 ?, the sclrel bit may be cleared by software to allow software to control the clock stretching. if the stren bit is ? 0 ?, a software write to the sclrel bit will be disregarded and have no effect on the sclrel bit. 0x00 general call address or start byte 0x01-0x03 reserved 0x04-0x07 hs mode master codes 0x08-0x77 valid 7-bit addresses 0x78-0x7b 10-bit address upper byte 0x7c-0x7f reserved
pic32mx3xx/4xx ds61143e-page 412 preliminary ? 2008 microchip technology inc. 18.11 slope control the i 2 c standard requires slope control on the sdax and sclx signals for fast mode (400 khz). the control bit, disslw, enables the user to disable slew rate control if desired. it is necessary to disable the slew rate control for 1 mhz mode. 18.12 clock arbitration clock arbitration occurs when the master deasserts the sclx pin (sclx allowed to go high by external pull-up resistors) during any receive, transmit or restart/stop condition. when the sclx pin is allowed to float high, the baud rate generator (brg) is suspended from counting until the sclx pin is actually sampled high. when the sclx pin is sampled high, the baud rate generator is reloaded with the contents of i2cxbrg and begins counting. this ensures that the sclx high time will always be at least one brg rollover count in the event that the clock is held low by an external device. 18.13 multi-master communication, bus collision and bus arbitration multi-master mode support is achieved by bus arbitration. when the master outputs address/data bits onto the sdax pin, arbitration takes place when the master outputs a ? 1 ? on sdax by letting sdax float high while another master asserts a ? 0 ?. when the sclx pin floats high, data should be stable. if the expected data on sdax is a ? 1 ? and the data sampled on the sdax pin = 0 , then a bus collision has taken place. the master will set the i 2 c master events interrupt flag and reset the master portion of the i 2 c port to its idle state. figure 18-2: typical i 2 c? interconnection bl ock diagram scl x sda x pic32mx3xx/4xx sda scl v dd v dd 4.7 k 24lc256 (typical)
? 2008 microchip technology inc. preliminary ds61143e-page 413 pic32mx3xx/4xx table 18-2: i2c1 sfr summary table 18-3: i2c1 interrupt register summary virtual address name bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 bf80_5000 i2c1con 31:24 ? ? ? ? ? ? ? ? 23:16 ? ? ? ? ? ? ? ? 15:8 on frz sidl sclrel strict a10m disslw smen 7:0 gcen stren ackdt acken rcen pen rsen sen bf80_0004 i2c1conclr 31:0 clears selected bits of i2c1con, read yields undefined value bf80_5008 i2c1conset 31:0 sets selected bits of i2c1con, read yields undefined value bf80_500c i2c1coninv 31:0 inverts selected bits of i2c1con, read yields undefined value bf80_5010 i2c1stat 31:24 ? ? ? ? ? ? ? ? 23:16 ? ? ? ? ? ? ? ? 15:8 ackstat trstat ? ? ? bcl gcstat add10 7:0 iwcol i2cov d/a p s r/w rbf tbf bf80_5014 i2c1statclr 31:0 clears selected bits of i2c1stat, read yields undefined value bf80_5018 i2c1statset 31:0 sets selected bits of i2c1stat, read yields undefined value bf80_501c i2c1statinv 31:0 inverts selected bits of i2c1stat, read yields undefined value bf80_5020 i2c1add 31:24 ? ? ? ? ? ? ? ? 23:16 ? ? ? ? ? ? ? ? 15:8 ? ? ? ? ? ? add<9:8> 7:0 add<7:0> bf80_5024 i2c1addclr 31:0 clears selected bits of i2c1add, read yields undefined value bf80_5028 i2c1addset 31:0 sets selected bits of i2c1add, read yields undefined value bf80_502c i2c1addinv 31:0 inverts selected bits of i2c1add, read yields undefined value bf80_5030 i2c1msk 31:24 ? ? ? ? ? ? ? ? 23:16 ? ? ? ? ? ? ? ? 15:8 ? ? ? ? ? ? msk<9:8> 7:0 msk<7:0> bf80_5034 i2c1mskclr 31:0 clears selected bits of i2c1msk, read yields undefined value bf80_5038 i2c1mskset 31:0 sets selected bits of i2c1msk, read yields undefined value bf80_503c i2c1mskinv 31:0 inverts selected bits of i2c1msk, read yields undefined value bf80_5040 i2c1brg 31:24 ? ? ? ? ? ? ? ? 23:16 ? ? ? ? ? ? ? ? 15:8 ? ? ? ? i2c1brg<11:8> 7:0 i2c1brg<7:0> bf80_5044 i2c1brgclr 31:0 clears selected bits of i2c1brg, read yields undefined value bf80_5048 i2c1brgset 31:0 sets selected bits of i2c1brg, read yields undefined value bf80_504c i2c1brginv 31:0 inverts selected bits of i2c1brg, read yields undefined value bf80_5050 i2c1trn 31:24 ? ? ? ? ? ? ? ? 23:16 ? ? ? ? ? ? ? ? 15:8 ? ? ? ? ? ? ? ? 7:0 i2ct1data bf80_5054 i2c1trnclr 31:0 clears selected bits of i2c1trn, read yields undefined value bf80_5058 i2c1trnset 31:0 sets selected bits of i2c1trn, read yields undefined value bf80_505c i2c1trninv 31:0 inverts selected bits of i2c1trn, read yields undefined value bf80_5060 i2c1rcv 31:24 ? ? ? ? ? ? ? ? 23:16 ? ? ? ? ? ? ? ? 15:8 ? ? ? ? ? ? ? ? 7:0 i2cr1data virtual address name bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 bf88_1060 iec0 31:24 i2c1mie i2c1sie i2c1bie u1txie u1rxie u1eie spi1rxie spi1txie bf88_1030 ifs0 31:24 i2c1mif i2c1sif i2c1bif u1txif u1rxif u1eif spi1rxif spi1txif bf88_10f0 ipc6 15:8 ? ? ? i2c1ip<2:0> i2c1is<1:0> note: this summary table contains partial register definitions that only pertain to the i2c1 peripheral. refer to the ? pic32mx family reference manual ? (ds61132) for a detailed description of these registers.
pic32mx3xx/4xx ds61143e-page 414 preliminary ? 2008 microchip technology inc. table 18-4: i2c2 sfr summary table 18-5: i2c2 interrupt register summary virtual address name bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 bf80_5200 i2c2con 31:24 ? ? ? ? ? ? ? ? 23:16 ? ? ? ? ? ? ? ? 15:8 on frz sidl sclrel strict a10m disslw smen 7:0 gcen stren ackdt acken rcen pen rsen sen bf80_5204 i2c2conclr 31:0 clears selected bits of i2c2con, read yields undefined value bf80_5208 i2c2conset 31:0 sets selected bits of i2c2con, read yields undefined value bf80_520c i2c2coninv 31:0 inverts selected bits of i2c2con, read yields undefined value bf80_5210 i2c2stat 31:24 ? ? ? ? ? ? ? ? 23:16 ? ? ? ? ? ? ? ? 15:8 ackstat trstat ? ? ? bcl gcstat add10 7:0 iwcol i2cov d/a p s r/w rbf tbf bf80_5214 i2c2statclr 31:0 clears selected bits of i2c2stat, read yields undefined value bf80_5218 i2c2statset 31:0 sets selected bits of i2c2stat, read yields undefined value bf80_521c i2c2statinv 31:0 inverts selected bits of i2c2stat, read yields undefined value bf80_5220 i2c2add 31:24 ? ? ? ? ? ? ? ? 23:16 ? ? ? ? ? ? ? ? 15:8 ? ? ? ? ? ? add<9:8> 7:0 add<7:0> bf80_5224 i2c2addclr 31:0 clears selected bits of i2c2add, read yields undefined value bf80_5228 i2c2addset 31:0 sets selected bits of i2c2add, read yields undefined value bf80_522c i2c2addinv 31:0 inverts selected bits of i2c2add, read yields undefined value bf80_5230 i2c2msk 31:24 ? ? ? ? ? ? ? ? 23:16 ? ? ? ? ? ? ? ? 15:8 ? ? ? ? ? ? msk<9:8> 7:0 msk<7:0> bf80_5234 i2c2mskclr 31:0 clears selected bits of i2c2msk, read yields undefined value bf80_5238 i2c2mskset 31:0 sets selected bits of i2c2msk, read yields undefined value bf80_523c i2c2mskinv 31:0 inverts selected bits of i2c2msk, read yields undefined value bf80_5240 i2c2brg 31:24 ? ? ? ? ? ? ? ? 23:16 ? ? ? ? ? ? ? ? 15:8 ? ? ? ? i2c2brg<11:8> 7:0 i2c2brg<7:0> bf80_5244 i2c2brgclr 31:0 clears selected bits of i2c2brg, read yields undefined value bf80_5248 i2c2brgset 31:0 sets selected bits of i2c2brg, read yields undefined value bf80_524c i2c2brginv 31:0 inverts selected bits of i2c2brg, read yields undefined value bf80_5250 i2c2trn 31:24 ? ? ? ? ? ? ? ? 23:16 ? ? ? ? ? ? ? ? 15:8 ? ? ? ? ? ? ? ? 7:0 i2ct1data bf80_5254 i2c2trnclr 31:0 clears selected bits of i2c2trn, read yields undefined value bf80_5258 i2c2trnset 31:0 sets selected bits of i2c2trn, read yields undefined value bf80_525c i2c2trninv 31:0 inverts selected bits of i2c2trn, read yields undefined value bf80_5260 i2c2rcv 31:24 ? ? ? ? ? ? ? ? 23:16 ? ? ? ? ? ? ? ? 15:8 ? ? ? ? ? ? ? ? 7:0 i2cr1data virtual address name bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 bf88_1070 iec1 15:8 rtccie fscmie i2c2mie i2c2sie i2c2bie u2txie u2rxie u2eie bf88_1040 ifs1 15:8 rtccif fscmif i2c2mif i2c2sif i2c2bif u2txif u2rxif u2eif bf88_1110 ipc8 15:8 ? ? ? i2c2ip<2:0> i2c2is<1:0> note: this summary table contains partial register definitions that only pertain to the i2c2 peripheral. refer to the ? pic32mx family reference manual ? (ds61132) for a detailed description of these registers.
? 2008 microchip technology inc. preliminary ds61143e-page 415 pic32mx3xx/4xx register 18-1: i2c x con: i 2 c? control register r-x r-x r-x r-x r-x r-x r-x r-x ? ? ? ? ? ? ? ? bit 31 bit 24 r-x r-x r-x r-x r-x r-x r-x r-x ? ? ? ? ? ? ? ? bit 23 bit 16 r/w-0 r/w-0 r/w-0 r/w-1 r/w-0 r/w-0 r/w-0 r/w-0 on frz sidl sclrel strict a10m disslw smen bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 gcen stren ackdt acken rcen pen rsen sen bit 7 bit 0 legend: r = readable bit w = writable bit p = programmable bit r = reserved bit u = unimplemented bit -n = bit value at por: (?0?, ?1?, x = unknown) bit 31-16 reserved: write ? 0 ?; ignore read bit 15 on: i 2 c enable bit 1 = enables the i 2 c module and configures the sda and scl pins as serial port pins 0 = disables i 2 c module; all i 2 c pins are controlled by port functions bit 14 frz: freeze in debug mode control bit 1 = freeze module operation when in debug mode 0 = do not freeze module operation when in debug mode note: frz is writable in debug exception mode only, it is forced to ? 0 ? in normal mode. bit 13 sidl: stop in idle mode bit 1 = discontinue module operation when device enters idle mode 0 = continue module operation in idle mode bit 12 sclrel: scl release control bit in i 2 c slave mode only module reset and (on = 0 ) sets sclrel = 1 if stren = 0 : 1 = release clock 0 = force clock low (clock stretch) note: automatically cleared to ? 0 ? at beginning of slave transmission. if stren = 1 : 1 = release clock 0 = holds clock low (clock stretch). user may program this bit to ? 0 ? to force a clock stretch at the next scl low. note: automatically cleared to ? 0 ? at beginning of slave transmission; automatically cleared to ? 0 ? at end of slave reception. bit 11 strict: strict i 2 c reserved address rule enable bit 1 = strict reserved addressing is enforced. device doesn?t respond to reserved address space or generate addresses in reserved address space. 0 = strict i 2 c reserved address rule not enabled
pic32mx3xx/4xx ds61143e-page 416 preliminary ? 2008 microchip technology inc. bit 10 a10m: 10-bit slave address flag bit 1 = i2cxadd is a 10-bit slave address 0 = i2cadd is a 7-bit slave address bit 9 disslw: slew rate control disable bit 1 = slew rate control disabled for standard speed mode (100 khz); also disabled for 1 mhz mode 0 = slew rate control enabled for high-speed mode (400 khz) bit 8 smen: smbus input levels disable bit 1 = enable input logic so that thresholds are compliant with smbus specification 0 = disable smbus specific inputs bit 7 gcen: general call enable bit in i 2 c slave mode only 1 = enable interrupt when a general call address is received in i2csr. module is enabled for reception 0 = general call address disabled bit 6 stren: scl clock stretch enable bit in i 2 c slave mode only; used in conjunction with sclrel bit. 1 = enable clock stretching 0 = disable clock stretching bit 5 ackdt: acknowledge data bit in i 2 c master mode only; applicable during master receive. value that will be transmitted when the user initiates an acknowledge sequence at the end of a receive. 1 = a nack is sent 0 = ack is sent bit 4 acken: acknowledge sequence enable bit in i 2 c master mode only; applicable during master receive 1 = initiate acknowledge sequence on sda and scl pins, and transmit ackdt data bit; cleared by module 0 = acknowledge sequence idle bit 3 rcen: receive enable bit in i 2 c master mode only. 1 = enables receive mode for i 2 c, automatically cleared by module at end of 8-bit receive data byte 0 = receive sequence not in progress bit 2 pen: stop condition enable bit in i 2 c master mode only. 1 = initiate stop condition on sda and scl pins; cleared by module 0 = stop condition idle bit 1 rsen: restart condition enable bit in i 2 c master mode only. 1 = initiate restart condition on sda and scl pins; cleared by module 0 = restart condition idle bit 0 sen: start condition enable bit in i 2 c master mode only. 1 = initiate start condition on sda and scl pins; cleared by module 0 = start condition idle register 18-1: i2c x con: i 2 c? control register (continued)
? 2008 microchip technology inc. preliminary ds61143e-page 417 pic32mx3xx/4xx register 18-2: i2c x stat: i 2 c status register r-x r-x r-x r-x r-x r-x r-x r-x ? ? ? ? ? ? ? ? bit 31 bit 24 r-x r-x r-x r-x r-x r-x r-x r-x ? ? ? ? ? ? ? ? bit 23 bit 16 r-0 r-0 r-x r-x r-x r/w-0 r-0 r-0 ackstat trstat ? ? ? bcl gcstat add10 bit 15 bit 8 r/w-0 r/w-0 r-0 r/w-0 r/w-0 r-0 r-0 r-0 iwcol i2cov d/a psr/w rbf tbf bit 7 bit 0 legend: r = readable bit w = writable bit p = programmable bit r = reserved bit u = unimplemented bit -n = bit value at por: (?0?, ?1?, x = unknown) bit 31-16 reserved: write ? 0 ?; ignore read bit 15 ackstat: acknowledge status bit in both i 2 c master and slave modes; applicable to both transmit and receive. 1 = acknowledge was not received 0 = acknowledge was received bit 14 trstat: transmit status bit in i 2 c master mode only; applicable to master transmit mode. 1 = master transmit is in progress (8 bits + ack ) 0 = master transmit is not in progress bit 13-11 reserved: write ? 0 ?; ignore read bit 10 bcl: master bus collision detect bit cleared when the i 2 c module is disabled (on = 0 ). 1 = a bus collision has been detected during a master operation 0 = no collision has been detected bit 9 gcstat: general call status bit cleared after stop detection. 1 = general call address was received 0 = general call address was not received bit 8 add10: 10-bit address status bit cleared after stop detection. 1 = 10-bit address was matched 0 = 10-bit address was not matched bit 7 iwcol: write collision detect bit 1 = an attempt to write the i2cxtrn register collided because the i 2 c module is busy. must be cleared in software. 0 = no collision
pic32mx3xx/4xx ds61143e-page 418 preliminary ? 2008 microchip technology inc. bit 6 i2cov: i 2 c receive overflow status bit 1 = a byte is received while the i2cxrcv register is still holding the previous byte. i2cov is a ?don?t care? in transmit mode. must be cleared in software. 0 = no overflow bit 5 d/a : data/address bit valid only for slave mode operation. 1 = indicates that the last byte received or transmitted was data 0 = indicates that the last byte received or transmitted was address bit 4 p: stop bit updated when start, reset or stop detected; cleared when the i 2 c module is disabled (on = 0 ). 1 = indicates that a stop bit has been detected last 0 = stop bit was not detected last bit 3 s: start bit updated when start, reset or stop detected; cleared when the i 2 c module is disabled (on = 0 ). 1 = indicates that a start (or restart) bit has been detected last 0 = start bit was not detected last bit 2 r/w : read/write information bit valid only for slave mode operation. 1 = read ? indicates data transfer is output from slave 0 = write ? indicates data transfer is input to slave bit 1 rbf: receive buffer full status bit 1 = receive complete; i2cxrcv is full 0 = receive not complete; i2cxrcv is empty bit 0 tbf: transmit buffer full status bit 1 = transmit in progress; i2cxtrn is full (8-bits of data) 0 = transmit complete; i2cxtrn is empty register 18-2: i2c x stat: i 2 c status register (continued)
? 2008 microchip technology inc. preliminary ds61143e-page 419 pic32mx3xx/4xx register 18-3: i2c x add: i 2 c slave address register r-x r-x r-x r-x r-x r-x r-x r-x ? ? ? ? ? ? ? ? bit 31 bit 24 r-x r-x r-x r-x r-x r-x r-x r-x ? ? ? ? ? ? ? ? bit 23 bit 16 r-x r-x r-x r-x r-x r-x r/w-0 r/w-0 ? ? ? ? ? ?add<9:8> bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 add<7:0> bit 7 bit 0 legend: r = readable bit w = writable bit p = programmable bit r = reserved bit u = unimplemented bit -n = bit value at por: (?0?, ?1?, x = unknown) bit 31-10 reserved: write ? 0 ?; ignore read bit 9-0 add<9:0>: i 2 c slave device address bits either master or slave mode.
pic32mx3xx/4xx ds61143e-page 420 preliminary ? 2008 microchip technology inc. register 18-4: i2c x msk: i 2 c address mask register r-x r-x r-x r-x r-x r-x r-x r-x ? ? ? ? ? ? ? ? bit 31 bit 24 r-x r-x r-x r-x r-x r-x r-x r-x ? ? ? ? ? ? ? ? bit 23 bit 16 r-x r-x r-x r-x r-x r-x r/w-0 r/w-0 ? ? ? ? ? ? msk<9:8> bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 msk<7:0> bit 7 bit 0 legend: r = readable bit w = writable bit p = programmable bit r = reserved bit u = unimplemented bit -n = bit value at por: (?0?, ?1?, x = unknown) bit 31-10 reserved: write ? 0 ?; ignore read bit 9-0 msk<9:0>: i 2 c address mask bits 1 = forces a ?don?t care? in the particular bit position on the incoming address match sequence 0 = address bit position must match the incoming i 2 c address match sequence note: msk<9:8> and msk<0> are only used in i 2 c 10-bit mode.
? 2008 microchip technology inc. preliminary ds61143e-page 421 pic32mx3xx/4xx register 18-5: i2c x brg: i 2 c baud rate generator register r-x r-x r-x r-x r-x r-x r-x r-x ? ? ? ? ? ? ? ? bit 31 bit 24 r-x r-x r-x r-x r-x r-x r-x r-x ? ? ? ? ? ? ? ? bit 23 bit 16 r-x r-x r-x r-x r/w-0 r/w-0 r/w-0 r/w-0 ? ? ? ? i2cxbrg<11:8> bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 i2cxbrg<7:0> bit 7 bit 0 legend: r = readable bit w = writable bit p = programmable bit r = reserved bit u = unimplemented bit -n = bit value at por: (?0?, ?1?, x = unknown) bit 31-12 reserved: write ? 0 ?; ignore read bit 11-0 i2cxbrg<11:0>: i 2 c baud rate generator value bits a divider function of the peripheral clock.
pic32mx3xx/4xx ds61143e-page 422 preliminary ? 2008 microchip technology inc. register 18-6: i2c x trn: i 2 c transmit data register r-x r-x r-x r-x r-x r-x r-x r-x ? ? ? ? ? ? ? ? bit 31 bit 24 r-x r-x r-x r-x r-x r-x r-x r-x ? ? ? ? ? ? ? ? bit 23 bit 16 r-x r-x r-x r-x r-x r-x r-x r-x ? ? ? ? ? ? ? ? bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 i2ctxdata<7:0> bit 7 bit 0 legend: r = readable bit w = writable bit p = programmable bit r = reserved bit u = unimplemented bit -n = bit value at por: (?0?, ?1?, x = unknown) bit 31-8 reserved: write ? 0 ?; ignore read bit 7-0 i2ctxdata<7:0>: i 2 c transmit data buffer bits
? 2008 microchip technology inc. preliminary ds61143e-page 423 pic32mx3xx/4xx register 18-7: i2cxrcv: i 2 c receive data register r-x r-x r-x r-x r-x r-x r-x r-x ? ? ? ? ? ? ? ? bit 31 bit 24 r-x r-x r-x r-x r-x r-x r-x r-x ? ? ? ? ? ? ? ? bit 23 bit 16 r-x r-x r-x r-x r-x r-x r-x r-x ? ? ? ? ? ? ? ? bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 i2crxdata<7:0> bit 7 bit 0 legend: r = readable bit w = writable bit p = programmable bit r = reserved bit u = unimplemented bit -n = bit value at por: (?0?, ?1?, x = unknown) bit 31-8 reserved: write ? 0 ?; ignore read bit 7-0 i2crxdata<7:0>: i 2 c receive data buffer bits
pic32mx3xx/4xx ds61143e-page 424 preliminary ? 2008 microchip technology inc. notes:
? 2008 microchip technology inc. preliminary ds61143e-page 425 pic32mx3xx/4xx 19.0 universal asynchronous receiver transmitter (uart) the universal asynchronous receiver transmitter (uart) module is one of the serial i/o modules avail- able in pic32mx3xx/4xx family devices. the uart is a full-duplex, asynchronous communication channel that communicates with peripheral devices and per- sonal computers through protocols such as rs-232, rs-485, lin 1.2 and irda ? . the module also supports the hardware flow control option, with uxcts and uxrts pins, and also includes the irda encoder and decoder. the primary features of the uart module are: ? full-duplex, 8-bit or 9-bit data transmission ? even, odd or no parity options (for 8-bit data) ? one or two stop bits ? hardware auto-baud feature ? hardware flow control option ? fully integrated baud rate generator (brg) with 16-bit prescaler ? baud rates ranging from 76 bps to 20 mbps at 80 mhz ? 4-level-deep first-in-first-out (fifo) transmit data buffer ? 4-level-deep fifo receive data buffer ? parity, framing and buffer overrun error detection ? support for interrupt only on address detect (9th bit = 1 ) ? separate transmit and receive interrupts ? loopback mode for diagnostic support ? lin 1.2 protocol support ? irda encoder and decoder with 16x baud clock output for external irda encoder/decoder support figure 19-1 shows a simplified block diagram of the uart. figure 19-1: uart simplified block diagram note: this data sheet summarizes the features of the pic32mx3xx/4xx family of devices. it is not intended to be a comprehensive refer- ence source. refer to the ?pic32mx family reference manual? (ds61132) for a detailed description of this peripheral. baud rate generator uxrx hardware flow control uartx receiver uartx transmitter uxtx uxcts uxrts bclkx irda ?
pic32mx3xx/4xx ds61143e-page 426 preliminary ? 2008 microchip technology inc. 19.1 uart registers table 19-1: uart1 sfr summary virtual address name bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 bf80_6000 u1mode 31:24 ? ? ? ? ? ? ? ? 23:16 ? ? ? ? ? ? ? ? 15:8 on frz sidl iren rtsmd ? uen<1:0> 7:0 wake lpback abaud rxinv brgh pdsel<2:0> stsel bf80_6004 u1modeclr 31:0 write clears selected bits in u1mode, read yields undefined value bf80_6008 u1modeset 31:0 write sets selected bits in u1mode, read yields undefined value bf80_600c u1modeinv 31:0 write inverts selected bits in u1mode, read yields undefined value bf80_6010 u1sta 31:24 ? ? ? ? ? ? ?adm_en 23:16 addr<7:0> 15:8 utxisel<1:0> utxinv urxen utxbrk utxen utxbf trmt 7:0 urxisel<1:0> adden ridle perr ferr oerr rxda bf80_6014 u1staclr 31:0 write clears selected bits in u1sta, read yields undefined value bf80_6018 u1staset 31:0 write sets selected bits in u1sta, read yields undefined value bf80_601c u1stainv 31:0 write inverts selected bits in u1sta, read yields undefined value bf80_6020 u1txreg 31:24 ? ? ? ? ? ? ? ? 23:16 ? ? ? ? ? ? ? ? 15:8 ? ? ? ? ? ? ?tx8 7:0 transmit register bf80_6030 u1rxreg 31:24 ? ? ? ? ? ? ? ? 23:16 ? ? ? ? ? ? ? ? 15:8 ? ? ? ? ? ? ?rx8 7:0 receive register bf80_6040 u1brg 31:24 ? ? ? ? ? ? ? ? 23:16 ? ? ? ? ? ? ? ? 15:8 brg<15:8> 7:0 brg<7:0> bf80_6044 u1brgclr 31:0 write clears selected bits in u1brg, read yields undefined value bf80_6048 u1brgset 31:0 write sets selected bits in u1brg, read yields undefined value bf80_604c u1brginv 31:0 write inverts selected bits in u1brg, read yields undefined value table 19-2: uart1 interrupt register summary virtual address name bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 bf88_1060 iec0 31:24 ? ? ? u1txie u1rxie u1eie ? ? bf88_1030 ifs0 31:24 ? ? ? u1txif u1rxif u1eif ? ? bf88_10f0 ipc6 7:0 ? ? ? u1ip[2:0] u1is[1:0] note 1: this summary table contains partial register definitions that only pertain to the uart peripheral. refer to the pic32mx family reference man- ual for a detailed description of these registers.
? 2008 microchip technology inc. preliminary ds61143e-page 427 pic32mx3xx/4xx table 19-3: uart2 sfr summary virtual address name bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 bf80_6200 u2mode 31:24 ? ? ? ? ? ? ? ? 23:16 ? ? ? ? ? ? ? ? 15:8 on frz sidl iren rtsmd ? uen<1:0> 7:0 wake lpback abaud rxinv brgh pdsel<2:0> stsel bf80_6204 u2modeclr 31:0 write clears selected bits in u2mode, read yields undefined value bf80_6208 u2modeset 31:0 write sets selected bits in u2mode, read yields undefined value bf80_620c u2modeinv 31:0 write inverts selected bits in u2mode, read yields undefined value bf80_6210 u2sta 31:24 ? ? ? ? ? ? ?adm_en 23:16 addr<7:0> 15:8 utxisel<1:0> utxinv urxen utxbrk utxen utxbf trmt 7:0 urxisel<1:0> adden ridle perr ferr oerr rxda bf80_6214 u2staclr 31:0 write clears selected bits in u2sta, read yields undefined value bf80_6218 u2staset 31:0 write sets selected bits in u2sta, read yields undefined value bf80_621c u2stainv 31:0 write inverts selected bits in u2sta, read yields undefined value bf80_6220 u2txreg 31:24 ? ? ? ? ? ? ? ? 23:16 ? ? ? ? ? ? ? ? 15:8 ? ? ? ? ? ? ?tx8 7:0 transmit register bf80_6230 u2rxreg 31:24 ? ? ? ? ? ? ? ? 23:16 ? ? ? ? ? ? ? ? 15:8 ? ? ? ? ? ? ?rx8 7:0 receive register bf80_6240 u2brg 31:24 ? ? ? ? ? ? ? ? 23:16 ? ? ? ? ? ? ? ? 15:8 brg<15:8> 7:0 brg<7:0> bf80_6244 u2brgclr 31:0 write clears selected bits in u2brg, read yields undefined value bf80_6248 u2brgset 31:0 write sets selected bits in u2brg, read yields undefined value bf80_624c u2brginv 31:0 write inverts selected bits in u2brg, read yields undefined value table 19-4: uart2 interrupt register summary virtual address name bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 bf88_1070 iec1 15:8 ? ? ? ? ? u2txie u2rxie u2eie bf88_1040 ifs1 15:8 ? ? ? ? ? u2txif u2rxif u2eif bf88_1110 ipc8 7:0 ? ? ? u2ip<2:0> u2is<1:0>
pic32mx3xx/4xx ds61143e-page 428 preliminary ? 2008 microchip technology inc. register 19-1: uxmode: uartx mode register r-x r-x r-x r-x r-x r-x r-x r-x ? ? ? ? ? ? ? ? bit 31 bit 24 r-x r-x r-x r-x r-x r-x r-x r-x ? ? ? ? ? ? ? ? bit 23 bit 16 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 on frz sidl iren rtsmd ? uen<1:0> bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 wake lpback abaud rxinv brgh pdsel<1:0> stsel bit 7 bit 0 legend: r = readable bit w = writable bit p = programmable bit r = reserved bit u = unimplemented bit -n = bit value at por: (?0?, ?1?, x = unknown) bit 31-16 reserved: write ? 0 ?; ignore read bit 15 on: uartx enable bit 1 = uartx is enabled; uartx pins are controlled by uartx as defined by uen<1:0> and utxen control bits 0 = uartx is disabled, all uartx pins are controlled by corresponding port tris and lat bits; uartx power consumption is minimal bit 14 frz: freeze in debug exception mode bit 1 = freeze operation when cpu is in debug exception mode 0 = continue operation when cpu is in debug exception mode note: . frz is writable in debug exception mode only, it is forced to ? 0 ? in normal mode. bit 13 sidl: stop in idle mode bit 1 = discontinue operation when device enters in idle mode 0 = continue operation in idle mode bit 12 iren: irda encoder and decoder enable bit 1 = irda is enabled 0 = irda is disabled bit 11 rtsmd: mode selection for uxrts pin bit 1 = uxrts pin is in simplex mode 0 = uxrts pin is in flow control mode bit 10 unimplemented: read as ? 0 bit 9-8 uen<1:0>: uartx enable bits 11 = uxtx, uxrx, and uxbclk pins are enabled and used; uxcts pin is controlled by port latches 10 = uxtx, uxrx, uxcts, and uxrts pins are enabled and used 01 = uxtx, uxrx and uxrts pins are enabled and used; uxcts pin is controlled by port latches 00 = uxtx and uxrx pins are enabled and used; uxcts and uxrts/uxbclk pins are controlled by port latches bit 7 wake: enable wake-up on start bit detect during sleep mode bit 1 = wake-up enabled 0 = wake-up disabled
? 2008 microchip technology inc. preliminary ds61143e-page 429 pic32mx3xx/4xx bit 6 lpback: uartx loopback mode select bit 1 = enable loopback mode 0 = loopback mode is disabled bit 5 abaud: auto-baud enable bit 1 = enable baud rate measurement on the next character ? requires reception of synch character (0x55); cleared by hardware upon completion 0 = baud rate measurement disabled or completed bit 4 rxinv: receive polarity inversion bit 1 = uxrx idle state is ? 0 ? 0 = uxrx idle state is ? 1 ? bit 3 brgh: high baud rate enable bit 1 = high speed mode ? 4x baud clock enabled 0 = standard speed mode ? 16x baud clock enabled bit 2-1 pdsel<1:0>: parity and data selection bits 11 = 9-bit data, no parity 10 = 8-bit data, odd parity 01 = 8-bit data, even parity 00 = 8-bit data, no parity bit 0 stsel: stop selection bit 1 = 2 stop bits 0 = 1 stop bit register 19-1: uxmode: uartx mode register (continued)
pic32mx3xx/4xx ds61143e-page 430 preliminary ? 2008 microchip technology inc. register 19-2: uxsta: uartx status register r-x r-x r-x r-x r-x r-x r-x r/w-0 ? ? ? ? ? ? ?adm_en bit 31 bit 24 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 addr<7:0> bit 23 bit 16 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r-0 r-1 utxisel<1:0> utxinv urxen utxbrk utxen utxbf trmt bit 15 bit 8 r/w-0 r/w-0 r/w-0 r-1 r-0 r-0 r/c-0 r-0 urxisel<1:0> adden ridle perr ferr oerr rxda bit 7 bit 0 legend: r = readable bit w = writable bit p = programmable bit r = reserved bit u = unimplemented bit -n = bit value at por: (?0?, ?1?, x = unknown) bit 31-25 reserved: write ? 0 ?; ignore read bit 24 adm_en: automatic address detect mode enable bit 1 = automatic address detect mode is enabled 0 = automatic address detect mode is disabled bit 23-16 addr<7:0>: automatic address mask bits when adm_en bit is ? 1 ?, this value defines the bits that are don?t care when comparing incoming address reception bit 15-14 utxisel<1:0>: tx interrupt mode selection bits 11 = reserved, do not use 10 = interrupt is generated when the transmit buffer becomes empty 01 = interrupt is generated when all characters are transmitted 00 = interrupt is generated when the transmit buffer contains at least one empty space bit 13 utxinv: transmit polarity inversion bit if irda mode is disabled (i.e., iren (uxmod<12>) is ? 0 ?) 1 = uxtx idle state is ? 0 ? 0 = uxtx idle state is ? 1 ? if irda mode is enabled (i.e., iren (uxmod<12>) is ? 1 ?) 1 = irda encoded uxtx idle state is ? 1 ? 0 = irda encoded uxtx idle state is ? 0 ? bit 12 urxen: receiver enable bit 1 = uartx receiver is enabled, uxrx pin controlled by uartx (if on = 1) 0 = uartx receiver is disabled, the uxrx pin is ignored by the uartx module. uxrx pin controlled by port bit 11 utxbrk: transmit break bit 1 = send break on next transmission ? start bit followed by twelve ? 0 ? bits, followed by stop bit; cleared by hardware upon completion 0 = break transmission is disabled or completed
? 2008 microchip technology inc. preliminary ds61143e-page 431 pic32mx3xx/4xx bit 10 utxen: transmit enable bit 1 = uartx transmitter enabled, uxtx pin controlled by uartx (if on = 1 ) 0 = uartx transmitter disabled, any pending transmission is aborted and buffer is reset. uxtx pin controlled by port. bit 9 utxbf: transmit buffer full status bit (read-only) 1 = transmit buffer is full 0 = transmit buffer is not full, at least one more character can be written bit 8 trmt: transmit shift register is empty bit (read-only) 1 = transmit shift register is empty and transmit buffer is empty (the last transmission has completed) 0 = transmit shift register is not empty, a transmission is in progress or queued in the transmit buffer bit 7-6 urxisel<1:0>: receive interrupt mode selection bit 11 = interrupt flag bit is set when receive buffer is full (i.e., has 4 data characters) 10 = interrupt flag bit is set when receive buffer is 3/4 full (i.e., has 3 data characters) 0x = interrupt flag bit is set when a character is received bit 5 adden: address character detect (bit 8 of received data = 1 ) 1 = address detect mode enabled. if 9-bit mode is not selected, this control bit has no effect. 0 = address detect mode disabled bit 4 ridle: receiver idle bit (read-only) 1 = receiver is idle 0 = data is being received bit 3 perr: parity error status bit (read-only) 1 = parity error has been detected for the current character 0 = parity error has not been detected bit 2 ferr: framing error status bit (read-only) 1 = framing error has been detected for the current character 0 = framing error has not been detected bit 1 oerr: receive buffer overrun error status bit (clear/read-only) 1 = receive buffer has overflowed 0 = receive buffer has not overflowed (clearing a previously set oerr bit will reset the receiver buffer and receive shift register (rsr) to an empty state) bit 0 rxda: receive buffer data available bit (read-only) 1 = receive buffer has data, at least one more character can be read 0 = receive buffer is empty register 19-2: uxsta: uartx status register (continued)
pic32mx3xx/4xx ds61143e-page 432 preliminary ? 2008 microchip technology inc. register 19-3: uxrxreg: uart receive register r-x r-x r-x r-x r-x r-x r-x r-x ? ? ? ? ? ? ? ? bit 31 bit 24 r-x r-x r-x r-x r-x r-x r-x r-x ? ? ? ? ? ? ? ? bit 23 bit 16 r-x r-x r-x r-x r-x r-x r-x r-0 ? ? ? ? ? ? ?rx8 bit 15 bit 8 r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 rx<7:0> bit 7 bit 0 legend: r = readable bit w = writable bit p = programmable bit r = reserved bit u = unimplemented bit -n = bit value at por: (?0?, ?1?, x = unknown) bit 31-9 reserved: write ? 0 ?; ignore read bit 8 rx8: data bit 8 of the received character (in 9-bit mode) bit 7-0 rx<7:0>: data bits 7-0 of the received character
? 2008 microchip technology inc. preliminary ds61143e-page 433 pic32mx3xx/4xx register 19-4: uxtxreg: uartx transmit register r-x r-x r-x r-x r-x r-x r-x r-x ? ? ? ? ? ? ? ? bit 31 bit 24 r-x r-x r-x r-x r-x r-x r-x r-x ? ? ? ? ? ? ? ? bit 23 bit 16 r-x r-x r-x r-x r-x r-x r-x w-0 ? ? ? ? ? ? ?tx8 bit 15 bit 8 w-0 w-0 w-0 w-0 w-0 w-0 w-0 w-0 tx<7:0> bit 7 bit 0 legend: r = readable bit w = writable bit p = programmable bit r = reserved bit u = unimplemented bit -n = bit value at por: (?0?, ?1?, x = unknown) bit 31-9 reserved: write ? 0 ?; ignore read bit 8 tx8: data bit 8 of the character to be transmitted (in 9-bit mode) bit 7-0 tx<7:0>: data bits 7-0 of the character to be transmitted
pic32mx3xx/4xx ds61143e-page 434 preliminary ? 2008 microchip technology inc. 19.2 uart baud rate generator (brg) the uart module includes a dedicated 16-bit baud rate generator. the brgx register controls the period of a free-running 16-bit timer. equation 19-1 shows the formula for computation of the baud rate with brgh = 0 . equation 19-1: uart baud rate with brgh = 0 (1) example 19-1 shows the calculation of the baud rate error for the following conditions: ?f pb =4 mhz ? desired baud rate = 9600 the maximum possible baud rate with brgh = 0 is f pb /16. the minimum possible baud rate is f pb /(16 * 65536). equation 19-2 shows the formula for computation of the baud rate with brgh = 1 . equation 19-2: uart baud rate with brgh = 1 (1) the maximum possible baud rate with brgh = 1 is f pb /4 for uxbrg = 0 , and the minimum possible baud rate is f pb /(4 * 65536). writing a new value to the uxbrg register causes the baud rate counter to be cleared. this ensures that the brg does not wait for a timer overflow before it generates the new baud rate. example 19-1: baud rate erro r calculation (brgh = 0 ) note 1: f pb denotes the peripheral bus clock frequency. baud rate = f pb 16 ? ( uxbrg + 1) f pb 16 ? baud rate uxbrg =? 1 note 1: f pb denotes the instruction cycle clock frequency . baud rate = f pb 4 ? ( uxbrg + 1) f pb 4 ? baud rate uxbrg =? 1 desired baud rate = fpb/(16 (uxbrg + 1)) solving for uxbrg value: uxbrg = ( (fpb/desired baud rate)/16) ? 1 uxbrg = ((4000000/9600)/16) ? 1 uxbrg = [25.042] = 25 calculated baud rate = 4000000/(16 (25 + 1)) = 9615 error = (calculated baud rate ? desired baud rate) desired baud rate = (9615 ? 9600)/9600 = 0.16%
? 2008 microchip technology inc. preliminary ds61143e-page 435 pic32mx3xx/4xx 19.3 transmitting in 8-bit data mode 1. set up the uart: a) write appropriate values for data, parity and stop bits. b) write appropriate baud rate value to the uxbrg register. c) set up transmit and receive interrupt enable and priority bits. 2. enable the uart. 3. set the utxen bit (causes a transmit interrupt). 4. write data byte to uxtxreg word. the value will be immediately transferred to the transmit shift register (tsr), and the serial bit stream will start shifting out with next rising edge of the baud clock. 5. alternately, the data byte may be transferred while utxen = 0 , and then the user may set utxen. this will cause the serial bit stream to begin immediately because the baud clock will start from a cleared state. 6. a transmit interrupt will be generated as per interrupt control bit, utxisel<1:0>. example 19-2: example 8-bit data mode 19.4 transmitting in 9-bit data mode 1. set up the uart (as described in section 19.3). 2. enable the uart. 3. set the utxen bit (causes a transmit interrupt). 4. write uxtxreg as a 16-bit value only. 5. a write to uxtxreg triggers the transfer of the 9-bit data to the tsr. serial bit stream will start shifting out with the first rising edge of the baud clock. 6. a transmit interrupt will be generated as per the setting of control bit, utxisel<1:0>. example 19-3: example 9-bit data mode /* the following code example demonstrates configuring uart1 for 8-bit data transmit mode. */ u1brg = #baudrate; // set uart baud rate. u1modeset= 0x8000; // enable uart for 8-bit data, no parity, and 1 stop bit u1staset= 0x1400; // enable transmitter and receiver /* the following code example demonstrates configuring uart1 for 9-bit data transmit mode. */ u1brg = #baudrate; // set uart baud rate. u1modeset= 0x8006; // enable uart for 8-bit data, no parity, and 1 stop bit u1staset= 0x1211420; // enable address detect, set address = 0x21, enable transmitter and receiver
pic32mx3xx/4xx ds61143e-page 436 preliminary ? 2008 microchip technology inc. 19.5 auto-baud support the uart will begin an automatic baud rate measure- ment sequence whenever a start bit is received when the auto-baud rate detect is enabled (abaud = 1 ). this feature is active only while the auto-wake-up is disabled (wake = 0 ). in addition, lpback must equal ? 0 ? for the auto-baud operation. following the start bit, the auto-baud expects to receive an ascii ?u? (0x55) in order to calculate the proper bit rate. on the 5th uxrx pin rising edge, an accumulated brg counter value totaling the proper brg period is transferred to the uxbrg register. the abaud bit is automatically cleared. 19.6 break and sync transmit sequence the following sequence is performed to send a mes- sage frame header that is composed of a break char- acter, followed by an auto-baud sync byte. this sequence is typical of a lin bus master: 1. configure the uart for the desired mode. 2. set utxen and utxbrk to set up the break character. 3. load the uxtxreg with a dummy character to initiate transmission (value is ignored). 4. write ?0x55? to uxtxreg to load the sync character into the transmit fifo. after the break has been sent, the utxbrk bit is reset by hardware. the sync character now transmits. 19.7 receiving in 8-bit or 9-bit data mode 1. set up the uart (as described in section 19.3). 2. enable the uart. 3. a receive interrupt will be generated when one or more data characters have been received as per interrupt control bit, urxisel<1:0>. 4. read the oerr bit to determine if an overrun error has occurred. the oerr bit must be reset in software. 5. read uxrxreg. the act of reading the uxrxreg character will move the next character to the top of the receive fifo, including a new set of perr and ferr values. 19.8 operation of uxcts and uxrts control pins uartx clear to send (uxcts ) and request to send (uxrts ) are the two hardware controlled pins that are associated with the uart module. these two pins allow the uart to operate in simplex and flow control mode. they are implemented to control the transmis- sion and reception between the data terminal equipment (dte). the uen<1:0> bits in the uxmode register configure these pins. 19.9 infrared support the uart module provides two types of infrared uart support: ? irda clock output to support external irda encoder and decoder device (legacy module support) ? full implementation of the irda encoder and decoder 19.10 external irda support ? irda clock output to support external irda encoder and decoder devices, the bclkx pin (same as the uxrts pin) can be configured to generate the 16x baud clock. with uen<1:0> = 11 , the bclkx pin will output the 16x baud clock (if the uart module is enabled). it can be used to support the irda codec chip. 19.11 built-in irda encoder and decoder the uart has full implementation of the irda encoder and decoder as part of the uart module. the built-in irda encoder and decoder functionality is enabled using the iren bit (uxmode<12>). when enabled (iren = 1 ), the receive pin (uxrx) acts as the input from the infrared receiver. the transmit pin (uxtx) acts as the output to the infrared transmitter.
? 2008 microchip technology inc. preliminary ds61143e-page 437 pic32mx3xx/4xx 19.12 uart interrupts the uart device has the ability to generate interrupts, reflecting the events that occur during data communi- cation. the following types of interrupts can be generated: ? receiver-data-available interrupts, signalled by u1rxif (ifs0<27>), u2rxif (ifs1<9>). this event occurs when there is new data assembled in the uxrxbuf receive buffer. ? transmitter-buffer-empty interrupts, signalled by u1txif (ifs0<28>), u2txif (ifs1<10>). this event occurs when there is space available in the uxtxbuf transmit buffer and new data can be written. ? receiver-buffer-overflow interrupt, signalled by u1eif (ifs0<26>), u2eif (ifs1<8>). this event occurs when there is an overflow condition for the uxrxbuf receive buffer, i.e., new receive data assembled but the previous one not read. a uart device is enabled as a source of interrupts via the respective uart interrupt enable bits: ? u1rxie (iec0<27>) and u2rxie (iec1<9>) ? u1txie (iec0<28>) and u2txie (iec1<10>) ? u1eie (iec0<26>) and u2eie (iec1<8>) the interrupt priority level bits and interrupt subpriority level bits must be also be configured: ? u1ip (ipc6<4:2>), u1is (ipc6<1:0>) ? u2ip (ipc8<4:2>), u2is (ipc8<1:0>). in addition to enabling the uart interrupts, an interrupt service routine (isr) is required. below is a partial code example of an isr. example 19-4: uart initialization with interrupts enable example 19-5: uart1 isr note: it is the user?s responsibility to clear the corresponding interrupt flag bit before returning from an isr. /* the following code example illustrates a uart1 interrupt configuration. when the uart1 interrupt is generated, the cpu will jump to the vector assigned to uart1 interrupt. */ iec0clr=0x1c000000; // disable all uart1 interrupts ifs0clr=0x1c000000; // clear any existing event ipc6clr=0x0000001f; // clear the priority ipc6set=0x000d; // set ipl=3, subpriority 1 iec0set=0x1c000000; // enable rx, tx and error interrupts u1brg = #baudrate; // set uart baud rate. u1modeset= 0x8000; // enable uart for 8-bit data, no parity, and 1 stop bit u1staset= 0x1400; // enable transmitter and receiver /* the following code example demonstrates a simple interrupt service routine for uart1 interrupts. the user?s code at this vector should perform any application specific operations and must clear the uart1 interrupt flags before exiting. */ void__isr(_uart_1_vector, ipl4)uart1_inthandler(void) { ... perform application specific operations in response to the interrupt ifs0clr = 0x1c000000; // be sure to clear the uart1 interrupt flags // before exiting the service routine. data = u1rxreg; // read data from the uart hardware buffer }
pic32mx3xx/4xx ds61143e-page 438 preliminary ? 2008 microchip technology inc. 19.13 i/o pin control the uart module shares pins with port input/output control and, in some cases, with other modules. to configure a pin for use by the uart, any modules shar- ing the pin must be disabled. after configuring the uart, the corresponding i/o pins must be configured using the tris bit to be an input or output as is required by the uart. table 19-5: pins associated with a uart pin name module control (2) controlling bit field required tris bit setting pin type (1) description u1tx on utxen (3) , uen (2) output d, o uart1 transmit pin u2rx on urxen (3) , uen (2) input d, i uart1 receive pin u1cts on uen (2) input d, i uart1 clear to send (cts) duplex mode u1rts on rtsmd (2) , uen (2) output d, o uart1 ready to send (rts) duplex mode bclk1 on iren (2) output d, o uart1 irda baud clock output u2tx on utxen (3) , uen (2) output d, o uart2 transmit pin u2rx on urxen (3) , uen (2) input d, i uart2 receive pin u2cts on uen (2) input d, i uart2 clear to send (cts) duplex mode u2rts on rtsmd (2) , uen (2) output d, o uart2 ready to send (rts) duplex mode bclk2 on iren (2) output d, o uart2 irda baud clock output legend: st = schmitt trigger input with cmos levels i = input o = output a = analog d = digital note 1: all pins are subject to the device pin priority control. 2: bits are contained in the uxmode register. 3: bits are contained in the uxsta register.
? 2008 microchip technology inc. preliminary ds61143e-page 439 pic32mx3xx/4xx 20.0 parallel master port the parallel master port (pmp) is a parallel 8-bit/16-bit input/output module specifically designed to communicate with a wide variety of parallel devices, such as communications peripherals, lcds, external memory devices, and microcontrollers. because the interface to parallel peripherals varies significantly, the pmp module is highly configurable. key features of the pmp module include: ? 8-bit,16-bit interface ? up to 16 programmable address lines ? up to two chip select lines ? programmable strobe options - individual read and write strobes, or - read/write strobe with enable strobe ? address auto-increment/auto-decrement ? programmable address/data multiplexing ? programmable polarity on control signals ? parallel slave port support - legacy addressable - address support - 4-byte deep auto-incrementing buffer ? programmable wait states ? operate during cpu sleep and idle modes ? fast bit manipulation using clr, set and inv registers ? freeze option for in-circuit debugging figure 20-1: pmp module pinout and connections to external devices note: this data sheet summarizes the features of the pic32mx3xx/4xx family of devices. it is not intended to be a comprehensive refer- ence source. refer to the ?pic32mx family reference manual? (ds61132) for a detailed description of this peripheral. note: on 64-pin devices, data pins pmd<15:8> are not available. pma0 pma14 pma15 pmrd pmwr pmenb pmrd/pmwr pmcs1 pma1 pma<13:2> pmall pmalh pmcs2 flash address bus data bus control lines pic32mx3xx/4xx lcd fifo microcontroller 16/8-bit data (with or without multiplexed addressing) up to 16-bit address parallel buffer pmd<15:8> (1) pmd<7:0> master port note 1: on 64-pin devices, data pins pmd<15:8> are not available in 16-bit master modes eeprom sram
pic32mx3xx/4xx ds61143e-page 440 preliminary ? 2008 microchip technology inc. 20.1 pmp registers table 20-1: pmp sfr summary virtual address name bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 bf80_7000 pmcon 31:24 ? ? ? ? ? ? ? ? 23:16 ? ? ? ? ? ? ? ? 15:8 on frz sidl adrmux<1:0> pmpttl ptwren ptrden 7:0 csf<1:0> alp cs2p cs1p ? wrsp rdsp bf80_7004 pmconclr 31:0 write clears selected bits in pmcon, read yields undefined value bf80_7008 pmconset 31:0 write sets selected bits in pmcon, read yields undefined value bf80_700c pmconinv 31:0 write inverts selected bits in pmcon, read yields undefined value bf80_7010 pmmode 31:24 ? ? ? ? ? ? ? ? 23:16 ? ? ? ? ? ? ? ? 15:8 busy irqm<1:0> incm<1:0> mode16 mode<1:0> 7:0 waitb<1:0> waitm<3:0> waite<1:0> bf80_7014 pmmodeclr 31:0 write clears selected bits in pmmode, read yields undefined value bf80_7018 pmmodeset 31:0 write sets selected bits in pmmode, read yields undefined value bf80_701c pmmodeinv 31:0 write inverts selected bits in pmmode, read yields undefined value bf80_7020 pmaddr 31:24 ? ? ? ? ? ? ? ? 23:16 ? ? ? ? ? ? ? ? 15:8 cs2en/a15 cs1en/a14 addr<13:8> 7:0 addr<7:0> bf80_7024 pmaddrclr 31:0 write clears selected bits in prx, read yields undefined value bf80_7028 pmaddrset 31:0 write sets selected bits in prx, read yields undefined value bf80_702c pmaddrinv 31:0 write inverts selected bits in prx, read yields undefined value bf80_7030 pmdout 31:24 dataout<31:24> 23:16 dataout<23:16> 15:8 dataout<15:8> 7:0 dataout<7:0> bf80_7034 pmdoutclr 31:0 write clears selected bits in pmdout, read yields undefined value bf80_7038 pmdoutset 31:0 write sets selected bits in pmdout, read yields undefined value bf80_703c pmdoutinv 31:0 write inverts selected bits in pmdout, read yields undefined value bf80_7040 pmdin 31:24 datain<31:24> 23:16 datain<23:16> 15:8 datain<15:8> 7:0 datain<7:0> bf80_7044 pmdinclr 31:0 write clears selected bits in pmdin, read yields undefined value bf80_7048 pmdinset 31:0 write sets selected bits in pmdin, read yields undefined value bf80_704c pmdininv 31:0 write inverts selected bits in pmdin, read yields undefined value bf80_7050 pmaen 31:24 ? ? ? ? ? ? ? ? 23:16 ? ? ? ? ? ? ? ? 15:8 pten<15:8> 7:0 pten<7:0> bf80_7054 pmaenclr 31:0 write clears selected bits in pmaen, read yields undefined value bf80_7058 pmaenset 31:0 write sets selected bits in pmaen, read yields undefined value bf80_705c pmaeninv 31:0 write inverts selected bits in pmaen, read yields undefined value bf80_7060 pmstat 31:24 ? ? ? ? ? ? ? ? 23:16 ? ? ? ? ? ? ? ? 15:8 ibf ibov ? ? ib3f ib2f ib1f ib0f 7:0 obe obuf ? ? ob3e ob2e ob1e ob0e bf80_7064 pmstatclr 31:0 write clears selected bits in pmstat, read yields undefined value bf80_7068 pmstatset 31:0 write sets selected bits in pmstat, read yields undefined value bf80_706c pmstatinv 31:0 write inverts selected bits in pmstat, read yields undefined value
? 2008 microchip technology inc. preliminary ds61143e-page 441 pic32mx3xx/4xx table 20-2: pmp interrupt register summary virtual address name bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 bf88_1070 iec1 7:0 spi2rxie spi2txie spi2eie cmp2ie cmp1ie pmpie ad1ie i2c1mie bf88_1040 ifs1 7:0 spi2rxif spi2txif spi2eif cmp2if cmp1if pmpif ad1if i2c1mif bf88_1100 ipc7 7:0 ? ? ? pmpip<2:0> pmpis<1:0> note: this summary table contains partial register definitions that only pertain to the pmp peripheral. refer to the ? pic32mx family reference manual ? (ds61132) for a detailed description of these registers.
pic32mx3xx/4xx ds61143e-page 442 preliminary ? 2008 microchip technology inc. register 20-1: pmcon: parall el port control register r-x r-x r-x r-x r-x r-x r-x r-x ? ? ? ? ? ? ? ? bit 31 bit 24 r-x r-x r-x r-x r-x r-x r-x r-x ? ? ? ? ? ? ? ? bit 23 bit 16 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r-x r/w-0 r/w-0 on frz sidl adrmux1 adrmux0 pmpttl ptwren ptrden bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r-x r/w-0 r/w-0 csf1 (1) csf0 (1) alp (1) cs2p (1) cs1p (1) ? wrsp rdsp bit 7 bit 0 legend: r = readable bit w = writable bit p = programmable bit r = reserved bit u = unimplemented bit -n = bit value at por: (?0?, ?1?, x = unknown) bit 31-16 reserved: write ? 0 ?; ignore read bit 15 on: parallel master port enable bit 1 = pmp enabled 0 = pmp disabled, no off-chip access performed bit 14 frz: freeze in debug exception mode bit 1 = freeze operation when cpu is in debug exception mode 0 = continue operation when cpu is in debug exception mode note: frz is writable in debug exception mode only, it is forced to ? 0 ? in normal mode. bit 13 sidl: stop in idle mode 1 = discontinue module operation when device enters idle mode 0 = continue module operation in idle mode bit 12-11 adrmux1:adrmux0: address/data multiplexing selection bits 11 = all 16 bits of address are multiplexed on pmd<15:0> pins 10 = all 16 bits of address are multiplexed on pmd<7:0> pins 01 = lower 8 bits of address are multiplexed on pmd<7:0> pins, upper 8 bits are on pma<15:8> 00 = address and data appear on separate pins bit 10 pmpttl: pmp module ttl input buffer select bit 1 = pmp module uses ttl input buffers 0 = pmp module uses schmitt input buffers bit 9 ptwren: write enable strobe port enable bit 1 = pmwr/pmenb port enabled 0 = pmwr/pmenb port disabled bit 8 ptrden: read/write strobe port enable bit 1 = pmrd/pmwr port enabled 0 = pmrd/pmwr port disabled note 1: these bits have no effect when their corresponding pins are used as address lines
? 2008 microchip technology inc. preliminary ds61143e-page 443 pic32mx3xx/4xx bit 7-6 csf<1:0>: chip select function bits (1) 11 = reserved 10 = pmcs2 and pmcs1 function as chip select 01 = pmcs2 functions as chip select, pmcs1 functions as address bit 14 00 = pmcs2 and pmcs1 function as address bits 15 and 14 bit 5 alp: address latch polarity bit (1) 1 = active-high (pmall and pmalh) 0 = active-low (pmall and pmalh ) bit 4 cs2p: chip select 1 polarity bit (1) 1 = active-high (pmcs2) 0 = active-low (pmcs2 ) bit 3 cs1p: chip select 0 polarity bit (1) 1 = active-high (pmcs1/pmcs) 0 = active-low (pmcs1 /pmcs ) bit 2 reserved: write ? 0 ?; ignore read bit 1 wrsp: write strobe polarity bit for slave modes and master mode 2 (pmmode<9:8> = 00 , 01 , 10 ): 1 = write strobe active-high (pmwr) 0 = write strobe active-low (pmwr ) for master mode 1 (pmmode<9:8> = 11 ): 1 = enable strobe active-high (pmenb) 0 = enable strobe active-low (pmenb ) bit 0 rdsp: read strobe polarity bit for slave modes and master mode 2 (pmmode<9:8> = 00 , 01 , 10 ): 1 = read strobe active-high (pmrd) 0 = read strobe active-low (pmrd ) for master mode 1 (pmmode<9:8> = 11 ): 1 = read/write strobe active-high (pmrd/pmwr ) 0 = read/write strobe active-low (pmrd /pmwr) register 20-1: pmcon: parallel po rt control register (continued) note 1: these bits have no effect when their corresponding pins are used as address lines
pic32mx3xx/4xx ds61143e-page 444 preliminary ? 2008 microchip technology inc. register 20-2: pmmode: parallel port mode register r-x r-x r-x r-x r-x r-x r-x r-x ? ? ? ? ? ? ? ? bit 31 bit 24 r-x r-x r-x r-x r-x r-x r-x r-x ? ? ? ? ? ? ? ? bit 23 bit 16 r-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 busy irqm<1:0> incm<1:0> mode16 mode<1:0> bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 waitb1<1:0> (1) waitm<3:0> waite1<1:0> (1) bit 7 bit 0 legend: r = readable bit w = writable bit p = programmable bit r = reserved bit u = unimplemented bit -n = bit value at por: (?0?, ?1?, x = unknown) bit 31-16 reserved: write ? 0 ?; ignore read bit 15 busy: busy bit (master modes only) 1 = port is busy 0 = port is not busy bit 14-13 irqm<1:0>: interrupt request mode bits 11 = reserved ? do not use 10 = interrupt generated when read buffer 3 is read or write buffer 3 is written (buffered psp mode) or on a read or write operation when pma<1:0> = 11 (addressable psp mode only) 01 = interrupt generated at the end of the read/write cycle 00 = no interrupt generated bit 12-11 incm<1:0>: increment mode bits 11 = slave mode read and write buffers auto-increment (mode<1:0> = 00 only) 10 = decrement addr<15:0> by 1 every read/write cycle (2,5) 01 = increment addr<15:0> by 1 every read/write cycle (2,5) 00 = no increment or decrement of address bit 10 mode16: 8/16-bit mode bit 1 = 16-bit mode: a read or write to the data register invokes a single 16-bit transfer (4) 0 = 8-bit mode: a read or write to the data register invokes a single 8-bit transfer note 1: whenever waitm3:waitm0 = 0000 , waitb and waite bits are ignored and forced to 1 t pbclk cycle for a write operation; waitb = 1 t pbclk cycle, waite = 0 t pbclk cycles for a read operation. 2: when addr15 and addr14 are used as cs2 and cs1, or addr15 is used as cs2, these bits are not subject to auto-increment/decrement. 3: in master mode 1 or master mode 2, data pins pmd<15:0> are active when mode16 = 1 ; data pins pmd<7:0> are active when mode16 = 0 . 4: on 64-pin devices, data pins pmd<15:8> are not available. 5: the pmaddr register is always incremented/decremented by 1, regardless of the transfer data width.
? 2008 microchip technology inc. preliminary ds61143e-page 445 pic32mx3xx/4xx bit 9-8 mode1:mode0: parallel port mode select bits 11 = master mode 1 (pmcsx, pmrd/pmwr , pmenb, pma, pmd<15:0>) (3,4) 10 = master mode 2 (pmcsx, pmrd, pmwr, pma, pmd<15:0>) (3,4) 01 = addressable slave mode, control signals (pmrd , pmwr , pmcs , pmd<7:0>, pma<1:0>) 00 = legacy parallel slave port, control signals (pmrd , pmwr , pmcs , pmd<7:0>) bit 7-6 waitb1:waitb0: data setup to read/write strobe wait states bits (1) 11 = data wait of 4 t pb ; multiplexed address phase of 4 t pb 10 = data wait of 3 t pb ; multiplexed address phase of 3 t pb 01 = data wait of 2 t pb ; multiplexed address phase of 2 t pb 00 = data wait of 1 t pb ; multiplexed address phase of 1 t pb ( default ) bit 5-2 waitm3:waitm0: data read/write strobe wait states bits 1111 = wait of 16 t pb ... 0001 = wait of 2 t pb 0000 = wait of 1 t pb ( default ) bit 1-0 waite1:waite0: data hold after read/write strobe wait states bits (1) 11 = wait of 4 t pb 10 = wait of 3 t pb 01 = wait of 2 t pb 00 = wait of 1 t pb ( default ) for read operations: 11 = wait of 3 t pb 10 = wait of 2 t pb 01 = wait of 1 t pb 00 = wait of 0 t pb ( default ) register 20-2: pmmode: parallel po rt mode register (continued) note 1: whenever waitm3:waitm0 = 0000 , waitb and waite bits are ignored and forced to 1 t pbclk cycle for a write operation; waitb = 1 t pbclk cycle, waite = 0 t pbclk cycles for a read operation. 2: when addr15 and addr14 are used as cs2 and cs1, or addr15 is used as cs2, these bits are not subject to auto-increment/decrement. 3: in master mode 1 or master mode 2, data pins pmd<15:0> are active when mode16 = 1 ; data pins pmd<7:0> are active when mode16 = 0 . 4: on 64-pin devices, data pins pmd<15:8> are not available. 5: the pmaddr register is always incremented/decremented by 1, regardless of the transfer data width.
pic32mx3xx/4xx ds61143e-page 446 preliminary ? 2008 microchip technology inc. register 20-3: pmaddr: parallel port address register r-x r-x r-x r-x r-x r-x r-x r-x ? ? ? ? ? ? ? ? bit 31 bit 24 r-x r-x r-x r-x r-x r-x r-x r-x ? ? ? ? ? ? ? ? bit 23 bit 16 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 cs2en/a15 cs1en/a14 addr<13:8> bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 addr<7:0> bit 7 bit 0 legend: r = readable bit w = writable bit p = programmable bit r = reserved bit u = unimplemented bit -n = bit value at por: (?0?, ?1?, x = unknown) bit 31-16 reserved: write ? 0 ?; ignore read bit 15 cs2en: chip select 2 bit 1 = chip select 2 is active 0 = chip select 2 is inactive (pin functions as pma<15>) bit 14 cs1en: chip select 1 bit 1 = chip select 1 is active 0 = chip select 1 is inactive (pin functions as pma<14>) bit 13-0 addr13:addr0: destination address bits
? 2008 microchip technology inc. preliminary ds61143e-page 447 pic32mx3xx/4xx register 20-4: pmdout: parallel port dataout register r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 dataout<31:24> bit 31 bit 24 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 dataout<23:16> bit 23 bit 16 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 dataout<15:8> bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 dataout<7:0> bit 7 bit 0 legend: r = readable bit w = writable bit p = programmable bit r = reserved bit u = unimplemented bit -n = bit value at por: (?0?, ?1?, x = unknown) bit 15-0 dataout<31:0>: output data port bits for 8-bit write operations in slave modes.
pic32mx3xx/4xx ds61143e-page 448 preliminary ? 2008 microchip technology inc. register 20-5: pmdin: parallel port datain register r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 datain<31:24> bit 31 bit 24 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 datain<23:16> bit 23 bit 16 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 datain<15:8> bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 datain<7:0> bit 7 bit 0 legend: r = readable bit w = writable bit p = programmable bit r = reserved bit u = unimplemented bit -n = bit value at por: (?0?, ?1?, x = unknown) bit 31-0 datain<31:0>: input and output data port bits for 8-bit or 16-bit read/write operations in master modes; input data port bits for read operations in slave modes.
? 2008 microchip technology inc. preliminary ds61143e-page 449 pic32mx3xx/4xx register 20-6: pmaen: parallel port pin enable register r-x r-x r-x r-x r-x r-x r-x r-x ? ? ? ? ? ? ? ? bit 31 bit 24 r-x r-x r-x r-x r-x r-x r-x r-x ? ? ? ? ? ? ? ? bit 23 bit 16 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 pten<15:8> bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 pten<7:0> bit 7 bit 0 legend: r = readable bit w = writable bit p = programmable bit r = reserved bit u = unimplemented bit -n = bit value at por: (?0?, ?1?, x = unknown) bit 31-16 reserved: write ? 0 ?; ignore read bit 15-14 pten15:pten14: pmcsx strobe enable bits 1 = pma15 and pma14 function as either pma<15:14> or pmcs2 and pmcs1 (1) 0 = pma15 and pma14 function as port i/o bit 13-2 pten13:pten2: pmp address port enable bits 1 = pma<13:2> function as pmp address lines 0 = pma<13:2> function as port i/o bit 1-0 pten1:pten0: pmalh/pmall strobe enable bits 1 = pma1 and pma0 function as either pma<1:0> or pmalh and pmall (2) 0 = pma1 and pma0 pads functions as port i/o note 1: the use of these pins as pma15/pma14 or cs2/cs1 are selected by bits csf<1:0> in the pmcon register. 2: the use of these pins as pma1/pma0 or pmalh/pmall depends on the address/data multiplex mode selected by bits, adrmux<1:0>, in the pmcon register.
pic32mx3xx/4xx ds61143e-page 450 preliminary ? 2008 microchip technology inc. register 20-7: pmstat: parallel port st atus register (slave mode only) r-x r-x r-x r-x r-x r-x r-x r-x ? ? ? ? ? ? ? ? bit 31 bit 24 r-x r-x r-x r-x r-x r-x r-x r-x ? ? ? ? ? ? ? ? bit 23 bit 16 r-0 r/w-0 r-x r-x r-0 r-0 r-0 r-0 ibf ibov ? ? ib3f ib2f ib1f ib0f bit 15 bit 8 r-1 r/w-0 r-x r-x r-1 r-1 r-1 r-1 obe obuf ? ? ob3e ob2e ob1e ob0e bit 7 bit 0 legend: r = readable bit w = writable bit p = programmable bit r = reserved bit u = unimplemented bit -n = bit value at por: (?0?, ?1?, x = unknown) bit 31-16 reserved: write ? 0 ?; ignore read bit 15 ibf: input buffer full status bit 1 = all writable input buffer registers are full 0 = some or all of the writable input buffer registers are empty bit 14 ibov: input buffer overflow status bit 1 = a write attempt to a full input byte register occurred (must be cleared in software) 0 = no overflow occurred bit 13-12 reserved: write ? 0 ?; ignore read bit 11-8 ib3f:ib0f: input buffer n status full bit 1 = input buffer contains data that has not been read (reading buffer will clear this bit) 0 = input buffer does not contain any unread data bit 7 obe: output buffer empty status bit 1 = all readable output buffer registers are empty 0 = some or all of the readable output buffer registers are full bit 6 obuf: output buffer underflow status bit 1 = a read occurred from an empty output byte register (must be cleared in software) 0 = no underflow occurred bit 5-4 reserved: write ? 0 ?; ignore read bit 3-0 ob3e:ob0e: output buffer n status empty bit 1 = output buffer is empty (writing data to the buffer will clear this bit) 0 = output buffer contains data that has not been transmitted
? 2008 microchip technology inc. preliminary ds61143e-page 451 pic32mx3xx/4xx 20.2 modes of operation 20.2.1 considerations for pmp module ? the pmp module is enabled and ready when the on bit (pmcon<15>) is set = 1 , therefore it is recommended to configure the desired operating mode prior to enabling the module. ? the pmp module is disabled and powered off when the on bit (pmpcon<15>) = 0 , thus pro- viding maximum power savings. ? it is recommended to wait for any pending read or write operation to be completed before enabling/disabling or re-configuring the module 20.2.2 considerations for master modes ? setting address bits a15 and a14 = 1 when pmcs2 and pmcs1 are enabled as chip selects will cause both pmcs2 and pmcs1 to be active during a read or write operation. this may enable two devices simultaneously and should be avoided. ? it is always recommended to poll the pmp?s busy bit prior to any read or write operation to ensure the prior pmp operation has completed. the pmp module offers two master modes of operation featuring 16-bit or 8-bit data (default), up to 16 bits of address, and all control signals to operate a variety of external parallel devices such as memory devices, peripherals, and slave microcontrollers. an example using master mode 2 is shown in figure 20-2. figure 20-2: example: pmp master mode 2, partial multiplexed interface 20.2.3 master mode selection the two master modes are selected using mode<1:0> bits (pmcon<9:8>). master mode 1 is selected by con- figuring mode<1:0> bits = 11 ; master mode 2 is selected by configuring mode<1:0> bits = 10 . 20.2.4 8, 16-bit data modes the pmp in master mode supports data widths 8 and 16 bits wide. by default, the data width is 8-bit, mode16 (pmmode<10>) bit = 0 . to select 16-bit data width, set mode16 = 1 . when configured in 8-bit data mode, the upper 8 bits of the data bus, pmd<15:8>, are not controlled by the pmp module and are available as general purpose i/o pins. 20.2.5 chip selects two chip select lines, pmcs1 and pmcs2, are avail- able for the master modes. the two chip select lines are multiplexed with the most significant bits of the address bus a14 and a15. if a pin is configured as a chip select, it is not included in any pma<15:0> address auto-increment/decrement. it is possible to enable both pmcs2 and pmcs1 as chip selects, or enable only pmcs2 as a chip select, allowing pmcs1 to function strictly as address line a14. it is not possible to enable only pmcs1. the chip select signals are configured using the chip select function bits csf<1:0> (pmcon <7:6>). refer to section 20.2.16 ?addressing consider- ations? for information regarding chip select address mapping. 20.2.6 port pin control the pmaen register controls the functionality of the address pins pma<15:0>. setting any pmaen bit = 1 configures the corresponding pma pin as an address line. those bits set = 0 remain as general purpose i/o pins. refer to section 20.5 ?i/o pin control? regarding i/o pin configuration. pmrd pmwr pmd<7:0> pma14/pmcs1 pma<13:8> pma0/pmall pma15/pmcs2 address bus multiplexed data and address bus data bus control lines pmd<15:8> adrmux<1:0> = 01 pic32mx3xx/4xx note: on 64-pin devices, data pins pmd<15:8> are not available. table 20-3: chip select control csf<1:0> function 00 pmcs2 = a15, pmcs1 = a14 01 pmcs2 = enabled, pmcs1 = a14 10 pmcs2, pmcs1 = enabled
pic32mx3xx/4xx ds61143e-page 452 preliminary ? 2008 microchip technology inc. 20.2.7 read/write control the pmp module supports two distinct read/write sig- naling methods. in master mode 1, read and write strobe are combined into a single control line, pmrd/pmwr ; a second control line, pmenb, deter- mines when a read or write action is to be taken. in master mode 2, read and write strobes (pmrd and pmwr) are supplied on separate pins. to enable the pmrd/pmwr and pmwr/pmenb pins, set ptrden bit (pmcon<8>) and ptwren bit (pmcon<9>) = 1 . 20.2.8 control line polarity all control signals (pmrd, pmwr, pmall, pmalh, pmcs2 and pmcs1) can be individually configured for either positive (active-high) or negative (active-low) polarity. the polarity for each control line is controlled by separate bits in the pmcon register. note that the polarity of control signals that share the same output pin (for example, pmwr and pmenb) are controlled by the same bit; the configuration depends on which master port mode is being used. 20.2.9 auto-increment/decrement while the module is operating in a master mode, the auto-address increment/decrement bits incm<1:0> (pmmode<12:11>) control the behavior of the address value that appears on the pma<15:0> address pins. the address in the pmaddr register can be made to automatically increment or decrement by 1 (regardless of the transfer data width) after each read and write operation is completed, and the busy bit goes to ? 0 ?. if the chip select signals are disabled and configured as address bits, the bits will participate in the increment and decrement operations; otherwise, the pmcs2 and pmcs1 bit values will be unaffected. 20.2.10 wait states in master modes, the user has control over the dura- tion of the read, write, and address cycles by configur- ing the module wait states. three portions of the cycle, the beginning, middle, and end are configured using the corresponding waitb, waitm, and waite bits in the pmmode register. 20.2.11 address multiplexing in either of the master modes the address bus can be multiplexed together with the data bus. there are three address multiplexing modes available; demultiplexed, partial multiplexed and full multiplexed. the address- ing multiplex mode is configured using bits adrmux<1:0> (pmcon<12:11). for detailed examples illustrating address multiplexing configurations, refer to the pmp chapter in the ? pic32mx family reference manual ? (ds61132). 20.2.12 demultiplexed mode in demultiplexed mode, address bits are presented on pins pma<15:0>. note, pma15 is not available if pmcs2 is enabled and pma14 is not available if pmcs1 is enabled. data bits are presented on pins pmd<15:0> in 16-bit data mode; pins pmd<7:0> in 8- bit data mode. demultiplexed mode is selected by configuring bits adrmux<1:0> = 00 . table 20-4: master mode pin polarity control pin pmcon control bit active-high select active-low select pmrd rdsp 10 pmwr wrsp 10 pmcs2 cs2p 10 pmcs1 cs1p 10 pmall/h alp 10 table 20-5: address auto- increment/decrement configuration incm<1:0> function 00 no increment, no decrement 01 increment every r/w cycle 10 decrement every r/w cycle table 20-6: address multiplex configurations adrmux<1:0> multiplex modes 00 demultiplexed 01 partial (uses pmd<7:0>) 10 full (uses pmd<7:0>) 11 full (uses pmd<15:0>) note: a design implementing partial or full multi- plexed address and data bus allows the unused pma address pins to be used as general purpose i/o pins. however, depending on the multiplexing mode, read and write operations will be extended by several peripheral bus clock cycles, t pbclk .
? 2008 microchip technology inc. preliminary ds61143e-page 453 pic32mx3xx/4xx figure 20-3: demultiplexed addressing 20.2.13 partial multiplexed mode in partial multiplexed mode, the lower eight address bits are multiplexed with data pins pmd<7:0>. the upper eight address bits are unaffected and are presented on pma<15:8>. note, pma15 is not available if pmcs2 is enabled and pma14 is not available if pmcs1 is enabled. the pma<0> pin is used as an address latch, and presents the address latch low enable strobe (pmall). pma<7:1> are available as general purpose i/o pins. partial multiplexed mode is selected by configuring bits adrmux<1:0> = 00 . figure 20-4: partial multiplexed addressing 20.2.14 full multiplexed mode (8-bit data pins) in 8-bit full multiplexed mode, the entire 16 bits of the address are multiplexed with the data pins on pmd<7:0>. the pma<0> and pma<1> pins are used to present address latch low enable (pmall) and address latch high enable pmalh strobes, respectively. pins pma<13:2> are not used as address pins and can be used as general purpose i/o pins. in the event address bits pma15 or pma14 are configured as chip selects, the corresponding address bits pmaddr<15> and pmaddr<14> are automatically forced = 0 . full 8-bit multiplexed mode is selected by configuring bits adrmux<1:0> (pmcon<12:11>) = 10 . figure 20-5: full multiplexed addressing (8-bit bus) 20.2.15 full multiplexed mode (16-bit data pins) in full 16-bit multiplexed mode, the entire 16 bits of the address are multiplexed with the data pins on pmd<15:0>. pins pma<0> and pma<1> provide address latch low enable pmall and address latch high enable pmalh strobes, respectively, and at the same time. pins pma<13:2> are not used as address pins and can be used as general purpose i/o pins. in the event address bits pma15 or pma14 are config- ured as chip selects, the corresponding address bits pmaddr<15> and pmaddr<14> are automatically forced = 0 . full 16-bit multiplexed mode is selected by configuring bits: adrmux<1:0>(pmcon<12:11>) = 11 pmrd pmwr pmd<7:0> pma14/pmcs1 pma<13:0> pma15/pmcs2 address bus data bus control lines pmd<15:8> (1) note 1: pma15 is not available if pmcs2 is enabled. pma14 is not available if pmcs1 is enabled. adrmux<1:0> = 00 pic32mx3xx/4xx pmrd pmwr pmd<7:0> pma14/pmcs1 pma<13:8> pma0 / pmall pma15/pmcs2 address bus multiplexed address/data bus data bus control lines pmd<15:8> (1) note 1: pma15 is not available if pmcs2 is enabled. pma14 is not available if pmcs1 is enabled. adrmux<1:0> = 01 pic32mx3xx/4xx pmrd pmwr pmd<7:0> pma14/pmcs1 pma1 / pmalh pma15/pmcs2 pic32mx3xx/4xx pma0 / pmall adrmux<1:0> = 10 (1) fully multiplexed address/data bus control lines note 1: pma15 is not available if pmcs2 is enabled. pma14 is not available if pmcs1 is enabled.
pic32mx3xx/4xx ds61143e-page 454 preliminary ? 2008 microchip technology inc. figure 20-6: full multiplexed addressing (16-bit bus) 20.2.16 addressing considerations pmcs2 and pmcs1 chip select pins share functional- ity with address lines a15 and a14. it is possible to enable both pmcs2 and pmcs1 as chip selects, or enable only pmcs2 as a chip select, allowing pmcs1 to function strictly as address line a14. it is not possible to enable only pmcs1. when configured as chip selects, a 1 must be written into bit position 15 or 14 of the pmaddr register in order for pmcs2 or pmcs1 to become active during a read or write operation. failing to write a 1 to pmcs2 or pmcs1 does not prevent address pins pma<13:0> from being active as the specified address appears, however, no chip select signal will be active. disabling one or both chip selects pmcs2 and pmcs1 makes these pins available as address lines a15 and a14. in full multiplexed mode, address bits pmaddr<15:0> are multiplexed with the data bus and in the event address bits pma15 or pma14 are config- ured as chip selects, the corresponding pmaddr<15:14> address bits are automatically forced = 0 . disabling one or both pmcs2 and pmcs1 makes these bits available as address bits pmaddr<15:14>. in any of the master mode multiplexing schemes, dis- abling both chip select pins pmcs2 and pmcs1 requires the user to provide chip select line control through some other i/o pin under software control. see figure 20-7. figure 20-7: pmp chip select address mapping (demultiplexed and partial multiplexed modes) (1) pmrd pmwr pma1 / pmalh pma15/pmcs2 pma0 / pmall pmd<7:0> pmd<15:8> pma14/pmcs1 adrmux<1:0> = 11 fully multiplexed address/data bus control lines note 1: pma15 is not available if pmcs2 is enabled. pma14 is not available if pmcs1 is enabled. pic32mx3xx/4xx note: when using auto-increment address mode, pmcs2 and pmcs1 do not partic- ipate and must be controlled by the user?s software by writing to ? 1 ? to pmaddr<15:14> explicitly. device 2 selected pmcs2 = 1 device 1 selected pmcs1 = 1 no device selected both devices selected (invalid) 0x0000 0x4000 0x8000 0xffff 0xc000 0 0 0 0 1 1 11 pmcs2, cs1 2 - 16k address ranges 2 - chip selects device selected pmcs2 = 1 no device selected 0 pmcs2, a14 1 - 32k address range 1 - chip select 1 1 0 0 0 1 1 device selected iopin = 1 a15, a14, io-pin 1 1 - 64k address range io-pin = software controlled cs 0 1 1 0 0 0 1 1 1 1 1
? 2008 microchip technology inc. preliminary ds61143e-page 455 pic32mx3xx/4xx 20.3 master mode timing a pmp master mode cycle time is defined as the num- ber of pbclk cycles required by the pmp to perform a read or write operation and is dependent on pbclk clock speed, pmp address/data multiplexing modes and the number of pmp wait states, if any. refer to the pic32mx family reference manual, pmp chapter, for various timing diagrams. for specific setup and hold timing characteristics, refer to section 30.2 ?ac char- acteristics and timing parameters? in this data sheet. a pmp master mode read or write cycle is initiated by accessing (reading or writing) the pmdin register. sec- tion table 20-7: ?pmp read/write cycle times? below provides a summary of read and write pmp cycle times for each multiplex configuration. the actual data rate of the pmp (the rate which user?s code can perform a sequence of read or write opera- tions) will be highly dependent on several factors: ? a user?s application code content ? code optimization level ? internal bus activity ? other factors relating to the instruction execution speed. 20.3.1 master port configuration the master mode configuration is determined primarily by the interface requirements to the external device. address multiplexing, control signal polarity, data width and wait states typically dictate the specific configura- tion of the pmp master port. the following illustrates example settings for master mode 2 operation: ? select master mode 2 - mode<1:0> (pmmode<9:8>) = 10 . ? select 16-bit data mode - mode16 (pmmode<10>) = 1 . ? select partial multiplexed addressing - adrmux<1:0> (pmcon<12:11>) = 01 . ? select auto-address increment - incm<1:0> (pmmode<12:11>) = 01 . ? enable interrupt request mode - irqm<1:0> (pmmode<14:13>) = 01 . ? enable pmrd strobe - ptrden (pmcon<8>) = 1 . ? enable pmwr strobe - ptwren (pmcon<9>) = 1 . ? enable pmcs2 and pmcs1 chip selects - csf (pmcon<7:6>) = 10 . ? select pmrd ?active-low? pin polarity - rdsp (pmcon<0>) = 0 . ? select pmwr ?active-low? pin polarity - wrsp (pmcon<1>) = 0 . ? select pmcs2, pmcs1 ?active-low? pin polarity - cs2p (pmcon<4>) = 0 and cs1p (pmcon<3>) = 0 . ? select 1 wait cycle for data setup - waitb<1:0>(pmmode<7:6>) = 00 . ? select 2 wait cycles to extend pmrd/pmwr - waitm<3:0>(pmmode<5:2>) = 01 . ? select 1 wait cycle for data hold - waitb<1:0>(pmmode<1:0>) = 00 . ? enable upper 8 pma<15:8> address pins - pmaen<15:8> = 1 (lower 8 can be used as general purpose i/o). note: during any master mode read or write operation, the busy flag will always de- assert 1 peripheral bus clock cycle (t pbclk ) , before the end of the operation, including wait states. the user?s applica- tion must check the status of the busy flag to ensure it is = 0 before initiating the next pmp operation. table 20-7: pmp read/write cycle times address/data multiplex configuration adrmux bit settings pmp cycle time (pbclk cycles) read write demultiplexed 00 23 partial multiplex 01 56 full multiplexed (8-bit data) 10 89 full multiplexed (16-bit data) 11 56 note: wait states are not enabled
pic32mx3xx/4xx ds61143e-page 456 preliminary ? 2008 microchip technology inc. 20.3.2 master port initialization the master mode initialization properly prepares the pmp port for communicating with an external device. the following steps should be performed to properly configure the pmp port: 1. if interrupts are used, disable the pmp interrupt by clearing the interrupt enable bit pmpie (iec1<2>) = 0 . 2. stop and reset the pmp module by clearing the control bit on (pmcon<15>) = 0 . 3. configure the desired settings in the pmcon, pmmode and pmaen control registers. 4. if interrupts are used: a) clear interrupt flag bit pmpif (ifs1<2>) = 0 . b) configure the pmp interrupt priority bits pmpip<2:0> (ipc7<4:2>) and interrupt sub priority bits pmpis (ipc7<1:0>. c) enable pmp interrupt by setting interrupt enable bit pmpie = 1 . 5. enable the pmp master port by setting control bit on = 1 . example 20-1: parallel master port initialization 20.3.3 read operation to perform a read on the parallel bus, the user reads the pmdin register. the effect of reading the pmdin register retrieves the current value and causes the pmp to activate the chip select lines and the address bus. the read line pmrd is strobed and the new data is latched into the pmdin register, making it available for the next time the pmdin register is read. refer to the pic32mx3xx/4xx reference manual for a detailed description of the read operation and illus- trated example. iec1clr = 0x0004; //disable pmp int pmcon = 0x0bc0; //stop and configure pmmode = 0x2a04; //config pmmode reg pmaen = 0xff00; //config pmaen reg ipc7set = 0x001c; //priority level=7 ipc7set = 0x0003; //subpriority=3 //same as.. //ipc7set=0x001f ifs1clr = 0x0004; //clear pmp flag iec1set = 0x0004; //enable pmp int pmconset = 0x8000; //enable pmp pmaddr = 0x4000; //set external address pmdin = 0x1234; //write to device ... note: the read data obtained from the pmdin register is actually the read value from the previous read operation. hence, the first user read will be a dummy read to initiate the first bus read and fill the read register. also, the requested read value will not be ready until after the busy bit is observed low. therefore, in a back-to-back read operation, the data read from the register will be the same for both reads. the next read of the register will yield the new value.
? 2008 microchip technology inc. preliminary ds61143e-page 457 pic32mx3xx/4xx 20.3.4 write operation to perform a write onto the parallel port, the user writes to the pmdin register (same register used for a read operation). this causes the module to first acti- vate the chip select lines and the address bus. the write data from the pmdin register is placed onto the pmd data bus and the write line pmpwr is strobed. 20.3.5 parallel master port status in addition to the pmp interrupt, a busy bit is provided to indicate the status of the module. this bit is only used in master modes. while any read or write operation is in progress, the busy bit is set for all but the very last peripheral bus cycle of the operation. while the bit is set, any request by the user to initiate a new operation will be ignored (i.e., writing or reading the pmdin register will not initi- ate either a read nor a write). if a large number of wait-states are used, or if the pbclk clock is operating slower than the sysclk clock, it is possible for the pmp module to be in the pro- cess of completing a read or write operation when the next cpu instruction is attempting to read or write the pmp module. for this reason, it is highly recommended that the pmp?s busy bit be checked prior to any read or write operation and any user operation that modifies the pmaddr address register. see the following code example. example 20-2: polling the busy flag in most applications, the pmp?s chip select pin(s) pro- vide the chip select interface and are under the timing control of the pmp module. however, some applica- tions may require the pmp chip select pin(s) not be configured as a chip select, but as a high-order address line, such as pma<14> or pma<15>. in this situation, the application?s chip select function must be provided by an available i/o port pin under software control. in these cases, it is especially important that the user?s software poll the busy bit to ensure any read or write operation is complete before de-asserting the software controlled chip select. the following example illustrates a common technique. note: during any master mode read or write operation, the busy flag will always de- assert 1 peripheral bus clock cycle (t pbclk ) , before the end of the operation, including wait states. /*an generic c example pmp write function utilizing the busy bit. */ pmpwrite(unsigned int value) { while(pmmode & 0x8000); // pmp busy? pmdin = value; // perform write } /*an mplab c32 example pmp write function utilizing busy bit. */ pmpwrite(unsigned int value) { while(pmmodebits.busy); // pmp busy? pmdin = value; // perform write }
pic32mx3xx/4xx ds61143e-page 458 preliminary ? 2008 microchip technology inc. example 20-3: polling the busy flag an d software controlled chip select /* an generic c example pmp write function utilizing portd.rd1 as an active low chip select and the busy bit. */ pmpwrite(unsigned int value) { portdclr = 0x0002; //cs enabled while(pmmode & 0x8000); // pmp busy? pmdin = value; //perform write while(pmmode & 0x8000); //wait for pmp portdset = 0x0002; //cs disabled } /* an mplab c32 example pmp write function utilizing portd.rd1 as an active low chip select and the busy bit. */ pmpwrite(unsigned int value) { portdclr = 0x0002; //cs enabled while(pmmodebits.busy); // pmp busy? pmdin = value; // perform write while(pmmodebits.busy); // wait for pmp portdset = 0x0002; //cs disabled }
? 2008 microchip technology inc. preliminary ds61143e-page 459 pic32mx3xx/4xx 20.3.6 slave mode 20.3.6.1 considerations for slave mode ? do not enable or disable the module during any read or write operation ? because of the asynchronous nature of the read and write operations, it is highly recommended that the user rely on the psp status bits prior to any read or write operation. the pmp module provides 8-bit (byte) legacy parallel slave port functionality as well as new buffered and addressable slave modes. 20.3.7 mode selection the three master modes are selected using mode<1:0> bits (pmcon<9:8>). legacy slave mode is selected by configuring mode<1:0> bits = 00 ; buff- ered and addressable slave modes are selected by configuring mode<1:0> = 01 . additionally, buffered slave mode requires bits incm<1:0> (pmmode<12:11>) = 11 . all slave modes support 8-bit data only and the associ- ated module control pins are automatically dedicated to the module when any of these modes are selected. the user only need to configure the polarity of the pmcs1, pmrd and pmwr signals. 20.3.8 legacy parallel slave mode in legacy slave mode, an external device can asyn- chronously read and write data using the 8-bit data bus pmd<7:0>, the read pmrd, write pmwr, and chip-select pmcs1 inputs. figure 20-8: legacy slave mode interface 20.3.9 legacy slave configuration the legacy slave mode configuration is determined automatically and dedicated to the psp module when the legacy slave mode is selected. the user only need to configure the polarity of the pmcs1, pmrd and pmwr signals. the following example illustrates which control bits are to be set for legacy slave mode configuration: ? configure legacy slave mode bits - mode<1:0> (pmmode<9:8>) = 00 ? select pmrd ?active-low? pin polarity - rdsp (pmcon<0>) = 0 . ? select pmwr ?active-low? pin polarity - wrsp (pmcon<1>) = 0 . ? select pmcs2, pmcs1 ?active-low? pin polarity - cs2p (pmcon<4>) = 0 and cs1p (pmcon<3>) = 0 . 20.3.10 slave port initialization the legacy slave mode initialization properly prepares the pmp port for communicating with an external mas- ter device. 1. if interrupts are used, disable the pmp interrupt by clearing the interrupt enable bit pmpie (iec1<2>) = 0 . 2. stop and reset the pmp module by clearing the control bit on (pmcon<15>) = 0 . 3. configure the desired settings in the pmcon and pmmode control registers. 4. if interrupts are used: a) clear interrupt flag bit pmpif (ifs1<2>) = 0 . b) configure the pmp interrupt priority bits pmpip<2:0> (ipc7<4:2>) and interrupt sub priority bits pmpis (ipc7<1:0>. c) enable pmp interrupt by setting interrupt enable bit pmpie = 1 . 5. enable the pmp slave port by setting control bit on = 1 . table 20-8: slave mode selection slave mode pmcon mode<1:0> pmmode incm<1:0> legacy 00 x = don?t care buffered 00 11 addressable 01 x = don?t care table 20-9: slave mode pin polarity configuration control pin pmcon control bit active-high select active-low select pmrd rdsp 10 pmwr wrsp 10 pmcs1 cs1p 10 d<7:0> rd wr master cs pmd<7:0> pmrd pmwr pic32mx3xx/4xx pmcs1 slave
pic32mx3xx/4xx ds61143e-page 460 preliminary ? 2008 microchip technology inc. example 20-4: example code: legacy parallel slave port initialization 20.3.11 buffered slave mode buffered parallel slave port mode is functionally iden- tical to the legacy parallel slave port mode with one exception: the implementation of 4-level read and write buffers. buffered slave mode is enabled by setting the pmmode bits to ? 11 ?. when the buffered mode is active, the module uses the pmdin register as write buffers and the pmdout reg- ister as read buffers, with respect to the master device. each register is divided into four 8-bit buffer registers, four read buffers in pmdout and four write buffers in pmdin. buffers are numbered 0 through 3, starting with the lower byte <7:0> and progressing upward through the high byte <31:24>. figure 20-9: parallel master /slave connection buffered 20.3.12 buffered slave configuration the buffered slave mode configuration is determined automatically and dedicated to the pmp module when the buffered slave mode is selected. the user only need to configure the polarity of the pmcs1, pmrd and pmwr signals. the following example illustrates which control bits are to be set for buffered slave mode configuration: ? configure buffered slave mode bits - mode<1:0> (pmmode<9:8>) = 00 and incm<1:0> (pmmode<12:11>) = 11 . ? select pmrd ?active-low? pin polarity - rdsp (pmcon<0>) = 0 . ? select pmwr ?active-low? pin polarity - wrsp (pmcon<1>) = 0 . ? select pmcs2, pmcs1 ?active-low? pin polarity - cs2p (pmcon<4>) = 0 and cs1p (pmcon<3>) = 0 . iec1clr = 0x0004 //disable pmp int pmcon = 0x0000 //stop and configure pmmode = 0x0000 //config pmmode ipc7set = 0x001c; //priority level=7 ipc7set = 0x0003; //subpriority =3 //same as... //ipc7set=0x001f ifs1clr = 0x0004; //clear pmp flag iec1set = 0x0004; //enable pmp int pmconset = 0x8000; //enable pmp d < 7:0> rd wr master cs pmrd pmwr pic32mx3xx/4xx slave pmcs1 pmdout (0) pmdout (1) pmdout (2) pmdout (3) pmdin (0) pmdin (1) pmdin (2) pmdin (3) pmd<7:0> write address pointer read address pointer
? 2008 microchip technology inc. preliminary ds61143e-page 461 pic32mx3xx/4xx 20.3.13 buffered slave mode initialization the buffered slave mode initialization properly prepares the psp port for communicating with an external master device. the following steps should be performed to properly configure the psp port: 1. if interrupts are used, disable the pmp interrupt by clearing the interrupt enable bit pmpie (iec1<2>) = 0 . 2. stop and reset the pmp module by clearing the control bit on (pmcon<15>) = 0 . 3. configure the desired settings in the pmcon and pmmode control registers. 4. if interrupts are used: a) clear interrupt flag bit pmpif (ifs1<2>) = 0 . b) configure the pmp interrupt priority bits pmpip<2:0> (ipc7<4:2>) and interrupt sub priority bits pmpis (ipc7<1:0>. c) enable psp interrupt by setting interrupt enable bit pmpie = 1 . 5. enable the pmp slave port by setting control bit on = 1 . example 20-5: buffered parallel slave mode initialization iec1clr = 0x0004 //disable pmp pmcon = 0x0000 //stop and configure pmmode = 0x1800 //configure pmmode ipc7set = 0x001c; //priority level=7 ipc7set = 0x0003; //subpriority=3 //same as... //ipc7set=0x001f ifs1clr = 0x0004; //clear pmp flag iec1set = 0x0004; //enable pmp int pmconset = 0x8000; //enable pmp
pic32mx3xx/4xx ds61143e-page 462 preliminary ? 2008 microchip technology inc. 20.3.14 addressable slave mode in the addressable parallel slave port mode, the mod- ule is configured with two extra inputs, pma<1:0>. this makes the 4-byte buffer space directly addressable as fixed pairs of read and write buffers. as with buffered legacy mode, data is output from register pmdout and is input to register pmdin. table 20-10 shows the address resolution for the incoming address to the input and output registers. figure 20-10: parallel master/s lave connection addressable buffer 20.3.15 addressable slave configuration the addressable slave mode configuration is deter- mined automatically and dedicated to the psp module when the addressable slave mode is selected. the user only need to configure the polarity of the pmcs1, pmrd and pmwr signals. the following example illustrates which control bits are to be set for addressable slave mode configuration: ? configure addressable slave mode bits ? mode<1:0> (pmmode<9:8>) = 01 ? select pmrd ?active-low? pin polarity ? rdsp (pmcon<0>) = 0 ? select pmwr ?active-low? pin polarity ? wrsp (pmcon<1>) = 0 ? select pmcs2, pmcs1 ?active-low? pin polarity ? cs2p(pmcon<4>)= 0 andcs1p(pmcon<3>)= 0 20.3.16 addressable slave port initialization the addressable slave mode initialization properly prepares the psp port for communicating with an external master device. the following steps should be performed to properly configure the psp port: 1. if interrupts are used, disable the pmp interrupt by clearing the interrupt enable bit pmpie (iec1<2>) = 0 . 2. stop and reset the pmp module by clearing the control bit on (pmcon<15>) = 0 . 3. configure the desired settings in the pmcon and pmmode control registers. 4. if interrupts are used: a) clear interrupt flag bit pmpif (ifs1<2>) = 0 . b) configure the pmp interrupt priority bits pmpip<2:0> (ipc7<4:2>) and interrupt sub priority bits pmpis (ipc7<1:0>. c) enable psp interrupt by setting interrupt enable bit pmpie = 1 . 5. enable the pmp slave port by setting control bit on = 1 . table 20-10: slave mode buffer addresses pma<1:0> output register pmdout (buffer) input register pmdin (buffer) 00 <7:0> (0) <7:0> (0) 01 <15:8> (1) <15:8> (1) 10 <23:16> (2) <23:16> (2) 11 <31:24> (3) <31:24> (3) d<7:0> rd wr master cs a<1:0> pmrd pmwr pic32mx3xx/4xx slave pmcs1 pmdout (0) pmdout (1) pmdout (2) pmdout (3) pmdin (0) pmdin (1) pmdin (2) pmdin (3) pmd<7:0> write address decode read address decode pma<1:0>
? 2008 microchip technology inc. preliminary ds61143e-page 463 pic32mx3xx/4xx example 20-6: addressable parallel slave port initialization 20.4 pmp interrupts the pmp module has the ability to generate the follow- ing types of interrupts reflecting the events that occur during data transfers. master mode: ? interrupt on every read and write operation. legacy slave mode: ? interrupt on every read and write byte buffered slave mode: ? interrupt on every read and write byte ? interrupt on read or write byte of buffer 3 (pmdout<31:24>) addressable slave mode: ? interrupt on every read and write byte ? interrupt on read or write byte of buffer 3 (pmdout<31:24>), pma<1:0> = 11 the pmp module is enabled as a source of interrupt using the pmp interrupt enable bit: ? pmpie (iec1<2>). the interrupt priority level and subpriority level bits must also be configured: - pmpip<2:0> (ipc7<4:2>) - pmpis<1:0> (ipc7<1:0>) ? the pmp interrupt status flag, pmpif (ifs1<2>) is typically cleared by the user?s software in the isr. below is a partial code example of an isr. iec1clr = 0x0004 //disable pmp int pmcon = 0x0000 //stop and configure pmmode = 0x0100 //config pmmode ipc7set = 0x001c; //priority level=7 ipc7set = 0x0003; //subpriority=3 //same as... //ipc7set=0x001f ifs1clr = 0x0004; //clear pmp int flag iec1set = 0x0004; //enable pmp int pmconset = 0x8000; //enable pmp module note: it is the user?s responsibility to clear the corresponding interrupt flag bit before returning from an isr.
pic32mx3xx/4xx ds61143e-page 464 preliminary ? 2008 microchip technology inc. example 20-7: pmp module interrupt initialization example 20-8: pmp isr /* the following code example illustrates a pmp interrupt configuration. when the pmp interrupt is generated, the cpu will branch to the vector assigned to pmp interrupt. */ // configure pmp for desired mode of operation ... // configure the pmp interrupts ipc7set = 0x0014; // set priority level=5 ipc7set = 0x0003; // set subpriority level=3 // could have also done this in single // operation by assigning ipc7set = 0x0017 ifs1clr = 0x0002; // clear the pmp interrupt status flag iec1set = 0x0002; // enable pmp interrupts pmconset = 0x8000; // enable pmp module /* the following code example demonstrates a simple interrupt service routine for pmp interrupts. the user?s code at this vector should perform any application specific operations and must clear the pmp interrupt status flag before exiting. */ void __isr(_pmp_vector, ipl5) pmp_interrupt_isr(void) { ... perform application specific operations in response to the interrupt ifs1clr = 0x00002; // be sure to clear the pmp interrupt status // flag before exiting the service routine. } note: the pmp isr code example shows mplab ? c32 c compiler-specific syntax. refer to your computer manual regarding support for isrs.
? 2008 microchip technology inc. preliminary ds61143e-page 465 pic32mx3xx/4xx 20.5 i/o pin control when enabling any of the pmp module for slave mode operations, the pmpcs1, pmrd, pmwr control pins, pmd<7:0> data pins and pma<1:0> address pins are automatically enabled and configured. the user is how- ever responsible for selecting the appropriate polarity for these control lines. table 20-11: required i/o pin resources for master modes i/o pin name de- multiplex partial multiplex full multiplex functional description pmpcs2 / pma15 yes (2) yes (2) yes (2) pmp chip select 2 / address a15 pmpcs1 / pma14 yes (2) yes (2) yes (2) pmp chip select 1 / address a14 pma<13:2> yes (2) yes (3) no (1) pmp address a13..a2 pma1 / pmalh no (1) no (1) yes (4) pmp address a1 / address latch high pma0 / pmall no (1) yes (2) yes (4) pmp address a0 / address latch low pmrd / pmwr yes yes yes pmp read / write control pmwr / pmenb yes yes yes pmp write / enable control pmd<15:0> yes (5) yes (5) yes (5) pmp bidirectional data bus d15..d0 note: 1. ?no? indicates the pin is not required and is available as a general purpose i/o pin when the corresponding pmaen bit is cleared, = 0. 2. depending on the application, not all pma<15:0> or cs2, cs1 may be required. 3. when partial multiplex mode is selected (addrmux<1:0> = 01 ), the lower 8 address lines are multiplexed with pmd<7:0>, pma<0> becomes (pmall) and pma<7:1> are available as general purpose i/o pins. 4. when full multiplex mode is selected (addrmux<1:0> = 10 or 11 ), all 16 address lines are multiplexed with pmd<15:0>, pma<0> becomes (pmall), pma<1> becomes (pmalh) and pma<13:2> are available as general purpose i/o pins. 5. if mode16 = 0 , then only pmd<7:0> are required. pmd<15:8> are available as general purpose i/o pins. 6. data pins pmd<15:0> are available on 100-pin pic32mx3xx/4xx devices and larger. for all other device variants, only pins pmd<7:0> are available. table 20-12: required i/o pi n resources for slave modes i/o pin name legacy buffered addressable functional description pmpcs1 / pma14 yes yes yes chip select pma1 / pmalh no (1) no (1) yes address a1 pma0 / pmall no (1) no (1) yes address a0 pmrd / pmwr yes yes yes read control pmwr / pmenb yes yes yes write control pmd<7:0> yes (2) yes (2) yes (2) bidirectional data bus d7..d0 note: 1. ?no? indicates the pin is not required and is available as a general purpose i/o pin when the corresponding pmaen bit is cleared, = 0 . 2. slave modes use pmd<7:0> only. pins pmd<15:8> are available as general purpose i/o pins. control bit mode16 (pmmode<10>) is ignored.
pic32mx3xx/4xx ds61143e-page 466 preliminary ? 2008 microchip technology inc. 20.5.1 i/o pin configuration the following table provides a summary of settings required to enable the i/o pin resources used with this module. the pmaen register controls the functionality of pins pma<15:0>. setting any pmaen bit = 1 config- ures the corresponding pma pin as an address line. those bits set = 0 remain as general purpose i/o pins. table 20-13: i/o pin configuration required settings for module pin control i/o pin name required (1) module control bit field tris pin type buffer type (2) description pmpcs2 / pma15 yes on csf<1:0>, cs2, pten15 ? o st/ttl pmp chip select 2 / address a15 pmpcs1 / pma14 yes on csf<1:0>, cs1 pten14 ? o st/ttl pmp chip select 1 / address a14 pma<13:2> yes on pten<13:2> ? o st/ttl pmp address a13..a2 pma1 / pmalh yes on pten<1> ? i,o st/ttl pmp address a1 / address latch hi pma0 / pmall yes on pten<0> ? i,o st/ttl pmp address a0 / address latch lo pmrd / pmwr yes on ptrden ? o st/ttl pmp read / write control pmwr / pmenb yes on ptwren ? o st/ttl pmp write / enable control pmd<15:0> yes on mode16, adrmux<1:0> ? i,o st/ttl pmp bidirectional data bus d15..d0 legend: ttl = ttl compatible input or output, st = schmitt trigger input with cmos levels, i = input, o = output note: 1. depending on the pmp mode and the user?s application, these pins may not be required. if not enabled, these pins can be used as general purpose i/o. 2. default buffer type is st.
? 2008 microchip technology inc. preliminary ds61143e-page 467 pic32mx3xx/4xx 21.0 real-time clock and calendar (rtcc) the pic32mx real-time clock and calendar (rtcc) module is intended for applications where accurate time must be maintained for extended periods of time with minimal or no cpu intervention. low-power optimization provides extended battery lifetime while keeping track of time. following are some of the key features of this module: ? time: hours, minutes and seconds ? 24-hour format (military time) ? visibility of one-half-second period ? provides calendar: weekday, date, month and year ? alarm intervals are configurable for half of a second, one second, 10 seconds, one minute, 10 minutes, one hour, one day, one week, one month and one year ? alarm repeat with decrementing counter ? alarm with indefinite repeat: chime ? year range: 2000 to 2099 ? leap year correction ? bcd format for smaller firmware overhead ? optimized for long-term battery operation ? fractional second synchronization ? user calibration of the clock crystal frequency with auto-adjust ? calibration range: 0.66 seconds error per month ? calibrates up to 260 ppm of crystal error ? requirements: external 32.768 khz clock crystal ? alarm pulse or seconds clock output on rtcc pin figure 21-1: rt cc block diagram note: this data sheet summarizes the features of the pic32mx3xx/4xx family of devices. it is not intended to be a comprehensive refer- ence source. refer to the ?pic32mx family reference manual? (ds61132) for a detailed description of this peripheral. seconds pulse rtcc prescalers rtcc timer comparator compare registers repeat counter year, mth, day wkday hr, min, sec mth, day wkday hr, min, sec with masks rtcc interrupt logic alarm event 32.768 khz input from sosc oscillator 0.5s alarm pulse rtcc interrupt rtcval alrmval rtcc pin rtcoe
pic32mx3xx/4xx ds61143e-page 468 preliminary ? 2008 microchip technology inc. 21.1 rtcc registers table 21-1: rtcc sfr summary table 21-2: rtcc interrupt register summary virtual address name bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 bf80_0200 rtccon 31:24 ? ? ? ? ? ? cal<9:8> 23:16 cal<7:0> 15:8 on frz sidl ? ? ? ? ? 7:0 rtsecsel rtcclkon ? ? rtcwren rtcsync halfsec rtcoe bf80_0204 rtcconclr 31:0 write clears selected bits in rtccon, read yields undefined value bf80_0208 rtcconset 31:0 write sets selected bits in rtccon, read yields undefined value bf80_020c rtcconinv 31:0 write inverts selected bits in rtccon, read yields undefined value bf80_0210 rtcalrm 31:24 ? ? ? ? ? ? ? ? 23:16 ? ? ? ? ? ? ? ? 15:8 alrmen chime piv alrmsync amask<3:0> 7:0 arpt<7:0> bf80_0214 rtcalrmclr 31:0 write clears selected bits in rtcalrm, read yields undefined value bf80_0218 rtcalrmset 31:0 write sets selected bits in rtcalrm, read yields undefined value bf80_021c rtcalrminv 31:0 write inverts selected bits in rtcalrm, read yields undefined value bf80_0220 rtctime 31:24 hr10<3:0> hr01<3:0> 23:16 min10<3:0> min01<3:0> 15:8 sec10<3:0> sec01<3:0> 7:0 ? ? ? ? ? ? ? ? bf80_0224 rtctimeclr 31:0 write clears selected bits in rtctime, read yields undefined value bf80_0228 rtctimeset 31:0 write sets selected bits in rtctime, read yields undefined value bf80_022c rtctimeinv 31:0 write inverts selected bits in rtctime, read yields undefined value bf80_0230 rtcdate 31:24 year10<3:0> year01<3:0> 23:16 month10<3:0> month01<3:0> 15:8 day10<3:0> day01<3:0> 7:0 ? ? ? ? wday01<3:0> bf80_0234 rtcdateclr 31:0 write clears selected bits in rtcdate, read yields undefined value bf80_0238 rtcdateset 31:0 write sets selected bits in rtcdate, read yields undefined value bf80_023c rtcdateinv 31:0 write inverts selected bits in rtcdate, read yields undefined value bf80_0240 alrmtime 31:24 hr10<3:0> hr01<3:0> 23:16 min10<3:0> min01<3:0> 15:8 sec10<3:0> sec01<3:0> 7:0 ? ? ? ? ? ? ? ? bf80_0244 alrmtimclr 31:0 write clears selected bits in alrmtime, read yields undefined value bf80_0248 alrmtimeset 31:0 write sets selected bits in alrmtime, read yields undefined value bf80_024c alrmtimeinv 31:0 write inverts selected bits in alrmtime, read yields undefined value bf80_0250 alrmdate 31:24 ? ? ? ? ? ? ? ? 23:16 month10<3:0> month01<3:0> 15:8 day10<3:0> day01<3:0> 7:0 ? ? ? ? wday01<3:0> bf80_0254 alrmdateclr 31:0 write clears selected bits in alrmdate, read yields undefined value bf80_0258 alrmdateset 31:0 write sets selected bits in alrmdate, read yields undefined value bf80_025c alrmdateinv 31:0 write inverts selected bits in alrmdate, read yields undefined value virtual address name bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 bf88_1070 iec1 15:8 rtccie fscmie i2c2mie i2c2sie i2c2bie u2txie u2rxie u2eie bf88_1040 ifs1 15:8 rtccif fscmif i2c2mif i2c2sif i2c2bif u2txif u2rxif u2eif bf88_1110 ipc8 31:24 ? ? ? rtccip<2:0> rtccis<1:0> note: this summary table contains partial register definitions that only pertain to the rtcc peripheral. refer to the ? pic32mx family reference manual ? (ds61132) for a detailed description of these registers.
? 2008 microchip technology inc. preliminary ds61143e-page 469 pic32mx3xx/4xx register 21-1: rtccon: rtc control register (1) r-x r-x r-x r-x r-x r-x r/w-0 r/w-0 ? ? ? ? ? ?cal<9:8> bit 31 bit 24 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 cal<7:0> bit 23 bit 16 r/w-0 r/w-0 r/w-0 r-x r-x r-x r-x r-x on frz sidl ? ? ? ? ? bit 15 bit 8 r/w-0 r-0 r-x r-x r/w-0 r-0 r-0 r/w-0 rtsecsel rtcclkon ? ? rtcwren rtcsync halfsec rtcoe bit 7 bit 0 legend: r = readable bit w = writable bit p = programmable bit r = reserved bit u = unimplemented bit -n = bit value at por: (?0?, ?1?, x = unknown) bit 31-26 reserved: write ? 0 ?; ignore read bit 25-16 cal<9:0>: rtc drift calibration bits contains a signed 10-bit integer value. 0111111111 = maximum positive adjustment, adds 511 rtc clock pulses every one minute ... 0000000001 = minimum positive adjustment, adds 1 rtc clock pulse every one minute 0000000000 = no adjustment 1111111111 = minimum negative adjustment, subtracts 1 rtc clock pulse every one minute ... 1000000000 = minimum negative adjustment, subtracts 512 clock pulses every one minute bit 15 on: rtcc on bit 1 = rtcc module is enabled 0 = rtcc module is disabled note: the on bit is only writable when rtcwren = 1 . bit 14 frz: freeze in debug mode bit 1 = when emulator is in debug mode, module freezes operation 0 = when emulator is in debug mode, module continues operation note: frz is writable in debug exception mode only, it is forced to ? 0 ? in normal mode. bit 13 sidl: stop in idle mode bit 1 = disables the pbclk to the rtcc when cpu enters in idle mode 0 = continue normal operation in idle mode bit 12-8 reserved: write ? 0 ?; ignore read bit 7 rtsecsel: rtcc seconds clock output select bit 1 = rtcc seconds clock is selected for the rtcc pin 0 = rtcc alarm pulse is selected for the rtcc pin note: requires rtcoe == 1 (rtccon<0>) for the output to be active. bit 6 rtcclkon: status of the rtcc clock enable bit 1 = rtcc clock is actively running 0 = rtcc clock is not running
pic32mx3xx/4xx ds61143e-page 470 preliminary ? 2008 microchip technology inc. bit 5-4 reserved: write ? 0 ?; ignore read bit 3 rtcwren: rtc value registers write enable bit 1 = rtc value registers can be written to by the user 0 = rtc value registers are locked out from being written to by the user note: the rtcwren bit can be set only when the write sequence is enabled. the register can be written to a ? 0 ? at any time. bit 2 rtcsync: rtcc value registers read synchronization bit 1 = rtc value registers can change while reading due to a roll over ripple that results in an invalid data read. if the register is read twice and results in the same data, the data can be assumed to be valid. 0 = rtc value registers can be read without concern about a roll over ripple bit 1 halfsec: half-second status bit 1 = second half period of a second 0 = first half period of a second note: this bit is read-only. it is cleared to ? 0 ? on a write to the seconds register. bit 0 rtcoe: rtcc output enable bit 1 = rtcc clock output enabled ? clock presented onto an i/o 0 = rtcc clock output disabled note: this bit is anded with on (rtccon<15>) to produce the effective rtcc output enable. note 1: this register is only reset by power-on reset (por). register 21-1: rtccon: rtc control register (1) (continued)
? 2008 microchip technology inc. preliminary ds61143e-page 471 pic32mx3xx/4xx register 21-2: rtcalrm: rtc alarm control register (1) r-x r-x r-x r-x r-x r-x r-x r-x ? ? ? ? ? ? ? ? bit 31 bit 24 r-x r-x r-x r-x r-x r-x r-x r-x ? ? ? ? ? ? ? ? bit 23 bit 16 r/w-0 r/w-0 r/w-0 r-0 r/w-0 r/w-0 r/w-0 r/w-0 alrmen chime piv alrmsync amask<3:0> bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 arpt<7:0> bit 7 bit 0 legend: r = readable bit w = writable bit p = programmable bit r = reserved bit u = unimplemented bit -n = bit value at por: (?0?, ?1?, x = unknown) bit 31-16 reserved: write ? 0 ?; ignore read bit 15 alrmen: alarm enable bit 1 = alarm is enabled 0 = alarm is disabled note: hardware clears alrmen anytime the alarm event occurs, when arpt<7:0> = 00 and chime = 0 . this field should not be written when rtccon = 1 (rtccon<15>) and alrmsync = 1 . bit 14 chime: chime enable bit 1 = chime is enabled ? arpt<7:0> is allowed to roll over from 00 to ff 0 = chime is disabled ? arpt<7:0> stops once it reaches 00 note: this field should not be written when rtccon = 1 (rtccon<15>) and alrmsync = 1 . bit 13 piv: alarm pulse initial value bit when alrmen = 0 , piv is writable and determines the initial value of the alarm pulse. when alrmen = 1 , piv is read-only and returns the state of the alarm pulse. note: this field should not be written when rtccon = 1 (rtccon<15>) and alrmsync = 1 . bit 12 alrmsync: alarm sync bit 1 = arpt<7:0> and alrmen may change as a result of a half-second rollover during a read. the arpt must be read repeatedly until the same value is read twice. this must be done since multiple bits may be changing, which are then synchronized to the pb clock domain. 0 = arpt<7:0> and alrmen can be read without concerns of rollover because prescaler is > 32 rtc clock away from a half-second rollover note: this assumes a cpu read will execute in less than 32 pbclks.
pic32mx3xx/4xx ds61143e-page 472 preliminary ? 2008 microchip technology inc. bit 11-8 amask<3:0>: alarm mask configuration bits 0000 = every half-second 0001 = every second 0010 = every 10 seconds 0011 = every minute 0100 = every 10 minutes 0101 = every hour 0110 = once a day 0111 = once a week 1000 = once a month 1001 = once a year (except when configured for february 29th, once every 4 years) 1010 = reserved ? do not use 1011 = reserved ? do not use 11xx = reserved ? do not use note: this field should not be written when rtccon = 1 (rtccon<15>) and alrmsync = 1 . bit 7-0 arpt<7:0>: alarm repeat counter value bits 11111111 = alarm will trigger 256 times ... 00000000 = alarm will trigger 1 time the counter decrements on any alarm event. the counter only rolls over from 00 to ff if chime = 1 . note: this field should not be written when rtccon = 1 (rtccon<15>) and alrmsync = 1 . note 1: this register is only reset by por. register 21-2: rtcalrm: rtc alarm control register (1) (continued)
? 2008 microchip technology inc. preliminary ds61143e-page 473 pic32mx3xx/4xx register 21-3: rtctime: rtc time value register (1) r-0 r-0 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x hr10<3:0> hr01<3:0> bit 31 bit 24 r-0 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x min10<3:0> min01<3:0> bit 23 bit 16 r-0 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x sec10<3:0> sec01<3:0> bit 15 bit 8 r-x r-x r-x r-x r-x r-x r-x r-x ? ? ? ? ? ? ? ? bit 7 bit 0 legend: r = readable bit w = writable bit p = programmable bit r = reserved bit u = unimplemented bit -n = bit value at por: (?0?, ?1?, x = unknown) bit 31-28 hr10<3:0>: binary coded decimal value of hours bits 10 digits; contains a value from 0 to 2. note: hr10<3:2> bits are always read ? 0 ?. bit 27-24 hr01<3:0>: binary coded decimal value of hours bits 1 digit; contains a value from 0 to 9. bit 23-20 min10<3:0>: binary coded decimal value of minutes bits 10 digits; contains a value from 0 to 5. note: min10<3> bit is always read ? 0 ?. bit 19-16 min01<3:0>: binary coded decimal value of minutes bits 1 digit; contains a value from 0 to 9. bit 15-12 sec10<3:0>: binary coded decimal value of seconds bits 10 digits; contains a value from 0 to 5. note: sec10<3> bit is always read ? 0 ?. bit 11-8 sec01<3:0>: binary coded decimal value of seconds bits 1 digit; contains a value from 0 to 9. bit 7-0 reserved: write ? 0 ?; ignore read note 1: this register is only writable when rtcwren = 1 (rtccon<3>).
pic32mx3xx/4xx ds61143e-page 474 preliminary ? 2008 microchip technology inc. register 21-4: rtcdate: rtc date value register (1) r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x year10<3:0> year01<3:0> bit 31 bit 24 r-0 r-0 r-0 r/w-x r/w-x r/w-x r/w-x r/w-x month10<3:0> month01<3:0> bit 23 bit 16 r-0 r-0 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x day10<3:0> day01<3:0> bit 15 bit 8 r-x r-x r-x r-x r-0 r/w-x r/w-x r/w-x ? ? ? ? wday01<3:0> bit 7 bit 0 legend: r = readable bit w = writable bit p = programmable bit r = reserved bit u = unimplemented bit -n = bit value at por: (?0?, ?1?, x = unknown) bit 31-28 year10<3:0>: binary coded decimal value of years bits (10 digits) bit 27-24 year01<3:0>: binary coded decimal value of years bits (1 digit) bit 23-20 month10<3:0>: binary coded decimal value of months bits (10 digits; contains a value from 0 to 1) note: month10<3:1> bits are always read ? 0 ?. bit 19-16 month01<3:0>: binary coded decimal value of months bits (1 digit; contains a value from 0 to 9) bit 15-12 day10<3:0>: binary coded decimal value of days bits (10 digits; contains a value from 0 to 3) note: day10<3:2> bits are always read ? 0 ?. bit 11-8 day01<3:0>: binary coded decimal value of days bits (1 digit; contains a value from 0 to 9) bit 7-4 reserved: write ? 0 ?; ignore read bit 3-0 wday01<3:0>: binary coded decimal value of weekdays bits (1 digit; contains a value from 0 to 6) note: wday01<3> bit is always read ? 0 ?. note 1: this register is only writable when rtcwren = 1 (rtccon<3>).
? 2008 microchip technology inc. preliminary ds61143e-page 475 pic32mx3xx/4xx register 21-5: alrmtime: alarm time value register r-0 r-0 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x hr10<3:0> hr01<3:0> bit 31 bit 24 r-0 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x min10<3:0> min01<3:0> bit 23 bit 16 r-0 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x sec10<3:0> sec01<3:0> bit 15 bit 8 r-x r-x r-x r-x r-x r-x r-x r-x ? ? ? ? ? ? ? ? bit 7 bit 0 legend: r = readable bit w = writable bit p = programmable bit r = reserved bit u = unimplemented bit -n = bit value at por: (?0?, ?1?, x = unknown) bit 31-28 hr10<3:0>: binary coded decimal value of hours bits (10 digit; contains a value from 0 to 2) note: hr10<3:2> bits are always read ? 0 ?. bit 27-24 hr01<3:0>: binary coded decimal value of hours bits (1 digit; contains a value from 0 to 9) bit 23-20 min10<3:0>: binary coded decimal value of minutes bits, (10 digit; contains a value from 0 to 5) note: min10<3> bit is always read ? 0 ?. bit 19-16 min01<3:0>: binary coded decimal value of minutes bits (1 digit; contains a value from 0 to 9) bit 15-12 sec10<3:0>: binary coded decimal value of seconds bits (10 digit; contains a value from 0 to 5) note: sec10<3> bit is always read ? 0 ?. bit 11-8 sec01<3:0>: binary coded decimal value of seconds bits (1 digit; contains a value from 0 to 9) bit 7-0 reserved: write ? 0 ?; ignore read
pic32mx3xx/4xx ds61143e-page 476 preliminary ? 2008 microchip technology inc. register 21-6: alrmdate: alarm date value register r-x r-x r-x r-x r-x r-x r-x r-x ? ? ? ? ? ? ? ? bit 31 bit 24 r-0 r-0 r-0 r/w-x r/w-x r/w-x r/w-x r/w-x month10<3:0> month01<3:0> bit 23 bit 16 r-0 r-0 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x day10<3:0> day01<3:0> bit 15 bit 8 r-x r-x r-x r-x r-0 r/w-x r/w-x r/w-x ? ? ? ? wday01<3:0> bit 7 bit 0 legend: r = readable bit w = writable bit p = programmable bit r = reserved bit u = unimplemented bit -n = bit value at por: (?0?, ?1?, x = unknown) bit 31-24 reserved: write ? 0 ?; ignore read. bit 23-20 month10<3:0>: binary coded decimal value of months bits (10 digit; contains a value from 0 to 1) note: month10<3:1> bits are always read ? 0 ?. bit 19-16 month01<3:0>: binary coded decimal value of months bits (1 digit; contains a value from 0 to 9) bit 15-12 day10<3:0>: binary coded decimal value of days bits (10 digit; contains a value from 0 to 3) note: day10<3:2> bits are always read ? 0 ?. bit 11-8 day01<3:0>: binary coded decimal value of days bits (1 digit; contains a value from 0 to 9) bit 7-4 reserved: write ? 0 ?; ignore read bit 3-0 wday01<3:0>: binary coded decimal value of weekdays bits (1 digit; contains a value from 0 to 6) note: wday01<3> bit is always read ? 0 ?.
? 2008 microchip technology inc. preliminary ds61143e-page 477 pic32mx3xx/4xx 21.2 clock calendar mode the pic32mx rtcc module provides clock and calendar functions with the following features: ? 100-year clock and calendar with automatic leap year detection. ? clock range from 00:00:00 (midnight) on january 1, 2000 to 23:59:59 on december 31, 2099. ? clock granularity of one second with half-second visibility to the user. 21.2.1 rtcc configuration the rtctime and rtcdate registers can be programmed with the desired time and date numeric values expressed in binary coded decimal (bcd) format. this simplifies users? firmware as each of the digit values is contained within its own 4-bit value (see figure 21-2). figure 21-2: timer digit format the user can configure the current time by simply writing the desired year, month, day, hour, minutes and seconds to the rtctime and rtcdate registers. however, these registers are write-protected and require a spe- cial ?unlock? sequence to be performed prior to writing to these registers. additionally, the user should verify that the rtcsync bit (rtccon<2>) = 0 (safe to access registers) for any read or write operations. refer to section 21.2.3 ?write lock? and example 21-3. 21.2.2 safety window for register reads and writes the rtctime and rtcdate registers can be safely accessed when the rtcc module is disabled (on bit (rtccon<15>) = 0) . however, when the rtcc mod- ule is enabled (on bit = 1) , the module provides a single rtcsync bit (rtccon<2>) that the user must use to determine when it is safe to read and update the time and date registers. the rtcsync bit indicates a time window during which the rtcc time registers (rtctime, rtcdate) are not about to be updated and can be safely read and written. for read or write operations, the registers can be safely accessed by the cpu when rtcsync = 0 . for a read operation when rtsync = 1 , the user must employ a firmware solution to assure that the data read did not fall on an update boundary, resulting in an invalid or partial read. for example, reading and com- paring a timer register value twice can ensure in code that the register read did not span an rtcc clock update. write operations to the time and date registers should not be performed when rtcsync = 1 . refer to example 21-2 and example 21-3. 0-6 0-9 0-9 0-3 0-9 0-9 0-9 0-9 0-2 0-5 0-5 0/1 day of year day hours (24-hr format) minutes seconds 1/2 second 0-1 0-9 month (binary format) week bit
pic32mx3xx/4xx ds61143e-page 478 preliminary ? 2008 microchip technology inc. example 21-1: updating the rtcc time and date example 21-2: updating the rtcc time using the rtcsync window 21.2.3 write lock in order to perform a write to any of the rtcc time reg- isters, the rtcwren bit (rtccon<3>) must be set. setting of the rtcwren bit is only allowed once the device level unlocking sequence has been executed. the unlocking sequence is as follows: 1. suspend or disable all initiators that can access the peripheral bus and interrupt the unlock sequence. (i.e., dma and interrupts). 2. store 0xaa996655 to the syskey register. 3. store 0x556699aa to the syskey register. 4. set rtcwren bit into the rtccon register. 5. perform the device relock by writing a dummy value to the syskey register. 6. re-enable dma and interrupts. note that steps 2 through 4 must be followed exactly to unlock rtcc write operations. if the sequence is not followed exactly, the rtcwren bit will not be set. refer to example 21-3 for a ?c? language implementation of the write unlock operation. /* the following code example will update the rtcc time and date. */ // assume the secondary oscillator is enabled and ready, i.e. // osccon<1>=1, osccon<22>=1, and rtcc write is enabled i.e. // rtcwren (rtccon<3>) =1; unsigned long time=0x04153300;// set time to 04 hr, 15 min, 33 sec unsigned long date=0x06102705;// set date to friday 27 oct 2006 rtcconclr=0x8000; // turn off the rtcc while(rtccon&0x40); // wait for clock to be turned off rtctime=time; // safe to update the time rtcdate=date; // update the date rtcconset=0x8000; // turn on the rtcc while(!(rtccon&0x40)); // wait for clock to be turned on // can disable the rtcc write /* the following code example will update the rtcc time and date. */ // assume rtcc write is enabled i.e. rtcwren (rtccon<3>) =1; unsigned long time=0x04153300;// set time to 04 hr, 15 min, 33 sec unsigned long date=0x06102705;// set date to friday 27 oct 2006 // disable interrupts, critical section follows asm volatile (?di?); while((rtccon&0x4)!=0); // wait for not rtcsync rtctime=time; // safe to update the time rtcdate=date; // update the date // restore interrupts, critical section ended asm volatile (?ei?); // can disable the rtcc write
? 2008 microchip technology inc. preliminary ds61143e-page 479 pic32mx3xx/4xx example 21-3: write unlock sequence note: to avoid accidental writes to the rtcc time values, it is recommended that the rtcwren bit (rtccon<3>) is kept clear at any other time. // assume interrupts are disabled // assume the dma controller is suspended // assume the device is locked // starting critical sequence syskey = 0xaa996655; // write first unlock key to syskey syskey = 0x556699aa; // write second unlock key to syskey rtcconset = 0x8; // set rtcwren in rtcconset // end critical sequence syskey = 0x33333333; // perform device re-lock // can resume the dma controller activity // can re-enable interrupts
pic32mx3xx/4xx ds61143e-page 480 preliminary ? 2008 microchip technology inc. 21.3 alarm mode the pic32mx rtcc module provides alarm functions with the following features: ? one-time alarm ? repeat alarms ? indefinite alarm repetition ? configurable from half-second to one year the rtcc alarm generates an alarm event when the rtcc timer matches the masked alarm value. the rtcc alarm functions are configurable from a half-second to one year and can repeat the alarm at preconfigured intervals. the chime feature provides indefinite repetition of the alarm. to enable the alarm feature, configure the alrmen bit (rtcalrm<15>) = 1 . to disable the alarm feature, configure the alrmen bit = 0 . an alarm event is generated when the rtcc timer matches the masked alarm registers. 21.3.1 alarm configuration the alrmtime and alrmdate registers can be pro- grammed with the desired time and date numeric val- ues expressed in binary coded decimal (bcd) format. this simplifies users? firmware as each of the digit values is contained within its own 4-bit value (see figure 21-3). figure 21-3: alarm digit format the alarm interval selection is based on the settings of the alarm mask, amask (rtcalrm<11:8>). the amask bits determine which and how many digits of the alarm must match the rtcc clock value for the alarm event to occur (see figure 21-4). figure 21-4: alarm mask settings 21.3.2 one-time alarm a single, one-time alarm can be generated by configur- ing the alarm repeat counter bits, arpt (rtcalrm<7:0>) = 0 , and the chime bit, (rtcalrm<14>) = 0 . once the alarm event occurs, the alrmen bit is automatically cleared in hardware, disabling future alarms. the user must re-enable this bit for any new alarm configuration. it is suggested to read and verify the alarm sync bit, alrmsync (rtcalrm<12>) = 0 , before performing the following configuration: ? disable alarm ? alrmen (rtcalrm<15>) = 0 . ? disable chime ? chime (rtcalrm<14>) = 0 . ? clear alarm repeat counter ? arpt (rtcalrm<7:0>) = 0 . the remaining bits are shown with example configura- tions and may be configured as desired: ? configure alarm date and time ? load alrmdate and alrmtime registers with the desired alarm date/time values. ? configure mask ? load the desired amask value. ? enable alarm ? alrmen (rtcalrm<15>) = 0 . refer to example 21-4 note 1: once the timer value reaches the alarm setting, one rtcc clock period will elapse prior to setting the alarm interrupt. 2: if rtcc is off (rtccon<15> = 0 ) the writable fields in the rtcalrm register can be safely modified. if rtcc is on, the write of the rtcalrm register has to be done while alrmsync = 0 . not fol- lowing the above steps can result in a false alarm event. 3: the same applies to the alrmtime and alrmdate registers: they can be safely modified only when alrmsync = 0 . 0-6 0-3 0-9 0-9 0-9 0-9 0-2 0-5 0-5 day of week day hours (24-hr format) minutes seconds 0-1 0-9 month note 1: annually, except when configured for february 29. s ss mss mm s s hh mm ss dhhmmss dd hh mm s s mm d d h h mm s s day of the week month day hours minutes seconds alarm mask setting amask<3:0> 0000 ? every half-second 0001 ? every second 0010 ? every 10 seconds 0011 ? every minute 0100 ? every 10 minutes 0101 ? every hour 0110 ? every day 0111 ? every week 1000 ? every month 1001 ? every year (1)
? 2008 microchip technology inc. preliminary ds61143e-page 481 pic32mx3xx/4xx example 21-4: configuring the rtcc for a one-time alarm 21.3.3 repeat alarm a repeat alarm can be generated by configuring the alarm repeat counter bits, arpt (rtcalrm<7:0>) = 0x00 to 0xff (0 to 255), and the chime bit (rtcalrm<14>) = 0 . once the alarm is enabled and an alarm event occurs, the arpt count is decre- mented by one. once the register reaches 0, the alarm will be generated one last time; after which point, alrmen bit is cleared automatically and the alarm will turn off. the user must re-enable this bit for any new alarm configuration. it is recommended to read and verify the alarm sync bit alrmsync (rtcalrm<12>) = 0 , before performing the following configuration steps: ? disable alarm ? alrmen (rtcalrm<15>) = 0 . ? disable chime ? chime (rtcalrm<14>) = 0 . ? configure alarm repeat counter ? arpt (rtcalrm<7:0>) = 0x00 to 0xff. ? configure alarm date and time ? load alrmdate and alrmtime registers with the desired alarm date/time values. ? configure mask ? load the desired amask value. ? enable alarm ? alrmen (rtcalrm<15>) = 0 . refer to example 21-5. example 21-5: configuring the rt cc for a ten times per hour alarm /* the following code example will update the rtcc one-time alarm. assumes the interrupts are disabled. */ unsigned long altime=0x16153300;// set time to 04 hr, 15 min, 33 sec unsigned long aldate=0x06102705;// set date to friday 27 oct 2006 // turn off the alarm, chime and alarm repeats; clear // the alarm mask while(rtcalrm&0x1000); // wait alrmsync to be off rtcalrmclr=0xcfff; // clear alrmen, chime, amask and arpt; alrmtime=altime; alrmdate=aldate; // update the alarm time and date rtcalrmset=0x8000|0x00000600; // re-enable the alarm, set alarm mask at once per day note: an alarm event is generated when arpt bits are = 0x00. /* the following code example will update the rtcc repeat alarm. assumes the interrupts are disabled. */ unsigned long altime=0x23352300; // set time to 23hr, 35 min, 23 sec unsigned long aldate=0x06111301; // set date to monday 13 nov 2006 // turn off the alarm, chime and alarm repeats; clear // the alarm mask while(rtcalrm&0x1000); // wait alrmsync to be off rtcalrmclr=0xcfff; // clear the alrmen, chime, amask and arpt; alrmtime=altime; alrmdate=aldate; // update the alarm time and date rtcalrmset=0x8000|0x0509; // re-enable the alarm, set alarm mask at once per hour // for 10 times repeat
pic32mx3xx/4xx ds61143e-page 482 preliminary ? 2008 microchip technology inc. 21.3.4 indefinite alarm an indefinite alarm can be generated by configuring the chime bit (rtcalrm<14>) = 1 ; arpt can be any value. once the alarm is enabled and an alarm event occurs, the arpt count is decremented by one. arpt rolls over from 0x00 to 0xff and continues to decre- ment on each alarm event indefinitely. the alrmen bit is never automatically cleared in hardware. the user must clear this bit to disable the indefinite alarm. it is recommended to read and verify the alarm sync bit, alrmsync (rtcalrm<12>) = 0 , before performing the following configuration: ? disable alarm ? alrmen (rtcalrm<15>) = 0 . ? enable chime ? chime (rtcalrm<14>) = 1 . ? configure alarm repeat counter ? arpt (rtcalrm<7:0>) = 0 to 256. ? configure alarm date and time ? load alrmdate and alrmtime registers with the desired alarm date/time values. ? configure mask ? load the desired amask value. ? enable alarm ? alrmen (rtcalrm<15>) = 0 . refer to example 21-6. example 21-6: configuring the rtcc for indefinite alarm 21.4 rtcc clock source the rtcc module is intended to be clocked by an external real-time clock crystal that is oscillating at 32.768 khz. to allow the rtcc to be clocked by an external 32.768 khz crystal, the soscen bit (osccon<1>) must be set (see section 4.0 ?oscilla- tors? ) or the fsoscen (devcfg1<5>) configuration bit must be programmed to ? 1 ?. this is the only bit outside of the rtcc module with which the user must be concerned of for enabling the rtcc. the status bit, soscrdy (osccon<22>), can be used to check that the secondary oscillator is running. note: an alarm event is generated when the arpt are = 0x00. /* the following code example will update the rtcc indefinite alarm. assumes the interrupts are disabled. */ unsigned long altime=0x23352300; // set time to 23hr, 35 min, 23 sec unsigned long aldate=0x06111301; // set date to monday 13 nov 2006 // turn off the alarm, chime and alarm repeats; clear // the alarm mask while(rtcalrm&0x1000); // wait alrmsync to be off rtcalrmclr=0xcfff; // clear alrmen, chime, amask, arpt; alrmtime=altime; alrmdate=aldate; // update the alarm time and date rtcalrmset=0xc600; // re-enable the alarm, set alarm mask at once per // hour, enable chime note: the rtcc does not have an exclusive access to use the sosc oscillator. this oscillator may be used by other peripher- als, such as the cpu as a low-power clock source or timer1. refer to the ? pic32mx3xx/4xx reference manual ? (ds61132) regarding the operation of the secondary low-power oscillator.
? 2008 microchip technology inc. preliminary ds61143e-page 483 pic32mx3xx/4xx 21.4.1 calibration the real-time crystal input can be calibrated using the periodic auto-adjust feature. when properly calibrated, the rtcc can provide an error of less than 0.66 sec- onds per month. calibration has the ability to eliminate an error of up to 260 ppm. the calibration is accomplished by finding the number of error clock pulses and writing this value into the cal field of the rtcccon register (rtccon<9:0>). this 10-bit signed value will either be added or subtracted from the rtcc timer, once every minute. refer to the steps below for rtcc calibration: 1. using another timer resource on the device, the user must find the error of the 32.768 khz crystal. 2. once the error is known, it must be converted to the number of error clock pulses per minute. equation 21-1: error clocks per minute 3. a) if the oscillator is faster than ideal (negative result from step 2), the cal bits register value needs to be negative. this causes the specified number of clock pulses to be subtracted from the timer counter, once every minute. b) if the oscillator is slower than ideal (positive result from step 2), the cal bits register value needs to be positive. this causes the specified number of clock pulses to be added to the timer counter, once every minute. 4. load the cal bits (rtccon<9:0>) with the cor- rect value. writes to the cal bits should only occur when the timer is turned off, or immediately after the rising edge of the seconds pulse (except when the seconds (rtctime<15:8>) field is ? 00 ? due to the possibility of the auto-adjust event). note: it is up to the user, to include in the error value, the initial error of the crystal drift, due to temperature and drift due to crystal aging. a write to the seconds bits resets the state of calibration (not its value). if an adjust- ment just occurred, it will occur again because of the minute roll over. (ideal frequency (32,758) ? measured frequency) * 60 = error clocks per minute
pic32mx3xx/4xx ds61143e-page 484 preliminary ? 2008 microchip technology inc. example 21-7: updating the rtcc calibration value 21.5 rtcc interrupts the rtcc alarm can be configured to generate an interrupt at every alarm event. refer to section 21.3 ?alarm mode? for details regarding the various alarm events. the rtcc module is enabled as a source of interrupts via the respective rtcc interrupt enable bit: ? rtccie (iec1<15>). the alarm interrupt is signalled by the corresponding rtcc interrupt flag bit: ? rtccif (ifs1<15>). this interrupt flag must be cleared in software. the interrupt priority level bits and interrupt subpriority level bits must be also be configured: ? rtccip<2:0> (ipc8<28:26>) ? rtccis<1:0> (ipc8<25:24>) in addition to enabling the rtcc interrupt, an interrupt service routine, isr, is required (see example 21-9). /* the following code example will update the rtcc calibration. */ int cal=0x3fd; // 10 bits adjustment, -3 in value if(rtccon&0x8000) { // rtcc is on unsigned intt0, t1; do { t0=rtctime; t1=rtctime; }while(t0!=t1); // read valid time value if((t0&0xff)==00) { // we?re at second 00, wait auto-adjust to be performed while(!(rtccon&0x2)); // wait until second half... } } rtcconclr=0x03ff0000; // clear the calibration rtcconset=cal; note: it is the user?s responsibility to clear the corresponding interrupt flag bit before returning from an isr.
? 2008 microchip technology inc. preliminary ds61143e-page 485 pic32mx3xx/4xx example 21-8: rtcc initialization with interrupts example 21-9: rtcc isr /* the following code example illustrates an rtcc initialization with interrupts enabled. when the rtcc alarm interrupt is generated, the cpu will jump to the vector assigned to rtcc interrupt. */ // assume rtcc write is enabled i.e. rtcwren (rtccon<3>) =1; iec1clr=0x00008000; // disable rtcc interrupts rtcconclr=0x8000; // turn off the rtcc while(rtccon&0x40); // wait for clock to be turned off ifs1clr=0x00008000; // clear rtcc existing event ipc8clr=0x1f000000; // clear the priority ipc8set=0x0d000000; // set ipl=3, subpriority 1 iec1set=0x00008000; // enable rtcc interrupts rtctime=0x16153300; // safe to update time to 16 hr, 15 min, 33 sec rtcdate=0x06102705; // update the date to friday 27 oct 2006 rtcalrmclr=0xcfff; // clear alrmen, chime, amask and arpt; alrmtime=0x16154300; // set alarm time to 16 hr, 15 min, 43 sec alrmdate=0x06102705; // set alarm date to friday 27 oct 2006 rtcalrmset=0x8000|0x00000600; // re-enable the alarm, set alarm mask at once per day rtcconset=0x8000; // turn on the rtcc while(!(rtccon&0x40)); // wait for clock to be turned on /* the following code example demonstrates a simple interrupt service routine for rtcc interrupts. the user?s code at this vector should perform any application specific operations and must clear the rtcc interrupt flag before exiting. */ void__isr(_rtcc_vector, ipl3) __rtccinterrupt(void) { // ... perform application specific operations // in response to the interrupt ifs1clr=0x00008000; // be sure to clear rtcc interrupt flag // before exiting the service routine. } note: the rtcc isr code example shows mplab ? c32 c compiler specific syntax. refer to your compiler manual regarding support for isrs.
pic32mx3xx/4xx ds61143e-page 486 preliminary ? 2008 microchip technology inc. 21.6 i/o pin control enabling the rtcc modules configures the i/o pin direction. when the rtcc module is enabled, config- ured and the output enabled, the i/o pin direction is properly configured as a digital output. the rtcc pin can be configured to toggle at every alarm or ?seconds? event. to enable the rtcc pin out- put, set the rtcoe bit (rtccon<0>) = 1 . to select the output to toggle on an alarm event, configure rtsecsel bit (rtccon<7>) = 0 . to select the output to toggle on every ?seconds? update, configure rtsecsel bit = 1 . table 21-3: i/o pin configurat ion for use with rtcc module required settings for module pin control io pin name required module control bit field tris (4) pin type buffer type description rtcc yes (1) on and rtcoe (2) rtsecsel = 1 xocmos rtcc seconds clock rtcc yes (1) on and rtcoe (2) rtsecsel = 0 and alrmen and piv (3) xocmos rtcc alarm pulse legend: cmos = cmos compatible input or output; st = schmitt trigger input with cmos levels; i = input; o=output note 1: the rtcc pin is only required when seconds clock or alarm pulse output is needed. otherwise, this pin can be used for general purpose io and require the user to set the corresponding tris control register bit. 2: the on (rtccon<15>) and rtcoe (rtccon<0>) bits are always required to validate the output function of the rtcc pin, either seconds clock or alarm pulse. 3: when rtsecsel (rtccon<7>) = 0 , the rtcc pin output is the alarm pulse. if the alrmen (rtcalrm<15>) = 0 , piv (rtcalrm<13>) selects the value at the rtcc pin. when the alrmen = 1 , the rtcc pin reflects the state of the alarm pulse. 4: the setting of the tris bit is irrelevant.
? 2008 microchip technology inc. preliminary ds61143e-page 487 pic32mx3xx/4xx 21.7 updating the time and date registers the following flowchart explains in detail the steps that have to be performed in order to update the rtctime and rtcdate registers. rtccon.on ? (alrmen && amask==halfsec && alrmsync)||rtcsync? write rtctime, rtcdate end start di updating the rtcctime, rtccdate registers logic flow yes no no write rtctime, rtcdate ei wait rtcc clock off rtcon.on=0; ei write rtctime, rtcdate wait rtcc clock off ? yes either, faster while(pulse); di pulse? ei ei pulse=alrmsync or pulse=rtcsync write rtctime, rtcdate yes no or, slower
pic32mx3xx/4xx ds61143e-page 488 preliminary ? 2008 microchip technology inc. 21.8 updating the alarm registers the following flowchart explains in detail the steps that have to be performed in order to update the alrmtime, alrmdate and rtcalrm registers. rtcc.on? wait rtcc clock off. write rtcalrm, alrmtime, alrmdate end start while(alrmsync); di alrmsync? write rtcalrm, alrmtime, alrmdate ei ei updating the alrmtime, alrmdate or rtcalrm registers logic flow yes no no yes
? 2008 microchip technology inc. preliminary ds61143e-page 489 pic32mx3xx/4xx 22.0 analog-digital converter the pic32mx3xx/4xx 10-bit analog-to-digital (a/d) converter (or adc) includes the following features: ? successive approximation register (sar) conversion ? up to 500 kilo samples per second (ksps) conversion speed ? up to 16 analog input pins ? external voltage reference input pins ? one unipolar, differential sample-and-hold amplifier (sha) ? automatic channel scan mode ? selectable conversion trigger source ? 16-word conversion result buffer ? selectable buffer fill modes ? eight conversion result format options ? operation during cpu sleep and idle modes a block diagram of the 10-bit adc is shown in figure 22-1. the 10-bit adc can have up to 16 analog input pins, designated an0-an15. in addition, there are two analog input pins for external voltage reference connections. these voltage reference inputs may be shared with other analog input pins and may be com- mon to other analog module references. the actual number of analog input pins and external voltage refer- ence input configuration will depend on the specific pic32mx device. refer to the device data sheet for further details. the analog inputs are connected through two multi- plexers (muxs) to one sha. the analog input muxs can be switched between two sets of analog inputs between conversions. unipolar differential conversions are possible on all channels, other than the pin used as the reference, using a reference input pin (see figure 22-1). the analog input scan mode sequentially converts user-specified channels. a control register specifies which analog input channels will be included in the scanning sequence. the 10-bit adc is connected to a 16-word result buffer. each 10-bit result is converted to one of eight, 32-bit output formats when it is read from the result buffer. note: this data sheet summarizes the features of the pic32mx3xx/4xx family of devices. it is not intended to be a comprehensive refer- ence source. refer to the ?pic32mx family reference manual? (ds61132) for a detailed description of this peripheral.
pic32mx3xx/4xx ds61143e-page 490 preliminary ? 2008 microchip technology inc. figure 22-1: 10-bit high-speed a/d converter block diagram comparator 10-bit sar conversion logic v ref + dac an12 an13 an14 an15 an8 an9 an10 an11 an4 an5 an6 an7 an0 an1 an2 an3 v ref - sample control sha av ss av dd adc1buf0: adc1buff ad1con1 ad1con2 ad1con3 ad1chs ad1pcfg ad1cssl control logic data input mux control conversion control pin config control internal data bus 32 v r + v r - mux a mux b v inh v inl v inh v inh v inl v inl v r + v r - v r select formatting + - ch0na ch0nb + ? + ?
? 2008 microchip technology inc. preliminary ds61143e-page 491 pic32mx3xx/4xx 22.1 control registers the adc module includes the following special func- tion registers (sfrs): the ad1con1, ad1con2 and ad1con3 registers control the operation of the adc module. ? ad1con1: adc control register 1 ad1con1clr, ad1con1set, ad1con1inv: atomic bit manipulation, write-only registers for ad1con1. ? ad1con2: adc control register 2 ad1con2clr, ad1con2set, ad1con2inv: atomic bit manipulation, write-only registers for ad1con2. ? ad1con3: adc control register 3 ad1con3clr, ad1con3set, ad1con3inv: atomic bit manipulation, write-only registers for ad1con3. the ad1chs register selects the input pins to be con- nected to the sha. ? ad1chs: adc input channel select register ad1chsclr, ad1chsset, ad1chsinv: atomic bit manipulation, write-only registers for ad1chs. the ad1pcfg register configures the analog input pins as analog inputs or as digital i/o. ? ad1pcfg: adc port configuration register ad1pcfgclr, ad1pcfgset, ad1pcfginv: atomic bit manipulation, write-only registers for ad1pcfg. the ad1cssl register selects inputs to be sequen- tially scanned. ? ad1cssl: adc input scan selection register ad1csslclr, ad1csslset, ad1csslinv: atomic bit manipulation, write-only registers for ad1cssl. the adc module also has the following associated bits for interrupt control: ? interrupt request flag status bit (ad1if) in ifs1: interrupt flag status register 1 ? interrupt enable control bit (ad1ie) in iec1: interrupt enable control register 1 ? interrupt priority control bits (ad1ip<2:0>) and (ad1is<1:0>) in ipc6: interrupt priority control register 6
pic32mx3xx/4xx ds61143e-page 492 preliminary ? 2008 microchip technology inc. 22.1.1 special function registers associated with the 10-bit adc table 22-1 provides a summary of all adc-related reg- isters, including their addresses and formats. corre- sponding registers appear after the summary, followed by a detailed description of each register. all unimplemented registers and/or bits within a register read as zeros. . table 22-1: adc sfr summary virtual address name bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 bf80_9000 ad1con1 31:24 ? ? ? ? ? ? ? ? 23:16 ? ? ? ? ? ? ? ? 15:8 on frz sidl ? ? form2 form1 form0 7:0 ssrc2 ssrc1 ssrc0 clrasam ? asam samp done bf80_9004 ad1con1clr 31:0 write clears selected bits in ad1con1, read yields undefined value bf80_9008 ad1con1set 31:0 write sets selected bits in ad1con1, read yields undefined value bf80_900c ad1con1inv 31:0 write inverts selected bits in ad1con1, read yields undefined value bf80_9010 ad1con2 31:24 ? ? ? ? ? ? ? ? 23:16 ? ? ? ? ? ? ? ? 15:8 vcfg2 vcfg1 vcfg0 offcal ? cscna ? ? 7:0 bufs ? smpi3 smpi2 smpi1 smpi0 bufm alts bf80_9014 ad1con2clr 31:0 write clears selected bits in ad1con2, read yields undefined value bf80_9018 ad1con2set 31:0 write sets selected bits in ad1con2, read yields undefined value bf80_901c ad1con2inv 31:0 write inverts selected bits in ad1con2, read yields undefined value bf80_9020 ad1con3 31:24 ? ? ? ? ? ? ? ? 23:16 ? ? ? ? ? ? ? ? 15:8 adrc ? ? samc4 samc3 samc2 samc1 samc0 7:0 adcs7 adcs6 adcs5 adcs4 adcs3 adcs2 adcs1 adcs0 bf80_9024 ad1con3clr 31:0 write clears selected bits in ad1con3, read yields undefined value bf80_9028 ad1con3set 31:0 write sets selected bits in ad1con3, read yields undefined value bf80_902c ad1con3inv 31:0 write inverts selected bits in ad1con3, read yields undefined value bf80_9040 ad1chs 31:24 ch0nb ? ? ? ch0sb3 ch0sb2 ch0sb1 ch0sb0 23:16 ch0na ? ? ? ch0sa3 ch0sa2 ch0sa1 ch0sa0 15:8 ? ? ? ? ? ? ? ? 7:0 ? ? ? ? ? ? ? ? bf80_9044 ad1chsclr 31:0 write clears selected bits in ad1chs, read yields undefined value bf80_9048 ad1chsset 31:0 write sets selected bits in ad1chs, read yields undefined value bf80_904c ad1chsinv 31:0 write inverts selected bits in ad1chs, read yields undefined value bf80_9060 ad1pcfg 31:24 ? ? ? ? ? ? ? ? 23:16 ? ? ? ? ? ? ? ? 15:8 pcfg15 pcfg14 pcfg13 pcfg 12 pcfg11 pcfg10 pcfg9 pcfg8 7:0 pcfg7 pcfg6 pcfg5 pcfg4 pcfg3 pcfg2 pcfg1 pcfg0 bf80_9064 ad1pcfgclr 31:0 write clears selected bits in ad1pcfg, read yields undefined value bf80_9068 ad1pcfgset 31:0 write sets selected bits in ad1pcfg, read yields undefined value bf80_906c ad1pcfginv 31:0 write inverts selected bits in ad1pcfg, read yields undefined value bf80_9050 ad1cssl 31:24 ? ? ? ? ? ? ? ? 23:16 ? ? ? ? ? ? ? ? 15:8 cssl15 cssl14 cssl13 cssl12 cssl11 cssl10 cssl9 cssl8 7:0 cssl7 cssl6 cssl5 cssl4 cssl3 cssl2 cssl1 cssl0
? 2008 microchip technology inc. preliminary ds61143e-page 493 pic32mx3xx/4xx table 22-2: adc interrupt register summary (1) bf80_9054 ad1csslclr 31:0 write clears selected bits in ad1cssl, read yields undefined value bf80_9058 ad1csslset 31:0 write sets selected bits in ad1cssl, read yields undefined value bf80_905c ad1csslinv 31:0 write inverts selected bits in ad1cssl, read yields undefined value bf80_9070 adc1buf0 31:0 adc result word 0 (adc1buf0<31:0>) bf80_9080 adc1buf1 31:0 adc result word 1 (adc1buf1<31:0>) bf80_9090 adc1buf2 31:0 adc result word 2 (adc1buf2<31:0>) bf80_90a0 adc1buf3 31:0 adc result word 3 (adc1buf3<31:0>) bf80_90b0 adc1buf4 31:0 adc result word 4 (adc1buf4<31:0>) bf80_90c0 adc1buf5 31:0 adc result word 5 (adc1buf5<31:0>) bf80_90d0 adc1buf6 31:0 adc result word 6 (adc1buf6<31:0>) bf80_90e0 adc1buf7 31:0 adc result word 7 (adc1buf7<31:0>) bf80_90f0 adc1buf8 31:0 adc result word 8 (adc1buf8<31:0>) bf80_9100 adc1buf9 31:0 adc result word 9 (adc1buf9<31:0>) bf80_9110 adc1bufa 31:0 adc result word a (adc1bufa<31:0>) bf80_9120 adc1bufb 31:0 adc result word b (adc1bufb<31:0>) bf80_9130 adc1bufc 31:0 adc result word c (adc1bufc<31:0>) bf80_9140 adc1bufd 31:0 adc result word d (adc1bufd<31:0>) bf80_9150 adc1bufe 31:0 adc result word e (adc1bufe<31:0>) bf80_9160 adc1buff 31:0 adc result word f (adc1buff<31:0>) table 22-1: adc sfr summary (continued) virtual address name bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 virtual address name bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 bf88_1040 ifs1 7:0 spi2rxif spi2txif spi2eif cmp2if cmp1if pmpif ad1if cnif bf88_1070 iec1 7:0 spi2rxie spi2txie spi2eie cmp2ie cmp1ie pmpie ad1ie cnie bf88_10f0 ipc6 31:24 ? ? ? ad1ip<2:0> ad1is<1:0> note 1: this summary table contains partial register definitions that only pertain to the adc peripheral. refer to the pic32mx family reference manual (ds61132) for a detailed description of these registers.
pic32mx3xx/4xx ds61143e-page 494 preliminary ? 2008 microchip technology inc. register 22-1: ad1con1: adc control register 1 r-x r-x r-x r-x r-x r-x r-x r-x ? ? ? ? ? ? ? ? bit 31 bit 24 r-x r-x r-x r-x r-x r-x r-x r-x ? ? ? ? ? ? ? ? bit 23 bit 16 r/w-0 r/w-0 r/w-0 r-x r-x r/w-0 r/w-0 r/w-0 on frz sidl ? ?form<2:0> bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r-x r/w-0 r/w-0 r/c-0 ssrc<2:0> clrasam ? asam samp done bit 7 bit 0 legend: r = readable bit w = writable bit p = programmable bit r = reserved bit u = unimplemented bit -n = bit value at por: (?0?, ?1?, x = unknown) bit 31-16 reserved: write ? 0 ?; ignore read bit 15 on: adc operating mode bit 1 = a/d converter module is operating 0 = a/d converter is off bit 14 frz: freeze in debug exception mode bit 1 = freeze operation when cpu enters debug exception mode 0 = continue operation when cpu enters debug exception mode note: frz is writable in debug exception mode only. it reads ? 0 ? in normal mode. bit 13 sidl: stop in idle mode bit 1 = discontinue module operation when device enters idle mode 0 = continue module operation in idle mode bit 12-11 reserved: write ? 0 ?; ignore read bit 10-8 form<2:0>: data output format bits 011 = signed fractional 16-bit (dout = 0000 0000 0000 0000 sddd dddd dd00 0000 ) 010 = fractional 16-bit (dout = 0000 0000 0000 0000 dddd dddd dd00 0000 ) 001 = signed integer 16-bit (dout = 0000 0000 0000 0000 ssss sssd dddd dddd ) 000 = integer 16-bit (dout = 0000 0000 0000 0000 0000 00dd dddd dddd ) 111 = signed fractional 32-bit (dout = sddd dddd dd00 0000 0000 0000 0000 ) 110 = fractional 32-bit (dout = dddd dddd dd00 0000 0000 0000 0000 0000 ) 101 = signed integer 32-bit (dout = ssss ssss ssss ssss ssss sssd dddd dddd ) 100 = integer 32-bit (dout = 0000 0000 0000 0000 0000 00dd dddd dddd ) bit 7-5 ssrc<2:0>: conversion trigger source select bits 111 = internal counter ends sampling and starts conversion (auto-convert) 110 = reserved 101 = reserved 100 = reserved 011 = reserved 010 = timer 3 period match ends sampling and starts conversion 001 = active transition on int0 pin ends sampling and starts conversion 000 = clearing samp bit ends sampling and starts conversion
? 2008 microchip technology inc. preliminary ds61143e-page 495 pic32mx3xx/4xx bit 4 clrasam: stop conversion sequence bit (when the first a/d converter interrupt is generated) 1 = stop conversions when the first adc interrupt is generated. hardware clears the asam bit when the adc interrupt is generated. 0 = normal operation, buffer contents will be overwritten by the next conversion sequence bit 3 reserved: write ? 0 ?; ignore read bit 2 asam: adc sample auto-start bit 1 = sampling begins immediately after last conversion completes; samp bit is automatically set. 0 = sampling begins when samp bit is set bit 1 samp: adc sample enable bit 1 = the adc sha is sampling 0 = the adc sample/hold amplifier is holding when asam = 0 , writing ? 1 ? to this bit starts sampling. when ssrc = 000 , writing ? 0 ? to this bit will end sampling and start conversion. bit 0 done: a/d conversion status bit 1 = a/d conversion is done 0 = a/d conversion is not done or has not started clearing this bit will not affect any operation in progress. note: the done bit is not persistent in automatic modes. it is cleared by hardware at the beginning of the next sample. register 22-1: ad1con1: adc control register 1 (continued)
pic32mx3xx/4xx ds61143e-page 496 preliminary ? 2008 microchip technology inc. register 22-2: ad1con2: adc control register 2 r-x r-x r-x r-x r-x r-x r-x r-x ? ? ? ? ? ? ? ? bit 31 bit 24 r-x r-x r-x r-x r-x r-x r-x r-x ? ? ? ? ? ? ? ? bit 23 bit 16 r/w-0 r/w-0 r/w-0 r/w-0 r-x r/w-0 r-x r-x vcfg<2:0> offcal ? cscna ? ? bit 15 bit 8 r-0 r-x r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 bufs ? smpi<3:0> bufm alts bit 7 bit 0 legend: r = readable bit w = writable bit p = programmable bit r = reserved bit u = unimplemented bit -n = bit value at por: (?0?, ?1?, x = unknown) bit 31-16 reserved: write ? 0 ?; ignore read bit 15-13 vcfg<2:0>: voltage reference configuration bits adc v r + adc v r - 000 av dd av ss 001 external v ref + pin av ss 010 av dd external v ref - pin 011 external v ref + pin external v ref - pin 1xx av dd av ss bit 12 offcal: input offset calibration mode select bit 1 = enable offset calibration mode v inh and v inl of the sha are connected to v r - 0 = disable offset calibration mode the inputs to the sha are controlled by ad1chs or ad1cssl bit 11 reserved: write ? 0 ?; ignore read cscna: scan input selections for ch0+ sha input for mux a input multiplexer setting bit 1 = scan inputs 0 = do not scan inputs bit 10 bit 9-8 reserved: write ? 0 ?; ignore read bit 7 bufs: buffer fill status bit only valid when bufm = 1 (adres split into 2 x 8-word buffers). 1 = adc is currently filling buffer 0x8-0xf, user should access data in 0x0-0x7 0 = adc is currently filling buffer 0x0-0x7, user should access data in 0x8-0xf bit 6 reserved: write ? 0 ?; ignore read
? 2008 microchip technology inc. preliminary ds61143e-page 497 pic32mx3xx/4xx bit 5-2 smpi<3:0>: sample/convert sequences per interrupt selection bits 1111 = interrupts at the completion of conversion for each 16 th sample/convert sequence 1110 = interrupts at the completion of conversion for each 15 th sample/convert sequence ..... 0001 = interrupts at the completion of conversion for each 2 nd sample/convert sequence 0000 = interrupts at the completion of conversion for each sample/convert sequence bit 1 bufm: adc result buffer mode select bit 1 = buffer configured as two 8-word buffers, adc1buf(7...0), adc1buf(15...8) 0 = buffer configured as one 16-word buffer adc1buf(15...0.) bit 0 alts: alternate input sample mode select bit 1 = uses mux a input multiplexer settings for first sample, then alternates between mux b and mux a input multiplexer settings for all subsequent samples 0 = always use mux a input multiplexer settings register 22-2: ad1con2: adc control register 2 (continued)
pic32mx3xx/4xx ds61143e-page 498 preliminary ? 2008 microchip technology inc. register 22-3: ad1con3: adc control register 3 r-x r-x r-x r-x r-x r-x r-x r-x ? ? ? ? ? ? ? ? bit 31 bit 24 r-x r-x r-x r-x r-x r-x r-x r-x ? ? ? ? ? ? ? ? bit 23 bit 16 r/w-0 r-x r-x r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 adrc ? ? samc<4:0> bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 adcs<7:0> bit 7 bit 0 legend: r = readable bit w = writable bit p = programmable bit r = reserved bit u = unimplemented bit -n = bit value at por: (?0?, ?1?, x = unknown) bit 31-16 reserved: write ? 0 ?; ignore read bit 15 adrc: adc conversion clock source bit 1 = adc internal rc clock 0 = clock derived from peripheral bus clock (pbclock) bit 14-13 reserved: write ? 0 ?; ignore read bit 12-8 samc<4:0>: auto-sample time bits 11111 = 31 t ad 00001 = 1 t ad 00000 = 0 t ad (not allowed) bit 7-0 adcs<7:0>: adc conversion clock select bits 11111111 = t pb ? (adcs<7:0> + 1) ? 2 = 512 ? t pb = t ad 00000001 = t pb ? (adcs<7:0> + 1) ? 2 = 4 ? t pb = t ad 00000000 = t pb ? (adcs<7:0> + 1) ? 2 = 2 ? t pb = t ad
? 2008 microchip technology inc. preliminary ds61143e-page 499 pic32mx3xx/4xx register 22-4: ad1chs: adc input select register r/w-0 r-x r-x r-x r/w-0 r/w-0 r/w-0 r/w-0 ch0nb ? ? ? ch0sb<3:0> bit 31 bit 24 r/w-0 r-x r-x r-x r/w-0 r/w-0 r/w-0 r/w-0 ch0na ? ? ? ch0sa<3:0> bit 23 bit 16 r-x r-x r-x r-x r-x r-x r-x r-x ? ? ? ? ? ? ? ? bit 15 bit 8 r-x r-x r-x r-x r-x r-x r-x r-x ? ? ? ? ? ? ? ? bit 7 bit 0 legend: r = readable bit w = writable bit p = programmable bit r = reserved bit u = unimplemented bit -n = bit value at por: (?0?, ?1?, x = unknown) bit 31 ch0nb: negative input select for mux b bit 1 = channel 0 negative input is an1 0 = channel 0 negative input is v r - bit 30-28 reserved: write ? 0 ?; ignore read bit 27-24 ch0sb<3:0>: positive input select for mux b bits 1111 = channel 0 positive input is an15 1110 = channel 0 positive input is an14 1101 = channel 0 positive input is an13 0001 = channel 0 positive input is an1 0000 = channel 0 positive input is an0 bit 23 ch0na: negative input select for mux a multiplexer setting bit (2) 1 = channel 0 negative input is an1 0 = channel 0 negative input is v r - bit 22-20 reserved: write ? 0 ?; ignore read bit 19-16 ch0sa<3:0>: positive input select for mux a multiplexer setting bits 1111 = channel 0 positive input is an15 1110 = channel 0 positive input is an14 1101 = channel 0 positive input is an13 0001 = channel 0 positive input is an1 0000 = channel 0 positive input is an0 bit 15-0 reserved: write ? 0 ?; ignore read
pic32mx3xx/4xx ds61143e-page 500 preliminary ? 2008 microchip technology inc. register 22-5: ad1pcfg: adc po rt configuration register r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 ? ? ? ? ? ? ? ? bit 31 bit 24 r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 ? ? ? ? ? ? ? ? bit 23 bit 16 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 pcfg15 pcfg14 pcfg13 pcfg12 pcfg11 pcfg10 pcfg9 pcfg8 bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w r/w-0 pcfg7 pcfg6 pcfg5 pcfg4 pcfg3 pcfg2 pcfg1 pcfg0 bit 7 bit 0 legend: r = readable bit w = writable bit p = programmable bit r = reserved bit u = unimplemented bit -n = bit value at por: (?0?, ?1?, x = unknown) bit 31-16 reserved: reserved for future use, maintain as ? 0 ? bit 15-0 pcfg<15:0>: analog input pin configuration control bits 1 = analog input pin in digital mode, port read input enabled, adc input multiplexer input for this analog input connected to avss 0 = analog input pin in analog mode, digital port read will return as a ? 1 ? without regard to the voltage on the pin, adc samples pin voltage
? 2008 microchip technology inc. preliminary ds61143e-page 501 pic32mx3xx/4xx register 22-6: ad1cssl: adc input scan select register r-x r-x r-x r-x r-x r-x r-x r-x ? ? ? ? ? ? ? ? bit 31 bit 24 r-x r-x r-x r-x r-x r-x r-x r-x ? ? ? ? ? ? ? ? bit 23 bit 16 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 cssl15 cssl14 cssl13 cssl12 cssl11 cssl10 cssl9 cssl8 bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w r/w-0 cssl7 cssl6 cssl5 cssl4 cssl3 cssl2 cssl1 cssl0 bit 7 bit 0 legend: r = readable bit w = writable bit p = programmable bit r = reserved bit u = unimplemented bit -n = bit value at por: (?0?, ?1?, x = unknown) bit 31-16 reserved: write ? 0 ? bit 15-0 cssl<15:0>: adc input pin scan selection bits 1 = select anx for input scan 0 = skip anx for input scan
pic32mx3xx/4xx ds61143e-page 502 preliminary ? 2008 microchip technology inc. 22.2 adc operation, terminology, and conversion sequence this section will describe the operation the a/d con- verter, the steps required to configure the converter, describe the special feature of the module, and provide examples of adc configuration with timing diagrams and charts showing the expected output of the converter. 22.2.1 overview of operation analog sampling consists of two steps: acquisition and conversion (see figure 22-2). during acquisition the analog input pin is connected to the sample and hold amplifier (sha). after the pin has been sampled for a sufficient period, the sample voltage is equivalent to the input, the pin is disconnected from the sha to provide a stable input voltage for the conversion process. the conversion process then converts the analog sample voltage to a binary representation. an overview of the adc is presented in figure 22-1. the 10-bit a/d converter has a single sha. the sha is connected to the analog input pins via the analog input muxs, mux a and mux b. the analog input muxs are controlled by the ad1chs register. there are two sets of mux control bits in the ad1chs register. these two sets of control bits allow the two different analog input to be independently controlled. the a/d converter can optionally switch between mux a and mux b configu- rations between conversions. the a/d converter can also optionally scan through a series of analog inputs using a single mux. acquisition time can be controlled manually or auto- matically. the acquisition time may be started manually by setting the samp bit (ad1con1<1>), and ended manually by clearing the samp in the user software. the acquisition time may be started automatically by the a/d converter hardware and ended automatically by a conversion trigger source. the acquisition time is set by the samc bits (ad1con3<12:8>). the sha has a minimum acquisition period. refer to the device data sheet for acquisition time specifications conversion time is the time required for the a/d con- verter to convert the voltage held by the sha. the a/d converter requires one adc clock cycle (t ad ) to con- vert each bit of the result, plus two additional clock cycles. therefore, a total of 12 t ad cycles are required to perform the complete conversion. when the conversion time is complete, the result is written into one of the 16 adc result registers (adc1buf0...adc1buff). the sum of the acquisition time and the a/d conver- sion time provides the total sample time (refer to figure 22-2). there are multiple input clock options for the a/d converter that are used to create the t ad clock. the user must select an input clock option that does not violate the minimum t ad specification. the sampling process can be performed once, period- ically, or based on a trigger as defined by the module configuration. figure 22-2: adc sample/conversion sequence acquisition time a/d conversion time adc total sample time sha is connected to the analog input pin for sampling. sha is disconnected from input and holds the signal. a/d conversion is started by the conversion trigger source. a/d conversion complete, result is written into the adc result buffer. optionally generate interrupt.
? 2008 microchip technology inc. preliminary ds61143e-page 503 pic32mx3xx/4xx the start time for sampling can be controlled in soft- ware by setting the samp control bit. the start of the sampling time can also be controlled automatically by the hardware. when the a/d converter operates in the auto-sample mode, the sha is reconnected to the analog input pin at the end of the conversion in the sample/convert sequence. the auto-sample function is controlled by the asam control bit (ad1con1<2>). the conversion trigger source ends the sampling time and begins an a/d conversion or a sample/convert sequence. the conversion trigger source is selected by the control bits ssrc<2:0> (ad1con1<7:5>). the conversion trigger can be taken from a variety of hard- ware sources, or can be controlled manually in soft- ware by clearing the samp control bit. one of the conversion trigger sources is an auto-conversion. the time between auto-conversions is set by a counter and the adc clock. the auto-sample mode and auto-con- version trigger can be used together to provide endless automatic conversions without software intervention. an interrupt may be generated at the end of each sam- ple sequence or multiple sample sequences as deter- mined by the value of the smpi<3:0> (ad1con2<5:2>). the number of sample sequences between interrupts can vary between 1 and 16. the user should note that the a/d conversion buffer holds the results of a single conversion sequence. the next sequence starts filling the buffer from the top even if the number of samples in the previous sequence was less than 16. the total number of conversion results between interrupts is the smpi value. the total number of conversions between interrupts cannot exceed the physical buffer length. 22.3 adc module configuration operation of the adc module is directed through bit settings in the appropriate registers. the following instructions summarize the actions and the settings. options and details for each configuration step are provided in subsequent sections. 1. to configure the adc module, perform the following steps: a-1. configure analog port pins in ad1pcfg<15:0>, as described in section 22.3.1 ?configuring analog port pins? . b-1. select the analog inputs to the adc muxs in ad1chs<32:0>, as described in section 22.3.2 ?selecting the analog inputs to the adc muxs? . c-1. select the format of the adc result using form<2:0> (ad1con1<10:8>), as described in section 22.3.3 ?selecting the format of the adc result? . c-2. select the sample clock source using ssrc<2:0> (ad1con1<7:5>), as described in section 22.3.3.1 ?selecting the sample clock source? . d-1. select the voltage reference source using vcfg<2:0> (ad1con2<15:13>), as described in section 22.3.6 ?selecting the voltage reference source? . d-2. select the scan mode using cscna (ad1con2<10>), as described in section 22.3.7 ?selecting the scan mode? . d-3. set the number of conversions per interrupt smpi<3:0> (ad1con2<5:2>), if interrupts are to be used, as described in section 22.3.8 ?setting the number of conver- sions per interrupt? . d-4. set buffer fill mode using bufm (ad1con2<1>), as described in section 22.3.9 ?buffer fill mode? . d-5. select the mux to be connected to the adc in alts (ad1con2<0>), as described in section 22.3.10 ?selecting the mux to be connected to the adc (alternating sam- ple mode)? . e-1. select the adc clock source using adrc (ad1con3<15>), as described in section 22.3.11 ?selecting the adc conversion clock source and prescaler? . e-2. select the sample time using samc<4:0> (ad1con3<12:8>), if auto-convert is to be used, as described in section 22.3.12 ?acquisition time considerations? . e-3. select the adc clock prescaler using adcs<7:0> (ad1con3<7:0>), as described in section 22.3.11 ?selecting the adc conversion clock source and prescaler? . f. turn on adc module using ad1con1<15>, as described in section 22.3.13 ?turning the adc on? . 2. to configure adc interrupt (if required). a-1. clear ad1if bit (ifs1<1>), as described in section 8.0 ?interrupts? . a-2. select adc interrupt priority ad1ip<2:0> (ipc<28:26>) and sub priority ad1is<1:0> (ipc<24:24>), as described in section 8.0 ?interrupts? , if interrupts are to be used. 3. start the conversion sequence by initiating sampling, as described in section 22.3.14 ?ini- tiating sampling? . note: steps a through e, above, can be per- formed in any order, but step f must be the final step in every case.
pic32mx3xx/4xx ds61143e-page 504 preliminary ? 2008 microchip technology inc. 22.3.1 configuring analog port pins the ad1pcfg register and the trisb register control the operation of the adc port pins. ad1pcfg specifies the configuration of device pins to be used as analog inputs. a pin is configured as an analog input when the corresponding pcfgn bit (ad1pcfg) = 0 . when the bit = 1 , the pin is set to digital control. when configured for analog input, the associated port i/o digital input buffer is disabled so it does not consume current. the ad1pcfg register is cleared at reset, causing the adc input pins to be configured for analog input by default at reset. tris registers control the digital function of the port pins. the port pins that are desired as analog inputs must have their corresponding tris bit set, specifying the pin as an input. if the i/o pin associated with an adc input is configured as an output, the tris bit is cleared and the ports digital output level (v oh or v ol ) will be converted. after a device reset, all tris bits are set. 22.3.2 selecting the analog inputs to the adc muxs the ad1chs register is used to select which analog input pin is connected to mux a and mux b. each mux has two inputs referred to as the positive and the negative input. the positive input to mux a is con- trolled by ch0sa<4:0> and the negative input is con- trolled by ch0na. the positive input for mux b is controlled by ch0sb<4:0> and the negative input is controlled by ch0nb. the positive input can be selected from any one of the available analog input pins. the negative input can be selected as the adc negative reference or an0. the use of an0 as the negative input allows the adc to be used in a unipolar differential mode. refer to the device data sheet for an0 input voltage restrictions when used as a negative reference. 22.3.3 selecting the format of the adc result the data in the adc result register can be read as one of eight formats. the format is controlled by form<2:0> (ad1con1<10:8>). the user can select from integer, signed integer, fractional or signed fractional as a 16-bit or 32-bit result. 22.3.3.1 selecting the sample clock source it is often desirable to synchronize the end of sampling and the start of conversion with some other time event. the adc module may use one of four sources as a conversion trigger. the selection of the conversion trig- ger source is controlled by the ssrc<2:0> (ad1con1<7:5>) bits. 22.3.3.2 manual conversion to configure the adc to end sampling and start a con- version when samp is cleared (= 0 ), ssrc is set to ? 000 ?. 22.3.3.3 timer compare trigger the adc is configured for this trigger mode by setting ssrc<2:0> = 010 . when a period match occurs for the 32-bit timer, tmr3/tmr2, or the 16-bit timer3, a special a/d converter trigger event signal is generated by timer3. 22.3.3.3.1 external int0 pin trigger to configure the adc to begin a conversion on an active transition on the int0 pin, ssrc<2:0> is set to ? 001 ?. the int0 pin may be programmed for either a rising edge input or a falling edge input to trigger the conversion process. 22.3.3.3.2 auto-convert the adc can be configured to automatically perform conversions at the rate selected by the auto-sample time bits, samc<4:0>. the adc is configured for this trigger mode by setting ssrc<2:0> = 111 . in this mode, the adc will perform continuous conversions on the selected channels. notes: when reading a port register that shares pins with the adc, any pin config- ured as an analog input reads as a ? 0 ? when the port latch is read. analog levels on any pin that is defined as a digital input (including the an15:an0 pins), but is not configured as an analog input, may cause the input buffer to con- sume current that is out of the device?s specification.
? 2008 microchip technology inc. preliminary ds61143e-page 505 pic32mx3xx/4xx 22.3.4 synchronizing adc operations to internal or external events the modes where an external event trigger pulse ends sampling and starts conversion (ssrc2:ssrc0 = 001 , 010 or 011 ) may be used in combination with auto-sampling (asam = 1 ) to cause the adc to synchronize the sample conversion events to the trigger pulse source. for example, where ssrc = 010 and asam = 1 , the adc will always end sampling and start conversions synchronously with the timer compare trigger event. the adc will have a sample conversion rate that corresponds to the timer comparison event rate. 22.3.5 selecting automatic or manual sampling sampling can be started manually or automatically when the previous conversion is complete. 22.3.5.1 manual clearing the asam (ad1con1<2>) bit disables the auto-sample mode. acquisition will begin when the samp (ad1con1<1>) bit is set by software. acquisi- tion will not resume until the samp bit is once again set. 22.3.5.2 automatic setting the asam (ad1con1<2>) bit enables the auto-sample mode. in this mode, the sampling will start automatically after the pervious sample has been converted. 22.3.6 selecting the voltage reference source the user can select the voltage reference for the adc module. the reference can be internal or external. the vcfg<2:0> control bits (ad1con2<15:13>) select the voltage reference for a/d conversions. the upper voltage reference (v r +) and the lower voltage reference (v r -) may be the internal av dd and av ss voltage rails, or the v ref + and v ref - input pins. 22.3.7 selecting the scan mode the adc module has the ability to scan through a selected vector of inputs. the cscna bit (ad1con2<10>) enables the mux a input to be scanned across a selected number of analog inputs. 22.3.7.1 scan mode enable scan mode is enabled by setting cscna (ad1con2<10>). when scan mode is enabled, the positive input of mux a is controlled by the contents of the ad1cssl register. each bit in the ad1cssl register corresponds to an analog input. bit 0 corre- sponds to an0, bit 1 corresponds to an1 and so on. if a particular bit in the ad1cssl register is ? 1 ?, the corresponding input is part of the scan sequence. 22.3.7.2 using scan and alternate modes together the scan and alternate modes may be combined to allow a vector of inputs to be scanned and a single input to be converted every other sample. this mode is enabled by setting the cscna bit = 1 , and setting the alts (ad1con2<0>) bit = 1 . the cscna bit enables the scan for mux a, and the ch0sb<3:0> (ad1chs<27:24>) and ch0nb (ad1chs<31>) are used to configure the inputs to mux b. scanning only applies to the mux a input selection. the mux b input selection, as specified by ch0sb<3:0>, will still select a single input. 22.3.8 setting the number of conversions per interrupt the smpi<3:0> bits (ad1con2<5:2>) select how many a/d conversions will take place before a cpu interrupt is generated. this also defines the number of locations that will be written in the result buffer stating with adc1buf0 (adc1buf0 or adc1buf8 for dual buffer mode). this can vary from 1 sample to 16 sam- ples (1 to 8 samples for dual buffer mode). after the interrupt is generated, the sampling sequence restarts; with the result of the first sample being written to the first buffer location. the data in the result registers will be overwritten by the next sampling sequence. the data in the result buffer must be read before the completion of the first sample after the interrupt is generated.
pic32mx3xx/4xx ds61143e-page 506 preliminary ? 2008 microchip technology inc. 22.3.9 buffer fill mode the buffer fill mode allows the output buffer to be used as a single, 16-word buffer or two, 8-word buffers. when bufm is ? 0 ?, the complete 16-word buffer is used for all conversion sequences. conversion results will be written sequentially in the buffer, starting at adc1buf0 until the number of samples as defined by smpi<3:0> (ad1con2<5:2>) is reached. the next conversion result will be written to adc1buf0 and the process repeats. if the adc interrupt is enabled, an interrupt will be generated when the number of samples in the buffer equals smpi<3:0>. when the bufm bit (ad1con2<1>) is ? 1 ?, the 16-word results buffer (adres) will be split into two 8-word groups. conversion results will be written sequentially into the first buffer starting at adc1buf0, bufs (ad1con2<7>) will be cleared, until the number of samples as defined by smpi<3:0> (ad1con2<5:2>) is reached. the adc interrupt flag will then be set. after the adc interrupt flag is set, the following result will be written sequentially to the second buffer, starting at adc1buf8 the next conversion result will be writ- ten to the second buffer; starting at adc1buf8, bufs (ad1con2<7>) will be set until the number of samples as defined by smpi<3:0> (ad1con2<5:2>) is reached. the adc interrupt flag will then be set. the process then restarts with bufs = 0 and the results being written to the first buffer. 22.3.10 selecting the mux to be connected to the adc (alternating sample mode) the adc has two input muxs that connect to the sha. these muxs are used to select which analog input is to be sampled. each of the muxs have a positive and a negative input. 22.3.10.1 single input selection the user may select one of up to 16 analog inputs, as determined by the number of analog channels on the device, as the positive input of the sha. the ch0sa<3:0> bits (ad1chs<19:16>) select the posi- tive analog input. the user may select either v r - or an1 as the negative input. the ch0na bit (ad1chs<23>) selects the ana- log input for the negative input of channel 0. using an1 as the negative input allows unipolar differential mea- surements. the alts bit (ad1con2<0>) must be clear for this mode of operation. 22.3.10.2 alternating input selections the alts bit causes the module to alternate between the two input muxs. the inputs specified by ch0sa<3:0> and ch0na are called the mux a inputs. the inputs specified by ch0sb<3:0> and ch0nb are called the mux b inputs. when alts is ? 1 ?, the module will alternate between the mux a inputs on one sample and the mux b inputs on the subsequent sample. when alts is ? 0 ?, only the inputs specified by ch0sa<3:0> and ch0na are selected for sampling. 22.3.11 selecting the adc conversion clock source and prescaler the adc module can use the internal rc oscillator or the pbclk as the conversion clock source. when the internal rc oscillator is used as the clock source, adrc (ad1con3<15>) = 1 , the t ad is the period of the oscillator, no prescaler are used. when using the internal oscillator the adc can continue to function in sleep and in idle. when the pbclk is used as the conversion clock source, adrc = 0 , the t ad is the period of the pbclk after the prescaler adcs<7:0> (ad1con3<7:0>) is applied. the a/d converter has a maximum rate at which con- versions may be completed. an analog module clock, t ad , controls the conversion timing. the a/d conver- sion requires 12 clock periods (12 t ad ). the period of the adc conversion clock is software selected using a 8-bit counter. there are 256 possible options for t ad , specified by the adcs<7:0> bits (ad1con3<7:0>). equation 22-3 gives the t ad value as a function of the adcs control bits and the device instruction cycle clock period, t cy . equation 22-3: adc conversion clock period for correct a/d conversions, the adc conversion clock (t ad ) must be selected to meet the minimum t ad time. t ad = 2 ? (t pb (aadcs + 1) adcs = (t ad /(2 ? t pb )) - 1
? 2008 microchip technology inc. preliminary ds61143e-page 507 pic32mx3xx/4xx equation 22-4: available sampling time, sequential sampling 22.3.12 acquisition time considerations different acquisition/conversion sequences provide dif- ferent times for the sample-and-hold channel to acquire the analog signal. the user must ensure the acquisition time meets the sampling requirements. when ssrc<2:0> (ad1con1<7:5>) = 111 , the con- version trigger is under adc clock control. the samc<4:0> bits (ad1con3<12:8>) select the number of t ad clock cycles between the start of acquisition and the start of conversion. this trigger option provides the fastest conversion rates on multiple channels. after the start of acquisition, the module will count a number of t ad clocks specified by the samc bits. 22.3.13 turning the adc on when the on bit (ad1con1<15>) is ? 1 ?, the module is in active mode and is fully powered and functional. when on is ? 0 ?, the module is disabled. the digital and analog portions of the circuit are turned off for maxi- mum current savings. in order to return to the active mode from the off mode, the user must wait for the analog stages to stabilize. for the stabilization time, refer to the electrical characteristics section of the device data sheet. 22.3.14 initiating sampling 22.3.14.1 manual mode in manual sampling, a acquisition is started by writing a ? 1 ? to the samp (ad1con1<1>) bit. software must manually manage the start and end of the acquisition period by setting samp and then clearing samp after the desired acquisition period has elapsed. 22.3.14.2 auto-sample mode in auto-sample mode, the sampling process is started by writing a ? 1 ? to the asam (ad1con1<2>) bit. in auto-sample mode, the acquisition period is defined by adcs<7:0> (ad1con3<7:0>). acquisition is automat- ically started after a conversion is completed. auto- sample mode can be used with any trigger source other than manual. t smp = trigger pulse interval (t seq ) ? conversion time (t conv ) t smp =t seq ? t conv note: t seq is the trigger pulse interval time. note: writing to adc control bits other than on (ad1con1<15>), samp (ad1con1<1>), and done (ad1con1<0>) is not recom- mended while the a/d converter is running.
pic32mx3xx/4xx ds61143e-page 508 preliminary ? 2008 microchip technology inc. 22.3.15 500 ksps configuration guideline the configuration for 500 ksps operation is dependent on whether a single input pin or multiple pins will be sampled. 22.3.15.1 500 ksps configuration procedure the following configuration items are required to achieve a 500 ksps conversion rate. ? connect external v ref + and v ref - pins following the recommended circuit shown in figure 22-4. ? set ssrc<2:0> = 111 in the ad1con1 register to enable the auto convert option. ? enable automatic sampling by setting the asam control bit in the ad1con1 register. ? configure the adc clock period by writing an adcs value = 2 to the adcs<5:0> control bits in the ad1con3 register. use the following formula: figure 22-3: 500 ksps sample rate calculations ? configure the sampling time to be 2 t ad by writing: samc<4:0> = 00010 . system clock of 80mhz and pbdiv = 2 period calculate number clocks required: sample clocks (see table 22-3) therefore sampc convert adc clock periods (see section 22.2.1 ) sample clocks + convert clocks = adclks calculate adc clock period: (adc clock period) (desired adc clock divisor) calculate desired adcs value from result results in 1.85 closest higher value closest lower value calculate actual sample rate: adc clock divisor ? adclks ? tpb using adcs = 1: (exceeds device specifications) using adcs = 2: results = 476 ksps conclusion: select adcs of 2 tpb 1 80 mhz ------------------ ?? ?? 2 ? 25 ns == 1 500 -------- - ksps 2 us = 2 = 1 = 12 = 14 = 2 us 14 -------- - 143 ns tad == 143 ns 1 40 mhz ------------------ ?? ?? ----------------------- - 5.71 = 5.71 adcs 1 + () 2 ? = 2 = 1 1 adcs 1 + () 2 ? () 14 ? () 25 ns ) ? -------------------------------------------------------------------------------- - 714 ksps =
? 2008 microchip technology inc. preliminary ds61143e-page 509 pic32mx3xx/4xx figure 22-4: converting 1 channel at 400 ksps, auto-sample start, 2 tad sampling time 22.4 miscellaneous adc functions the following section describes bits not covered in the previous section. 22.4.1 aborting sampling clearing the samp (ad1con1<1>) bit while in manual sample mode will terminate sampling, but may also start a conversion if ssrc (ad1con1<7:5>) = 000 . clearing the asam (ad1con1<2>) bit while in auto- sample mode will not terminate an ongoing acquire/convert sequence, however, sampling will not automatically resume after the current sample is converted. 22.4.2 aborting a conversion clearing the on (ad1con1<15>) bit during a conver- sion will abort the current conversion. the adc result register will not be updated with the partially com- pleted a/d conversion sample. that is, the correspond- ing result buffer location will continue to contain the value of the last completed conversion (or the last value written to the buffer). 22.4.3 buffer fill status when the conversion result buffer is split using the bufm control bit, the bufs status bit (ad1con2<7>) indicates which half of the buffer the a/d converter is currently filling. if bufs = 0 , then the a/d converter is filling adc1buf0-adc1buf7 and the user software should read conversion values from adc1buf8- adc1buff. if bufs = 1 , the situation is reversed and the user software should read conversion values from adc1buf0-adc1buf7. 22.4.4 offset calibration the adc module provides a method of measuring the internal offset error. after this offset error is measured, it can be subtracted, in software, from the result of an a/d conversion. use the following steps to perform an offset measurement: 1. configure the a/d converter in the same manner as it will be used in the application. 2. set the offcal bit (ad1con2<12>). this overrides the input selections and connects the sample and hold inputs to avss. 3. if auto-sample is used set the clrasam bit (ad1con1<4>) to force conversions. 4. enable the a/d converter and perform a conver- sion. the result that is written to the adc result buffer is the internal offset error. 5. clear the offcal (ad2con<12>) bit to return the a/d converter to normal operation. t conv = 12 t ad t conv = 12 t ad t samp = 2 t ad t samp = 2 t ad adclk samp done adc1buf0 adc1buf1 instruction execution set ad1con1,asam note: only positive adc offsets can be measured with this method.
pic32mx3xx/4xx ds61143e-page 510 preliminary ? 2008 microchip technology inc. 22.4.5 terminate conversion sequence after an interrupt the clrasam bit provides a method to terminate auto-sample after the first sequence is completed. set- ting the clrasam and starting an auto-sample sequence will cause the a/d converter to complete one auto-sample sequence (the number of samples as defined by smpi<3:0> (ad1con2<5:2>)). hardware will clear asam (ad1con1<2>) and set the interrupt flag. this will stop the sampling process to allow inspection of the result buffer without results being overwritten by the next automatic conversion sequence. the clrasam must be cleared by software to disable this mode. 22.4.6 conversion sequence examples the following configuration examples show the adc operation in different sampling and buffering configura- tions. in each example, setting the asam bit starts automatic sampling. a conversion trigger ends sam- pling and starts conversion. 22.4.7 manual conversion control when ssrc<2:0> = 000 , the conversion trigger is under software control. clearing the samp bit (ad1con1<1>) starts the conversion sequence. see example 22-1 for sample code to manually control the sampling of a single channel. example 22-1: converting 1 channel, manual sample start, manual conversion start code note: disabling interrupts or masking the adc interrupt has no effect on the operation of the clrasam bit. ad1pcfg = ~(1 << 5); // portb = digital; rb5 = analog ad1con1 = 0x0000; // samp bit = 0 ends sampling ... // and starts converting ad1chs = 5 << 16; // connect rb5/an5 as ch0 input .. ad1cssl = 0; ad1con3 = 0x0002; // manual sample, tad = 6 tpb ad1con2 = 0; ad1con1set = 0x8000; // turn adc on while (1) // repeat continuously { ad1con1set = 0x0002; // start sampling ... delaynmsec(100); // for 100 ms ad1con1clr = 0x0002; // start converting while (!(ad1con1 & 0x0001)); // conversion done? adcvalue = adc1buf0; // yes then get adc value }
? 2008 microchip technology inc. preliminary ds61143e-page 511 pic32mx3xx/4xx 22.4.8 automatic acquisition automatic acquisition control is enabled by setting the asam (ad1con1<2>) bit. setting the asam bit initi- ates automatic acquisition, and clearing the samp (ad1con1<1>) bit terminates sampling and starts conversion. after the conversion completes, the mod- ule will automatically return to an acquisition state. the samp bit is automatically set at the start of the acquisi- tion interval. the user software must time the clearing of the samp bit to ensure adequate acquisition time of the input signal, understanding that the time between clearing of the samp bit includes the conversion time as well as the acquisition time. see example 22-2 for a code example. example 22-2: converting 1 channel, automatic sample start, manual conversion start code 22.4.9 clocked conversion trigger when ssrc<2:0> = 111 , the conversion trigger is under adc clock control. the samc bits (ad1con3<4:0>) select the number of t ad clock cycles between the start of acquisition and the start of conversion. this trigger option provides the fastest conversion rates on multiple channels. after the start of acquisition, the module will count a number of t ad clocks specified by the samc bits. equation 22-1: clocked conversion trigger time samc must always be programmed for at least one clock cycle. see example 22-3 for a code example. ad1pcfg = ~(1 << 5); // all portb = digital but rb5 = analog ad1con1 = 0x0004; // asam bit = 1 implies acquisition .. // starts immediately after last conversion is done ad1chs = 5 << 16; // connect rb5/an5 as ch0 input ad1cssl = 0; ad1con2 = 0; ad1con3 = 0x0002; // sample time manual, tad = 6 tpb ad1con1set = 0x8000; // turn adc on while (1) // repeat continuously { delaynmsec(100); // sample for 100 ms ad1con1clr = 0x0002; // start converting while (!(ad1con1 & 0x0001)); // conversion done? adcvalue = adc1buf0; // yes then get adc value } // repeat t smp = samc <4:0>* t ad
pic32mx3xx/4xx ds61143e-page 512 preliminary ? 2008 microchip technology inc. example 22-3: converting 1 channel, manual sample start, tad-based conversion start code ad1pcfg = ~(1 << 5); // all portb = digital but rb5 = analog ad1con1 = 0x00e0; // ssrc bit = 111 implies internal // counter ends sampling and starts converting. ad1chs = 5 << 16; // connect rb5/an5 as ch0 input ad1cssl = 0; ad1con3 = 0x1f02; // sample time = 31tad ad1con2 = 0; ad1con1set = 0x8000; // turn adc on while (1) // repeat continuously { ad1con1set = 0x0002; // start sampling then // after 31tad go to conversion while (!(ad1con1 & 0x0001)); // conversion done? adcvalue = adc1buf0; // yes then get adc value } // repeat
? 2008 microchip technology inc. preliminary ds61143e-page 513 pic32mx3xx/4xx 22.4.10 free-running sample conversion sequence the auto-convert conversion trigger mode (ssrc = 111 ) in combination with the automatic sam- pling start mode (asam = 1 ), allows the adc module to schedule acquisition/conversion sequences with no intervention by the user or other device resources. this ?clocked? mode allows continuous data collection after module initialization. see example 22-4 for a code example. example 22-4: converting 1 channel, aut o-sample start, auto-convert code 22.4.11 sampling a single channel multiple times in this case, one adc input, an0, will be acquired and converted. the results are stored in the adc1buf buf- fer. this process repeats 15 times until the buffer is full, and then the module generates an interrupt. then entire process repeats. with alts (ad1con2<0>) clear, only the mux a inputs are active. the ch0sa (ad1chs<19:16>) bits and ch0na (ad1chs<23>) bit are specified (an0- vref-) as the input to the sample/hold channel. other input selection bits are not used. 22.4.12 example: a/d conversions while scanning through analog inputs a typical setup might include all available analog input channels to be sampled and converted. the cscna (ad1con2<10>) bit specifies scanning of the adc inputs. other conditions are similar to the previous example (see section 22.4.11 ?sampling a single channel multiple times? ). initially, the an0 input is acquired and converted. the result is stored in the adc1buf buffer. then the an1 input is acquired and converted. this process of scan- ning the inputs repeats 16 times until the buffer is full and then the module generates an interrupt. then the entire process repeats. ad1pcfg = ~(1 << 5); // all portb = digital but rb5 = analog ad1con1 = 0x00e0; // ssrc bit = 111 internal // counter ends sampling and starts // converting. ad1chs = 5 << 16; // connect rb5/an5 as ch0 input // in this example rb2/an2 is the input ad1cssl = 0; ad1con3 = 0x0f00; // sample time = 15 tad ad1con2 = 0x0004; // interrupt after every 2 samples ad1con1set = 0x8000; // turn adc on ad1con1set = 0x0004; // auto start sampling while (1) // repeat continuously { while (!ifs1 & 0x0002); // poll for interrupt // flag for conversion done ifs1clr = 0x0002; // clear adc interrupt flag // result of conversions is available in adc1buf0 // and adc1buf1 }
pic32mx3xx/4xx ds61143e-page 514 preliminary ? 2008 microchip technology inc. 22.4.12.1 example: using dual 8-word buffers to enable the dual 8-word buffers and alternating the buffer fill, set the bufm (ad1con2<1>) bit. the bufm setting does not affect other operational parameters. first, the conversion sequence starts filling the buffer at adc1buf0 (buffer location 0 x 0). after the first inter- rupt occurs, the buffer begins to fill at adc1buf8 (buf- fer location 0 x 8). the bufs (ad1con2<7>) bit is alternately set and cleared after each interrupt to show which buffer is being filled. in this example, three ana- log inputs are sampled and an interrupt occurs after every third sample. 22.4.12.2 example: using alternating mux a, mux b input selections setting the alts (ad1con2<0>) bit enables alternat- ing input selections. the first sample uses the mux a inputs specified by the ch0sa (ad1chs<19:16>) and ch0na (ad1chs<23>) bits. the next sample uses the mux b inputs specified by the ch0sb (ad1chs<27:24>) and ch0nb (ad1chs<31>) bits. in the following example, one of the mux b input specifications uses 2 analog inputs as a differential source to the sample/hold. this example also demonstrates use of the dual 8-word buffers. an interrupt occurs after every 4th sample, which results in filling 4-words into the buffer on each interrupt. 22.4.12.3 example: converting three analog inputs using alternating sample mode and a scan list it is possible to sample by scanning through the input channels and alternate between mux a and mux b. when the alternating sample mode is selected, the first input to be sampled will be the input selected for mux a, the second sample will be the input selected for mux b. then the process repeats. when scanning is combined with alternating input mode, the positive input to mux a is selected by the contents of the ad1cssl register, not ch0sa. for each sample that mux a is selected the next item in the scan list is sam- pled. the positive input to mux b is selected by ch0sb (ad1chs<27:24>). when asam (ad1con1<2>) is clear, sampling will not resume after conversion completion, but will occur when setting the samp (ad1con1<1>) bit. 22.5 initialization a simple initialization code example for the adc module is provided in example 22-5. in this particular configuration, all 16 analog input pins, an0-an15, are set up as analog inputs. operation in idle mode is disabled, output data is in unsigned frac- tional format, and av dd and av ss are used for v r + and v r -. the start of acquisition, as well as start of conver- sion (conversion trigger), are performed manually in software. the ch0 sha is used for conversions. scan- ning of inputs is disabled, and an interrupt occurs after every acquisition/convert sequence (1 conversion result). the adc conversion clock is t pb /2. since acquisition is started manually by setting the samp bit (ad1con1<1>) after each conversion is complete, the auto-sample time bits, samc<4:0> (ad1con3<12:8>), are ignored. moreover, since the start of conversion (i.e., end of acquisition) is also trig- gered manually, the samp bit needs to be cleared each time a new sample needs to be converted.
? 2008 microchip technology inc. preliminary ds61143e-page 515 pic32mx3xx/4xx example 22-5: adc initialization code example void __isr(_adc_vector, ipl7) adc_handler(void) { // interrupt handler unsigned long int result; result = adc1buf0; // read the result ifs1clr = 2; // clear adc conversion interrupt flag } int main(void) { ad1pcfg = ~(1 << 5); // configure rb5 as an analog input ad1con1 = (7 << 5) | 4; //configure sample clock source and trigger mode // integer format, automatic conversion trigger, // automatic start of sampling, no operation in idle mode. ad1con2 = 0x0000; // configure adc voltage reference // and buffer fill modes. // vref from avdd and avss,inputs are not scanned, // interrupt every sample ad1con3 = (31 << 8) | 0xff; // configure adc conversion clock // sample for 31 tad, tad = tpb / 512 ad1chs = 5 << 16; // configure input channels, // ch0+ input is an0. cho- input is vrefl (avss) ad1cssl = 0x0000; // no inputs are scanned. // note: contents of ad1cssl are ignored when cscna = 0 ipc6clr = 0x1f << 24; // clear the adc interrupt priority bits ipc6set = (0x07 << 26) | (1 << 24); // configure adc interrupt priority bits // priority = 3, sub-priority = 1 intenablesystemmultivectoredint(); // enable system interrupts ifs1clr = 2; // clear adc conversion interrupt iec1set = 2; // enable adc conversion interrupt ad1con1set = 0x8000; // turn on the adc module while(1) {} } // main
pic32mx3xx/4xx ds61143e-page 516 preliminary ? 2008 microchip technology inc. 22.6 i/o pin control the pins used for analog input can also be used for dig- ital i/o. configuring a pin for analog input requires three steps. any digital peripherals that share the desired pin must be disabled. the pin must be configured as a dig- ital input, by setting the corresponding tris bit to a ? 1 ? to disable the output driver. then, the pin must be placed in analog mode by setting the corresponding bit in the ad1pcfg register. table 22-3: pins associated with the adc module pin name module control controlling bit field pin type buffer type tris description an0 on ad1pcfg<0> a ? input analog input an1 on ad1pcfg<1> a ? input analog input an2 on ad1pcfg<2> a ? input analog input an3 on ad1pcfg<3> a ? input analog input an4 on ad1pcfg<4> a ? input analog input an5 on ad1pcfg<5> a ? input analog input an6 on ad1pcfg<6> a ? input analog input an7 on ad1pcfg<7> a ? input analog input an8 on ad1pcfg<8> a ? input analog input an9 on ad1pcfg<9> a ? input analog input an10 on ad1pcfg<10> a ? input analog input an11 on ad1pcfg<11> a ? input analog input an12 on ad1pcfg<12> a ? input analog input an13 on ad1pcfg<13> a ? input analog input an14 on ad1pcfg<14> a ? input analog input an15 on ad1pcfg<15> a ? input analog input v ref + on ad1con2<15:13> p ? ? positive voltage reference v ref - on ad1con2<15:13> p ? ? negative voltage reference legend: st = schmitt trigger input with cmos levels i = input o=output a=analog p=power
? 2008 microchip technology inc. preliminary ds61143e-page 517 pic32mx3xx/4xx figure 22-5: a/d converter voltage reference schematic v dd av dd av dd v dd r2 10 c2 0.1 f c1 0.01 f r1 10 c8 1 f v dd c7 0.1 f v dd c6 0.01 f v dd c5 1 f v dd c4 0.1 f v dd c3 0.01 f v dd v dd 92 94 93 91 90 89 88 87 86 85 84 83 82 81 80 79 78 20 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 65 64 63 62 61 60 59 56 45 44 43 42 41 40 39 28 29 30 31 32 33 34 35 36 37 38 17 18 19 21 22 95 1 76 77 72 71 70 69 68 67 66 75 74 73 58 57 24 23 25 96 98 97 99 27 46 47 48 49 55 54 53 52 51 100 50 26 v dd av ss av ss av ss v dd v dd 10k v dd 10 f av ss
pic32mx3xx/4xx ds61143e-page 518 preliminary ? 2008 microchip technology inc. 22.6.1 adc conversion speeds the pic32mx 10-bit a/d converter specifications per- mit a maximum 500 ksps sampling rate. table 22-4 summarizes the conversion speeds for the pic32mx 10-bit a/d converter and the required operating conditions. table 22-4: 10-bit conversion rate parameters pic32mx 10-bit a/d converter conversion rates adc speed t ad minimum sampling time min r s max v dd temperature adc channels configuration 500 ksps (1) 100 nsec 2 t ad 500 3.0v to 3.6v -40c to +85c up to 400 ksps 200 nsec 1 t ad 5.0 k 2.5v to 3.6v -40c to +125c up to 300 ksps 256.41 nsec 1 t ad 5.0 k 2.5v to 3.6v -40c to +125c note 1: external v ref - and v ref + pins must be used for correct operation. v ref -v ref + adc anx sha ch x v ref -v ref + adc anx sha ch x anx or v ref - or av ss or av dd v ref -v ref + adc anx sha ch x anx or v ref - or av ss or av dd
? 2008 microchip technology inc. preliminary ds61143e-page 519 pic32mx3xx/4xx 22.6.2 adc sampling requirements the analog input model of the 10-bit a/d converter is shown in figure 22-6. the total acquisition time for the a/d conversion is a function of the internal amplifier settling time and the holding capacitor charge time. for the a/d converter to meet its specified accuracy, the charge holding capacitor (c hold ) must be allowed to fully charge to the voltage level on the analog input pin. the analog output source impedance (r s ), the interconnect impedance (r ic ) and the internal sam- pling switch (r ss ) impedance combine to directly affect the time required to charge the c hold . the combined impedance of the analog sources must therefore be small enough to fully charge the holding capacitor within the chosen sample time. to minimize the effects of pin leakage currents on the accuracy of the a/d con- verter, the maximum recommended source imped- ance, r s , is 5 k for the conversion rates of up to 400 ksps and a maximum of 500 for conversion rates of up to 500 ksps). after the analog input channel is selected (changed), this acquisition function must be completed prior to starting the conversion. the internal holding capacitor will be in a discharged state prior to each sample operation. at least 1 t ad time period should be allowed between conversions for the acquisition time. for more details, see the device electrical specifications. figure 22-6: 10-bit a/d converter analog input model c pin va rs anx v t = 0.6v v t = 0.6v i leakage r ic 250 sampling switch r ss c hold = dac capacitance v ss v dd = 4.4 pf 500 na note: c pin value depends on device package and is not tested. effect of c pin negligible if rs 5 k . r ss 3 k legend c pin = input capacitance v t = threshold voltage r ss = sampling switch resistance r ic = interconnect resistance r s = source resistance c hold = sample/hold capacitance (from dac) i leakage = leakage current at the pin due to various junctions
pic32mx3xx/4xx ds61143e-page 520 preliminary ? 2008 microchip technology inc. notes:
? 2008 microchip technology inc. preliminary ds61143e-page 521 pic32mx3xx/4xx 23.0 power saving this section describes power saving for the pic32mx3xx/4xx. the pic32mx devices offer a total of nine methods and modes that are organized into two categories that allow the user to balance power con- sumption with device performance. in all of the meth- ods and modes described in this section, power saving is controlled by software. 23.1 power saving with cpu running when the cpu is running, power consumption can be controlled by reducing the cpu clock frequency, lower- ing the pb clk , and by individually disabling modules. these methods are grouped into the following catego- ries: ? frc run mode: the cpu is clocked from the frc clock source with or without postscalers. ? lprc run mode: the cpu is clocked from the lprc clock source. ? sosc run mode: the cpu is clocked from the sosc clock source. ? peripheral bus scaling mode: peripherals are clocked at programmable fraction of the cpu clock (sysclk). 23.2 cpu halted methods the device supports two power-saving modes, sleep and idle, both of which halt the clock to the cpu. these modes operate with all clock sources, as listed below: ? posc idle mode: the system clock is derived from the posc. the system clock source continues to operate. peripherals continue to operate, but can optionally be individually disabled. ? frc idle mode: the system clock is derived from the frc with or without postscalers. peripherals continue to operate, but can option- ally be individually disabled. ? sosc idle mode: the system clock is derived from the sosc. peripherals continue to operate, but can optionally be individually disabled. ? lprc idle mode: the system clock is derived from the lprc. peripherals continue to operate, but can option- ally be individually disabled. this is the lowest power mode for the device with a clock running. ? sleep mode: the cpu, the system clock source, and any peripherals that operate from the system clock source, are halted. some peripherals can operate in sleep using specific clock sources. this is the lowest power mode for the device. note: this data sheet summarizes the features of the pic32mx3xx/4xx family of devices. it is not intended to be a comprehensive refer- ence source. refer to the ?pic32mx family reference manual? (ds61132) for a detailed description of this peripheral.
pic32mx3xx/4xx ds61143e-page 522 preliminary ? 2008 microchip technology inc. 23.3 power-saving modes control registers power-saving modes control consists of the following special function registers (sfrs): ? osccon: control register for the oscillators module oscconclr, oscconset, oscconinv: atomic bit manipulation write-only registers for osccon ? wdtcon: control register for the watchdog timer module wdtconclr, wdtconset, wdtconinv: atomic bit manipulation write-only registers for wdtcon ? rcon: control register for the resets module rconclr, rconset, rconinv: atomic bit manipulation write-only registers for rcon the following table summarizes power-saving modes registers. corresponding registers appear after the summary, followed by a detailed description of each register. table 23-1: power-saving modes sfr summary virtual address name bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 bf80_f000 osccon 31:24 ? ? pllodiv<2:0> rcdiv<2:0> 23:16 ? soscrdy ? pbdiv<1:0> pllmult<2:0> 15:8 ?cosc<2:0> ? nosc<2:0> 7:0 clklock ulock lock slpen cf ufrcen soscen oswen bf80_f004 oscconclr 31:0 write clears selected bits in osccon, read yields undefined value bf80_f008 oscconset 31:0 write sets selected bits in osccon, read yields undefined value bf80_f00c oscconinv 31:0 write inverts selected bits in osccon, read yields undefined value bf80_0000 wdtcon 31:24 ? ? ? ? ? ? ? ? 23:16 ? ? ? ? ? ? ? ? 15:8 on ? ? ? ? ? ? ? 7:0 ? swdtps<4:0> ? wdtclr bf80_0004 wdtconclr 31:0 write clears selected bits in wdtcon; read yields undefined value bf80_0008 wdtconset 31:0 write sets selected bits in wdtcon; read yields undefined value bf80_000c wdtconinv 31:0 write inverts selected bits in wdtcon; read yields undefined value bf80_f600 rcon 31:24 ? ? ? ? ? ? ? ? 23:16 ? ? ? ? ? ? ? ? 15:8 ? ? ? ? ? ?cm vregs 7:0 extr swr ? wdto sleep idle bor por bf80_f604 rconclr 31:0 write clears selected bits in rcon; read yields undefined value bf80_f608 rconset 31:0 write sets selected bits in rcon; read yields undefined value bf80_f60c rconinv 31:0 write inverts selected bits in rcon; read yields undefined value
? 2008 microchip technology inc. preliminary ds61143e-page 523 pic32mx3xx/4xx register 23-1: osccon: os cillator control register r-x r-x r/w-x r/w-x r/w-x r/w-0 r/w-0 r/w-1 ? ? pllodiv<2:0> frcdiv<2:0> bit 31 bit 24 r-0 r-0 r-x r/w-x r/w-x r/w-x r/w-x r/w-x ? soscrdy ? pbdiv<1:0> pllmult<2:0> bit 23 bit 16 r-x r-0 r-0 r-0 r-x r/w-x r/w-x r/w-x ?cosc<2:0> ?nosc<2:0> bit 15 bit 8 r/w-0 r-0 r-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 clklock ulock lock slpen cf ufrcen soscen oswen bit 7 bit 0 legend: r = readable bit w = writable bit p = programmable bit r = reserved bit u = unimplemented bit -n = bit value at por: (?0?, ?1?, x = unknown) bit 29-27 pllodiv<2:0>: output divider for pll 111 = pll output divided by 256 110 = pll output divided by 64 101 = pll output divided by 32 100 = pll output divided by 16 011 = pll output divided by 8 010 = pll output divided by 4 001 = pll output divided by 2 000 = pll output divided by 1 note: on reset these bits are set to the value of the fpllodiv configuration bits (devcfg2<18:16>) bit 26-24 frcdiv<2:0>: fast internal rc clock divider bits 111 = frc divided by 256 110 = frc divided by 64 101 = frc divided by 32 100 = frc divided by 16 011 = frc divided by 8 010 = frc divided by 4 001 = frc divided by 2 (default setting) 000 = frc divided by 1 bit 23 reserved: write ? 0 ? bit 22 soscrdy: secondary oscillator ready indicator bit 1 = indicates that the secondary oscillator is running and is stable 0 = secondary oscillator is either turned off or is still warming up bit 21 reserved: write ? 0 ?; ignore read bit 20-19 pbdiv<1:0>: peripheral bus clock divisor 11 = pbclk is sysclk divided by 8 (default) 10 = pbclk is sysclk divided by 4 01 = pbclk is sysclk divided by 2 00 = pbclk is sysclk divided by 1 note: on reset these bits are set to the value of the fpbdiv configuration bits devcfg1<13:12>
pic32mx3xx/4xx ds61143e-page 524 preliminary ? 2008 microchip technology inc. bit 18-16 pllmult<2:0>: pll multiplier bits 111 = clock is multiplied by 24 110 = clock is multiplied by 21 101 = clock is multiplied by 20 100 = clock is multiplied by 19 011 = clock is multiplied by 18 010 = clock is multiplied by 17 001 = clock is multiplied by 16 000 = clock is multiplied by 15 note: on reset these bits are set to the value of the fpllmult configuration bits (devcfg2<6:4>). bit 15 reserved: write ? 0 ?; ignore read bit 14-12 cosc<2:0>: current oscillator selection bits 111 = fast internal rc oscillator divided by osccon bits 110 = fast internal rc oscillator divided by 16 101 = low-power internal rc oscillator (lprc) 100 = secondary oscillator (sosc) 011 = primary oscillator with pll module (xtpll, hspll or ecpll) 010 = primary oscillator (xt, hs or ec) 001 = fast rc oscillator with pll module via postscaler (frcpll) 000 = fast rc oscillator (frc) note: on reset these bits are set to the value of the fnosc configuration bits (devcfg1<2:0>). bit 11 reserved: write ? 0 ?; ignore read bit 10-8 nosc<2:0>: new oscillator selection bits 111 = fast internal rc oscillator divided by osccon bits 110 = fast internal rc oscillator divided by 16 101 = low-power internal rc oscillator (lprc) 100 = secondary oscillator (sosc) 011 = primary oscillator with pll module (xtpll, hspll or ecpll) 010 = primary oscillator (xt, hs or ec) 001 = fast internal rc oscillator with pll module via postscaler (frcpll) 000 = fast internal rc oscillator (frc) note: on reset these bits are set to the value of the fnosc configuration bits (devcfg1<2:0>). bit 7 clklock: clock selection lock enable bit if fscm is enabled (fcksm1 = 1 ): 1 = clock and pll selections are locked. 0 = clock and pll selections are not locked and may be modified if fscm is disabled (fcksm1 = 0 ): note: clock and pll selections are never locked and may be modified. bit 6 ulock: usb pll lock status bit 1 = indicates that the usb pll module is in lock or usb pll module start-up timer is satisfied 0 = indicates that the usb pll module is out of lock or usb pll module start-up timer is in progress or usb pll is disabled bit 5 lock: pll lock status bit 1 = pll module is in lock or pll module start-up timer is satisfied 0 = pll module is out of lock, pll start-up timer is running or pll is disabled bit 4 slpen: sleep mode enable bit 1 = device will enter sleep mode when a wait instruction is executed 0 = device will enter idle mode when a wait instruction is executed bit 3 cf: clock fail detect bit 1 = fscm (fail safe clock monitor) has detected a clock failure 0 = no clock failure has been detected register 23-1: osccon: oscillato r control register (continued)
? 2008 microchip technology inc. preliminary ds61143e-page 525 pic32mx3xx/4xx bit 2 ufrcen: usb frc clock enable bit 1 = enable frc as the clock source for the usb clock source 0 = use the primary oscillator or usb pll as the usb clock source bit 1 soscen: 32.768 khz secondary oscillator (sosc) enable bit 1 = enable secondary oscillator 0 = disable secondary oscillator note: on reset these bits are set to the value of the fsoscen configuration bit devcfg1<5> bit 0 oswen: oscillator switch enable bit 1 = initiate an oscillator switch to selection specified by nosc2:nosc0 bits 0 = oscillator switch is complete register 23-1: osccon: oscillato r control register (continued)
pic32mx3xx/4xx ds61143e-page 526 preliminary ? 2008 microchip technology inc. register 23-2: wdtcon: wat chdog timer control register r-x r-x r-x r-x r-x r-x r-x r-x ? ? ? ? ? ? ? ? bit 31 bit 24 r-x r-x r-x r-x r-x r-x r-x r-x ? ? ? ? ? ? ? ? bit 23 bit 16 r/w-0 r-x r-x r-x r-x r-x r-x r-x on ? ? ? ? ? ? ? bit 15 bit 8 r-x r-0 r-0 r-0 r-0 r-0 r-0 r/w-0 ? swdtps<4:0> ? wdtclr bit 7 bit 0 legend: r = readable bit w = writable bit p = programmable bit r = reserved bit u = unimplemented bit -n = bit value at por: (?0?, ?1?, x = unknown) bit 15 on: watchdog peripheral on bit 1 = watchdog peripheral is enabled. the status of other bits in the register are not affected by setting this bit. the lprc oscillator will not be disabled when entering sleep. 0 = watchdog peripheral is disabled and not drawing current. sfr modifications are allowed. the status of other bits in this register are not affected by clearing this bit.
? 2008 microchip technology inc. preliminary ds61143e-page 527 pic32mx3xx/4xx register 23-3: rcon: re sets control register r-x r-x r-x r-x r-x r-x r-x r-x ? ? ? ? ? ? ? ? bit 31 bit 24 r-x r-x r-x r-x r-x r-x r-x r-x ? ? ? ? ? ? ? ? bit 23 bit 16 r-x r-x r-x r-x r-x r-0 r/w-0 r/w-0 ? ? ? ? ? ? cm vregs bit 15 bit 8 r/w-0 r/w-0 r-x r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 extr swr ? wdto sleep idle bor por bit 7 bit 0 legend: r = readable bit w = writable bit p = programmable bit r = reserved bit u = unimplemented bit -n = bit value at por: (?0?, ?1?, x = unknown) bit 3 sleep: wake from sleep bit 1 = the device woke up from sleep mode 0 = the device did not wake from sleep mode note: must clear this bit to detect future wake-ups from sleep. bit 2 idle: wake from idle bit 1 = the device woke up from idle mode 0 = the device did not wake from idle mode note: must clear this bit to detect future wake-ups from idle.
pic32mx3xx/4xx ds61143e-page 528 preliminary ? 2008 microchip technology inc. 23.4 power-saving operation the purpose of all power saving is to reduce power consumption by reducing the device clock frequency. to achieve this, low-frequency clock sources can be selected. in addition, the peripherals and cpu can be halted or disabled to further reduce power consump- tion. 23.5 sleep mode sleep mode has the lowest power consumption of the device power-saving operating modes. the cpu and most peripherals are halted. select peripherals can continue to operate in sleep mode and can be used to wake the device from sleep. see the individ- ual peripheral module sections for descriptions of behavior in sleep. sleep mode includes the following characteristics: ? the cpu is halted. ? the system clock source is typically shut down. see section 23.5.1 ?oscillator shutdown in sleep mode? for specific information. ? there can be a wake-up delay based on the oscillator selection (refer to table 23-2). ? the fail-safe clock monitor (fscm) does not operate during sleep mode. ? the bor circuit, if enabled, remains operative during sleep mode. ? the wdt, if enabled, is not automatically cleared prior to entering sleep mode. ? some peripherals can continue to operate in sleep mode. these peripherals include i/o pins that detect a change in the input signal, wdt, adc, uart, and peripherals that use an external clock input or the internal lprc oscillator, e.g., rtcc and timer 1. ? i/o pins continue to sink or source current in the same manner as they do when the device is not in sleep. ? the usb module can override the disabling of the posc or frc. refer to the usb section for spe- cific details. ? some modules can be individually disabled by software prior to entering sleep in order to fur- ther reduce consumption. the processor will exit, or ?wake-up?, from sleep on one of the following events: ? on any interrupt from an enabled source that is operating in sleep. the interrupt priority must be greater than the current cpu priority. ? on any form of device reset. ? on a wdt time-out. see section 23.10 ?wake- up from sleep or idle on watchdog time- out (nmi)? . if the interrupt priority is lower than or equal to current priority, the cpu will remain halted, but the pbclk will start running and the device will enter into idle mode. refer example 23-1 for example code. note: in this data sheet, a distinction is made between a power mode as it is used in a specific module, and a power mode as it is used by the device, e.g., sleep mode of the comparator and sleep mode of the cpu. to indicate which type of power mode is intended, uppercase and lower- case letters (sleep, idle, debug) signify a module power mode, and all uppercase letters (sleep, idle, debug) signify a device power mode. note: there is no frz mode for this module.
? 2008 microchip technology inc. preliminary ds61143e-page 529 pic32mx3xx/4xx 23.5.1 oscillator shutdown in sleep mode the criteria for the device disabling the clock source in sleep are: the oscillator type, peripherals using the clock source, and (for select sources) the clock enable bit. ? if the cpu clock source is posc, it is turned off in sleep. see table 23-2 for applicable delays when waking from sleep. the usb module can override the disabling of the posc or frc. refer to the usb section for specific details. ? if the cpu clock source is frc, it is turned off in sleep. see table 23-2 for applicable delays when waking from sleep. the usb module can override the disabling of the posc or frc. refer to the usb section for specific details. ? if the cpu clock source is sosc, it will be turned off if the soscen bit is not set. see table 23-2 for applicable delays when waking from sleep. ? if the cpu clock source is lprc, it will be turned off if the clock source is not being used by a peripheral that will be operating in sleep, such as the wdt. see table 23-2 for applicable delays when waking from sleep. 23.5.2 clock selection on wake-up from sleep the processor will resume code execution and use the same clock source that was active when sleep mode was entered. the device is subject to a start-up delay if a crystal oscillator and/or pll is used as a clock source when the device exits sleep. 23.5.3 delay on wake-up from sleep the oscillator start-up and fail-safe clock monitor delays (if enabled) associated with waking up from sleep mode are shown in table 23-2. table 23-2: delay times for exit from sleep mode clock source oscillator delay fscm delay ec, extrc ? ? ec + pll t lock t fscm xt + pll t ost + t lock t fscm xt, hs, xtl t ost t fscm lp (off during sleep) t ost t fscm lp (on during sleep) ? ? frc, lprc ? ? note: refer to section 30.0 ?electrical char- acteristics? for t por , t fscm , and t lock specifications.
pic32mx3xx/4xx ds61143e-page 530 preliminary ? 2008 microchip technology inc. 23.5.4 wake-up from sleep mode with crystal oscillator or pll if the system clock source is derived from a crystal oscillator and/or the pll, then the oscillator start-up timer (ost) and/or pll lock times will be applied before the system clock source is made available to the device. as an exception to this rule, no oscillator delays are applied if the system clock source is the posc oscillator and it was running while in sleep mode. 23.5.5 fail-safe clock monitor delay and sleep mode the fail-safe clock monitor (fscm) does not operate while the device is in sleep. if the fscm is enabled it will resume operation when the device wakes from sleep. 23.5.6 slow oscillator start-up when an oscillator starts slowly, the ost and pll lock times may not have expired before fscm times out. if the fscm is enabled, then the device will detect this condition as a clock failure and a clock event trap will occur. the device will switch to the frc oscillator and the user can re-enable the crystal oscillator source in the clock failure interrupt service routine. if the fscm is not enabled, then the device will simply not start executing code until the clock is stable. from the user?s perspective, the device will appear to be in sleep until the oscillator clock has started. 23.5.6.1 the usb peripheral control of oscillators in sleep mode for devices with a usb peripheral, posc and frc will remain active in sleep if the usb module is not dis- abled prior to entering sleep. the oscillators remain- ing active will not stop the halting of the cpu or peripherals in sleep. example 23-1: put device in sleep, then wake with wdt note: in spite of the various delays applied the crystal oscillator (and pll) may not be up and running at the end of the t ost , or t lock delays. for proper operation the user must design the external oscillator circuit such that reliable oscillation will occur within the delay period. // code example to put the device in sleep and then wake the device // with the wdt oscconset = 0x10; // set power-saving mode to sleep wdtconclr = 0x0002; // disable wdt window mode wdtconset = 0x8000; // enable wdt // wdt timeout period is set in the device configuration while (1) { ... user code ... wdtconset = 0x01; // service the wdt asm volatile ( ?wait? );// put device in selected power-saving mode // code execution will resume here after wake ... user code ... } // the following code fragment is at the beginning of the ?c? start-up code if ( rcon & 0x18 ) { // the wdt caused a wake from sleep asm volatile ( ?eret? );// return from interrupt }
? 2008 microchip technology inc. preliminary ds61143e-page 531 pic32mx3xx/4xx 23.6 peripheral bus scaling method most of the peripherals on the device are clocked using the pbclk. the peripheral bus can be scaled relative to the sysclk to minimize the dynamic power con- sumed by the peripherals. the pbclk divisor is con- trolled by pbdiv<1:0> (osccon<20:19>), allowing sysclk-to-pbclk ratios of 1:1, 1:2, 1:4, and 1:8. all peripherals using pbclk are affected when the divisor is changed. peripherals such as the interrupt control- ler, dma, bus matrix, and prefetch cache are clocked directly from sysclk, as a result, they are not affected by pbclk divisor changes. most of the peripherals on the device are clocked using the pbclk. the peripheral bus can be scaled relative to the sysclk to minimize the dynamic power con- sumed by the peripherals. the pbclk divisor is con- trolled by pbdiv<1:0> (osccon<20:19>), allowing sysclk-to-pbclk ratios of 1:1, 1:2, 1:4, and 1:8. all peripherals using pbclk are affected when the divisor is changed. peripherals such as usb, interrupt con- troller, dma, bus matrix, and prefetch cache are clocked directly from sysclk, as a result, they are not affected by pbclk divisor changes changing the pbclk divisor affects: ? the cpu to peripheral access latency. the cpu has to wait for next pbclk edge for a read to complete. in 1:8 mode this results in a latency of one to seven sysclks. ? the power consumption of the peripherals. power consumption is directly proportional to the fre- quency at which the peripherals are clocked. the greater the divisor, the lower the power consumed by the peripherals. to minimize dynamic power the pb divisor should be chosen to run the peripherals at the lowest frequency that provides acceptable system performance. when selecting a pbclk divider, peripheral clock require- ments such as baud rate accuracy should be taken into account. for example, the uart peripheral may not be able to achieve all baud rate values at some pbclk divider depending on the sysclk value.
pic32mx3xx/4xx ds61143e-page 532 preliminary ? 2008 microchip technology inc. 23.6.1 dynamic peripheral bus scaling method the pb clk can be scaled dynamically, by software, to save additional power when the device is in a low activ- ity mode. the following issues need to be taken into account when scaling the pbclk: ? all the peripherals clocked from pbclk will scale at the same ratio, at the same time. this needs to be accounted in peripherals which need to main- tain a constant baud rate, or pulse period even in low-power modes. ? any communication through a peripheral on the peripheral bus that is in progress when the pbclk changes may cause a data or protocol error due to a frequency change during transmission or reception. the following steps are recommended if the user intends to scale the pbclk divisor dynamically: ? disable all communication peripherals whose baud rate will be affected. care should be taken to ensure that no communication is currently in prog- ress before disabling the peripherals as it may result in protocol errors. ? update the baud rate generator (brg) settings for peripherals as required for operation at the new pbclk frequency. ? change the peripheral bus ratio to the desired value. ? enable all communication peripherals whose baud rate were affected. example 23-2: changing the pb clock divisor note: modifying the peripheral baud rate is done by writing to the associated peripheral sfrs. to minimize latency, the peripher- als should be modified in the mode where the pbclk is running at its highest frequency. // code example to change the pbclk divisor // this example is for a device running at 20 mhz // make sure that there is no uart send/receive in progress ... user code ... u1brg = 0x81; // set baud rate for uart1 for 9600 ... user code ... syskey = 0x0; // write invalid key to force lock syskey = 0xaa996655; // write key1 to syskey syskey = 0x556699aa; // write key2 to syskey oscconclr = 0x3 << 19; // set pb divisor to minimum (1:1) syskey = 0x0; // write invalid key to force lock ... user code ... // change peripheral clock value u1brg = 0x0f; // set baud rate for uart1 for 9600 based on // new pb clock frequency syskey = 0x0; // write invalid key to force lock syskey = 0xaa996655; // write key1 to syskey syskey = 0x556699aa; // write key2 to syskey oscconset = 0x3 << 19; // set pb divisor to maximum (1:8) syskey = 0x0; // write invalid key to force lock // reset peripheral clock oscconclr = 0x3 << 19; // set pb divisor to minimum (1:1) u1brg = 0x81; // restore baud rate for uart1 to 9600 based // on new pb clock frequency
? 2008 microchip technology inc. preliminary ds61143e-page 533 pic32mx3xx/4xx 23.7 idle modes in the idle modes, the cpu is halted but the system clock (sysclk) source is still enabled. this allows peripherals to continue operation when the cpu is halted. peripherals can be individually configured to halt when entering idle by setting their respective sidl bit. latency when exiting idle mode is very low due to the cpu oscillator source remaining active. the device enters idle mode when the slpen (osc- con<4>) bit is clear and a wait instruction is executed. the processor will wake or exit from idle mode on the following events: ? on any interrupt event for which the interrupt source is enabled. the priority of the interrupt event must be greater than the current priority of cpu. if the priority of the interrupt event is lower than or equal to current priority of cpu, the cpu will remain halted and the device will remain in idle mode. ? on any source of device reset. ? on a wdt time-out interrupt. see section 23.10 ?wake-up from sleep or idle on watchdog time-out (nmi)? and section 26.0 ?watchdog timer? . notes: changing the pbclk divider ratio requires recalculation of peripheral timing. for example, assume the uart is config- ured for 9600 baud with a pb clock ratio of 1:1 and a posc of 8 mhz. when the pb clock divisor of 1:2 is used, the input fre- quency to the baud clock is cut in half; therefore, the baud rate is reduced to 1/2 its former value. due to numeric truncation in calculations (such as the baud rate divi- sor), the actual baud rate may be a tiny percentage different than expected. for this reason, any timing calculation required for a peripheral should be per- formed with the new pb clock frequency instead of scaling the previous value based on a change in pb divisor ratio. oscillator start-up and pll lock delays are applied when switching to a clock source that was disabled and that uses a crystal and/or the pll. for example, assume the clock source is switched from posc to lprc just prior to entering sleep in order to save power. no oscilla- tor start-up delay would be applied when exiting idle. however, when switching back to posc, the appropriate pll and or oscillator startup/lock delays would be applied.
pic32mx3xx/4xx ds61143e-page 534 preliminary ? 2008 microchip technology inc. example 23-3: placing device in idle and waking by adc event 23.8 interrupts there are two sources of interrupts that will wake the device from a power-saving mode: peripheral inter- rupts, and a non-maskable interrupt (nmi) generated by the wdt in power-saving mode. 23.9 wake-up from sleep or idle on peripheral interrupt any source of interrupt that is individually enabled using the corresponding ie control bit in the iecx reg- ister and is operational in the current power-saving mode will be able to wake-up the processor from sleep or idle mode. when the device wakes, one of two events will occur, based on the interrupt priority: ? if the assigned priority for the interrupt is less than, or equal to, the current cpu priority, the cpu will remain halted and the device enters, or remains in, idle mode. ? if the assigned priority level for the interrupt source is greater than the current cpu priority, the device will wake-up and the cpu will jump to the corresponding interrupt vector. upon completion of the isr, the cpu will start executing the next instruction after wait . the idle status bit (rcon<2>) is set upon wake-up from idle mode. the sleep status bit (rcon<3>) is set upon wake-up from sleep mode. // code example to put the device in idle and then wake the device when the adc completes // a conversion syskey = 0x0; // write invalid key to force lock syskey = 0xaa996655; // write key1 to syskey syskey = 0x556699aa; // write key2 to syskey oscconclr = 0x10; // set power-saving mode to idle syskey = 0x0; // write invalid key to force lock asm volatile ( ?wait? ); // put device in selected power-saving mode // code execution will resume here after wake and the isr is complete ... user code ... // interrupt handler void __isr(_adc_vector, ipl7) adc_handler(void) { // interrupt handler unsigned long int result; result = adc1buf0; // read the result ifs1clr = 2; // clear adc conversion interrupt flag } notes: a peripheral with an interrupt priority set- ting of zero cannot wake the device. any applicable oscillator start-up delays are applied before the cpu resumes code execution.
? 2008 microchip technology inc. preliminary ds61143e-page 535 pic32mx3xx/4xx 23.10 wake-up from sleep or idle on watchdog time-out (nmi) when the wdt times out in sleep or idle mode, an nmi is generated. the nmi causes the cpu code exe- cution to jump to the device reset vector. although the cpu executes the reset vector, it is not a device reset, peripherals and most cpu registers do not change their states. to detect a wake from a power-saving mode caused by wdt expiration, the wdto (rcon<4>), sleep (rcon<3>), and idle (rcon<2>) bits must be tested. if the wdto bit is ? 1 ? the event was due to a wdt time-out. the sleep and idle bits can then be tested to determine if the wdt event occurred in sleep or idle. to use a wdt time-out during sleep mode as a wake- up interrupt, a return from interrupt ( eret ) instruction must be used in the start-up code after the event was determined to be a wdt wake-up. this will cause code execution to continue from the instruction following the wait instruction that put the device in power-saving mode. see section 26.0 ?watchdog timer? for detailed information on the wdt operation. 23.11 interrupts coincident with power-saving instruction any peripheral interrupt that coincides with the execu- tion of a wait instruction will be held off until entry into sleep or idle mode has completed. the device will then wake-up from sleep or idle mode. 23.12 i/o pins associated with power-saving modes no device pins are associated with power-saving modes. note: any applicable oscillator start-up delays are applied before the cpu resumes code execution. note: if a peripheral interrupt and wdt event occur simultaneously, or in close proxim- ity, the nmi may not occur, due to the device being awakened by the peripheral interrupt. to avoid unexpected wdt reset in this scenario, the wdt is auto- matically cleared when the device awakens.
pic32mx3xx/4xx ds61143e-page 536 preliminary ? 2008 microchip technology inc. notes:
? 2008 microchip technology inc. preliminary ds61143e-page 537 pic32mx3xx/4xx 24.0 comparator the pic32mx3xx/4xx analog comparator module contains one or more comparator(s) that can be config- ured in a variety of ways. following are some of the key features of this module: ? selectable inputs available include: - analog inputs multiplexed with i/o pins - on-chip internal absolute voltage reference (iv ref ) - comparator voltage reference (cv ref ) ? outputs can be inverted ? selectable interrupt generation a block diagram of the comparator module is shown in figure 24-1. figure 24-1: compar ator block diagram note: this data sheet summarizes the features of the pic32mx3xx/4xx family of devices. it is not intended to be a comprehensive refer- ence source. refer to the ?pic32mx family reference manual? (ds61132) for a detailed description of this peripheral. c1 cv ref (3) c1in+ (2) c1in+ c1in- c1out cout (cm1con) cref cch<1:0> cpol coe on c2in+ iv ref (3) c1out (cmstat) c2 cv ref (3) c2in+ c2in+ c2in- c2out cout (cm2con) cref cpol coe on c1in+ iv ref (3) c2out (cmstat) comparator 2 comparator 1 cch<1:0> note 1: ivref is the internal 1.2v reference. 2: on usb variants, when usb is enabled, this pin is controlled by the usb module and therefore is not available as a comparator input. 3: internally connected.
pic32mx3xx/4xx ds61143e-page 538 preliminary ? 2008 microchip technology inc. 24.1 comparator control registers a comparator module consists of the following special function registers (sfrs): ? cmxcon: comparator control register ? cmxconclr, cmxconset, cmxconinv: atomic bit manipulation registers for cmxcon ? cmstat: comparator status registers ? cmstatclr, cmstatset, cmstatinv: atomic bit manipulation registers for cmstat the comparator module also has the following interrupt control registers: ? ifs1: interrupt flag status register ? iec: interrupt enable control register ? ipc7: interrupt priority control register table 24-1 provides brief summaries of all comparator related registers. corresponding registers appear after the summary, followed by a detailed description of each register. note: each pic32mx device variant may have one or more comparator modules. an ?x? used in the names of pins, control/status bits and registers denotes the particular module. refer to the specific device data sheets for more details. table 24-1: comparator sfrs summary virtual address name bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 bf80_a000 cm1con 31:24 ? ? ? ? ? ? ? ? 23:16 ? ? ? ? ? ? ? ? 15:8 on coe cpol ? ? ? ?cout 7:0 evpol<1:0> ? cref ? ?cch<1:0> bf80_a004 cm1conclr 31:0 write clears selected bits in cm1con, read yields undefined value bf80_a008 cm1conset 31:0 write sets selected bits in cm1con, read yields undefined value bf80_a00c cm1coninv 31:0 write inverts selected bits in cm1con, read yields undefined value bf80_a010 cm2con 31:24 ? ? ? ? ? ? ? ? 23:16 ? ? ? ? ? ? ? ? 15:8 on coe cpol ? ? ? ?cout 7:0 evpol<1:0> ? cref ? ?cch<1:0> bf80_a014 cm2conclr 31:0 write clears selected bits in cm2con, read yields undefined value bf90_a018 cm2conset 31:0 write sets selected bits in cm2con, read yields undefined value bf80_a01c cm2coninv 31:0 write inverts selected bits in cm2con, read yields undefined value bf80_a060 cmstat 31:24 ? ? ? ? ? ? ? ? 23:16 ? ? ? ? ? ? ? ? 15:8 ? frz sidl ? ? ? ? ? 7:0 ? ? ? ? ? ? c2out c1out bf80_a064 cmstatclr 31:0 write clears selected bits in cmstat, read yields undefined value bf80_a068 cmstatset 31:0 write sets selected bits in cmstat, read yields undefined value bf80_a06c cmstatinv 31:0 write inverts selected bits in cmstat, read yields undefined value
? 2008 microchip technology inc. preliminary ds61143e-page 539 pic32mx3xx/4xx table 24-2: comparator interrupt register summary (1) virtual address name bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 bf88_1040 ifs1 7:0 spi2rxif spi2txif spi2eif cmp2if cmp1if pmpif ad1if cnif bf88_1070 iec1 7:0 spi2rxie spi2txie spi2eie cmp2ie cmp1ie pmpie ad1ie cnie bf88_1100 ipc7 23:16 ? ? ? cmp2ip<2:0> cmp2is<1:0> 15:8 ? ? ? cmp1ip<2:0> cmp1is<1:0> note 1: this summary table contains partial register definitions t hat only pertain to the comparator peripheral. refer to the pic32mx family reference manual (ds61132) for a detailed description of these registers.
pic32mx3xx/4xx ds61143e-page 540 preliminary ? 2008 microchip technology inc. register 24-1: cm1con: comp arator 1 control register r-x r-x r-x r-x r-x r-x r-x r-x ? ? ? ? ? ? ? ? bit 31 bit 24 r-x r-x r-x r-x r-x r-x r-x r-x ? ? ? ? ? ? ? ? bit 23 bit 16 r/w-0 r/w-0 r/w-0 r-x r-x r-x r-x r-0 on coe cpol ? ? ? ?cout bit 15 bit 8 r/w-1 r/w-1 r-x r/w-0 r-x r-x r/w-1 r/w-1 evpol<1:0> ? cref ? ?cch<1:0> bit 7 bit 0 legend: r = readable bit w = writable bit p = programmable bit r = reserved bit u = unimplemented bit -n = bit value at por: (?0?, ?1?, x = unknown) bit 31-16 reserved: write ? 0 ?; ignore read bit 15 on: comparator on bit 1 = module is enabled. setting this bit does not affect the other bits in this register. 0 = module is disabled and does not consume current. clearing this bit does not affect the other bits in this register. bit 14 coe: comparator output enable bit 1 = comparator output is driven on the output c1out pin 0 = comparator output is not driven on the output c1out pin bit 13 cpol: comparator output inversion bit 1 = output is inverted 0 = output is not inverted note: setting this bit will invert the signal to the to the comparator interrupt generator as well. this will result in an interrupt being generated on the opposite edge from the one selected by evpol<1:0>. bit 12 reserved: write ? 0 ? bit 11-9 reserved: write ? 0 ?; ignore read bit 8 cout: comparator output bit 1 = output of the comparator is a ? 1 ? 0 = output of the comparator is a ? 0 ? bit 7-6 evpol<1:0>: interrupt event polarity select bits 11 = comparator interrupt is generated on a low-to-high or high-to-low transition of the comparator output 10 = comparator interrupt is generated on a high-to-low transition of the comparator output 01 = comparator interrupt is generated on a low-to-high transition of the comparator output 00 = comparator interrupt generation is disabled bit 5 reserved: write ? 0 ?; ignore read
? 2008 microchip technology inc. preliminary ds61143e-page 541 pic32mx3xx/4xx bit 4 cref: comparator 1 positive input configure bit 1 = comparator non-inverting input is connected to the internal cv ref 0 = comparator non-inverting input is connected to the c1in+ pin bit 3-2 reserved: write ? 0 ?; ignore read bit 1-0 cch<1:0>: comparator negative input select bits for comparator 1 11 = comparator inverting input is connected to the iv ref 10 = comparator inverting input is connected to the c2in+ pin 01 = comparator inverting input is connected to the c1in+ pin 00 = comparator inverting input is connected to the c1in- pin register 24-1: cm1con: comparator 1 control register (continued)
pic32mx3xx/4xx ds61143e-page 542 preliminary ? 2008 microchip technology inc. register 24-2: cm2con: comp arator 2 control register r-x r-x r-x r-x r-x r-x r-x r-x ? ? ? ? ? ? ? ? bit 31 bit 24 r-x r-x r-x r-x r-x r-x r-x r-x ? ? ? ? ? ? ? ? bit 23 bit 16 r/w-0 r/w-0 r/w-0 r-x r-x r-x r-x r-0 on coe cpol ? ? ? ?cout bit 15 bit 8 r/w-1 r/w-1 r-x r/w-0 r-x r-x r/w-1 r/w-1 evpol<1:0> ? cref ? ?cch<1:0> bit 7 bit 0 legend: r = readable bit w = writable bit p = programmable bit r = reserved bit u = unimplemented bit -n = bit value at por: (?0?, ?1?, x = unknown) bit 31-16 reserved: write ? 0 ?; ignore read bit 15 on: comparator on bit 1 = module is enabled. setting this bit does not affect the other bits in this register. 0 = module is disabled and does not consume current. clearing this bit does not affect the other bits in this register. bit 14 coe: comparator output enable bit 1 = comparator output is driven on the output c2out pin 0 = comparator output is not driven on the output c2out pin bit 13 cpol: comparator output inversion bit 1 = output is inverted 0 = output is not inverted note: setting this bit will invert the signal to the to the comparator interrupt generator as well. this will result in an interrupt being generated on the opposite edge from the one selected by evpol<1:0>. bit 12 reserved: write ? 0 ? bit 11-9 reserved: write ? 0 ?; ignore read bit 8 cout: comparator output bit 1 = output of the comparator is a ? 1 ? 0 = output of the comparator is a ? 0 ? bit 7-6 evpol<1:0>: interrupt event polarity select bits 11 = comparator interrupt is generated on a low-to-high or high-to-low transition of the comparator output 10 = comparator interrupt is generated on a high-to-low transition of the comparator output 01 = comparator interrupt is generated on a low-to-high transition of the comparator output 00 = comparator interrupt generation is disabled bit 5 reserved: write ? 0 ?; ignore read
? 2008 microchip technology inc. preliminary ds61143e-page 543 pic32mx3xx/4xx bit 4 cref: comparator 1 positive input configure bit 1 = comparator non-inverting input is connected to the internal cv ref 0 = comparator non-inverting input is connected to the c2in+ pin bit 3-2 reserved: write ? 0 ?; ignore read bit 1-0 cch<1:0>: comparator negative input select bits for comparator 2 11 = comparator inverting input is connected to the iv ref 10 = comparator inverting input is connected to the c1in+ pin 01 = comparator inverting input is connected to the c2in+ pin 00 = comparator inverting input is connected to the c2in- pin register 24-2: cm2con: comparator 2 control register (continued)
pic32mx3xx/4xx ds61143e-page 544 preliminary ? 2008 microchip technology inc. register 24-3: cmstat: co mparator control register r-x r-x r-x r-x r-x r-x r-x r-x ? ? ? ? ? ? ? ? bit 31 bit 24 r-x r-x r-x r-x r-x r-x r-x r-x ? ? ? ? ? ? ? ? bit 23 bit 16 r-x r/w-0 r/w-0 r-x r-x r-x r-x r-x ? frz sidl ? ? ? ? ? bit 15 bit 8 r-x r-x r-x r-x r-x r-x r-0 r-0 ? ? ? ? ? ? c2out c1out bit 7 bit 0 legend: r = readable bit w = writable bit p = programmable bit r = reserved bit u = unimplemented bit -n = bit value at por: (?0?, ?1?, x = unknown) bit 31-15 reserved: write ? 0 ?; ignore read bit 14 frz: freeze control bit 1 = freeze operation when cpu enters debug exception mode 0 = continue operation when cpu enters debug exception mode note: frz is writable in debug exception mode only. it always reads ? 0 ? in normal mode. bit 13 sidl: stop in idle control bit 1 = all comparator modules are disabled in idle mode 0 = all comparator modules continue to operate in idle mode. bit 12-2 reserved: write ? 0 ?; ignore read bit 1 c2out: comparator output bit 1 = output of comparator 2 is a ? 1 ? 0 = output of comparator 2 is a ? 0 ? bit 0 c1out: comparator output bit 1 = output of comparator 1 is a ? 1 ? 0 = output of comparator 1 is a ? 0 ?
? 2008 microchip technology inc. preliminary ds61143e-page 545 pic32mx3xx/4xx 24.2 comparator operation 24.2.1 comparator configuration the comparator module has a flexible input and output configuration to allow the module to be tailored to the needs of the application. the pic32mx3xx/4xx com- parator module has individual control over the enables, output inversion, output on i/o pin and input selections. the v in + pin of each comparator can select from an input pin or the cv ref . the v in - input of the compara- tor can select from one of 3 input pins or the iv ref . in addition, the module has two individual comparator event generation control bits. these control bits can be used for detecting when the output of an individual comparator changes to a desired state or changes states. if the comparator mode is changed, the comparator output level may not be valid for the specified mode change delay (refer to the device data sheet for more information). a single comparator is shown in the upper portion of figure 24-2. the lower portion represents the relation- ship between the analog input levels and the digital out- put. when the analog input at v in + is less than the analog input at v in -, the output of the comparator is a digital low level. when the analog input at v in + is greater than the analog input v in -, the output of the comparator is a digital high level. the shaded areas of the output of the comparator in the lower portion of figure 24-2 demonstrate the uncertainty that is due to input offsets and the response time of the comparator. 24.3 comparator inputs depending on the comparator operating mode, the inputs to the comparators may be from two input pins or a combination of an input pin and one of two internal voltage references. the analog signal present at v in - is compared to the signal at v in + and the digital output of the comparator is set or cleared according to the result of the comparison (see figure 24-2). figure 24-2: single comparator 24.3.0.1 external reference signal an external voltage reference may be used with the comparator by using the output of the reference as an input to the comparator. refer to the device data sheet for input voltage limits. 24.3.0.2 internal reference signals the cv ref module and the iv ref can be used as inputs to the comparator (see figure 24-1). the cv ref provides a user-selectable voltage for use as a compar- ator reference. refer to 25.0 ?comparator refer- ence? of this manual for more information on this module. the iv ref has a fixed, 1.2v output that does not change with the device supply voltage. refer to the device data sheet for specific details and accuracy of this reference. note: comparator interrupts should be disabled during a comparator mode change; otherwise, a false interrupt may be gener- ated. ? + v in + v in - output output v in - v in +
pic32mx3xx/4xx ds61143e-page 546 preliminary ? 2008 microchip technology inc. 24.4 comparator outputs the comparator output is read through the cmstat register and the cout bit (cm2con<8> or cm1con<8>). this bit is read-only. the comparator output may also be directed to an i/o pin via the cxout bit; however, the cout bit is still valid when the signal is routed to a pin. for the comparator output to be available on the cxout pin, the associated tris bit for the output pin must be configured as an output. when the cout signal is routed to a pin the signal is the unsynchronized output of the comparator. the output of the comparator has a degree of uncer- tainty. the uncertainty of each of the comparators is related to the input offset voltage and the response time, as stated in the specifications. the lower portion of figure 24-2 provides a graphical representation of this uncertainty. the comparator output bit, cout, provides the latched sampled value of the comparator?s output- when the register was read. there are two common methods used to detect a change in the comparator output: ? software polling ? interrupt generation 24.4.1 changing the polarity of comparator outputs the polarity of the comparator outputs can be changed using the cpol bit (cmxcon<13>). cpol appears below the comparator cx on the left side of figure 24-1. 24.5 analog input connection considerations a simplified circuit for an analog input is shown in figure 24-3. a maximum source impedance of 10 k is recommended for the analog sources. any external component connected to an analog input pin, such as a capacitor or a zener diode, should have very little leakage current. see the device data sheet for input voltage limits. if a pin is to be shared by two or more analog inputs that are to be used simultaneously, the loading effects of all the modules involved must be taken into consideration. this loading may reduce the accuracy of one or more of the modules connected to the common pin. this may also require a lower source impedance than is stated for a single module with exclusive use of a pin in analog mode. figure 24-3: comparator analog input model notes: when reading the port register, all pins configured as analog inputs will read as a ? 0 ?. pins configured as digital inputs will convert an analog input according to the schmitt trigger input specification. analog levels on any pin defined as a digital input may cause the input buffer to consume more current than is specified. va r s < 10k a in c pin 5 pf v dd r ic i leakage 500 na v ss comparator input legend: c pin = input capacitance leakage = leakage current at the pin due to various junctions r ic = interconnect resistance r s = source impedance va = analog voltage
? 2008 microchip technology inc. preliminary ds61143e-page 547 pic32mx3xx/4xx 24.6 interrupts example 24-1: comparator initialization with interrupts enabled code example example 24-2: comparator isr code example // configure both comparators to generate an interrupt on any // output transition cm1con = 0xc0d0; // initialize comparator 1 // comparator enabled, output enabled, interrupt on any output // change, inputs: cvref, c1in- cm2con = 0xa0c2; // initialize comparator 2 // comparator enabled, output enabled, interrupt on any output // change, inputs: c2in+, c1in+ // enable interrupts for comparator modules and set priorities // set priority to 7 & sub priority to 3 ipc7set = 0x00000700; // set cmp1 interrupt sub priority ifs1clr = 0x00000008; // clear the cmp1 interrupt flag iec1set = 0x00000008; // enable cmp1 interrupt ipc7set = 0x00070000; // set cmp2 interrupt sub priority ifs1clr = 0x000000010; // clear the cmp2 interrupt flag iec1set = 0x000000010; // enable cmp2 interrupt // insert user code here void__isr(_comparator_2_vector, ipl4)cmp2_inthandler(void) { // insert user code here ifs1clr = 0x00000010; // clear the cmp2 interrupt flag } void__isr(_comparator_1_vector, ipl4)cmp1_inthandler(void) { // insert code user here ifs1clr = 0x00000008; // clear the cmp1 interrupt flag }
pic32mx3xx/4xx ds61143e-page 548 preliminary ? 2008 microchip technology inc. 24.7 i/o pin control table 24-3: pins associated with a comparator pin name module control controlling bit field required tris bit setting pin type buffer type description c1in+ (3) on cvr ef (1) , cch<1:0> (1) , cch<1:0> (2) , ad1pcfg input a, i ? analog input for c1in+ c1in- on cch<1:0> (1) , ad1pcfg input a, i ? analog input for c1in- c2in+ on cvr ef (2) , cch<1:0> (1) , cch<1:0> (2) , ad1pcfg input a, i ? analog input for c2in+ c2in- on cch<1:0> (2) , ad1pcfg input a, i ? analog input for c2in- c1out on coe (1) output d, o ? digital output of the c1 c2out on coe (2) output d, o ? digital output of the c2 legend: st = schmitt trigger input with cmos levels, i = input, o = output, a = analog, d = digital note 1: in cm1con register. 2: in cm2con register. 3: on usb variants, when usb is enabled, this pin is controlled by the usb module and therefore is not available as a comparator input.
? 2008 microchip technology inc. preliminary ds61143e-page 549 pic32mx3xx/4xx 25.0 comparator reference the comparator voltage reference (cv ref ) is a 16- tap, resistor ladder network that provides a selectable reference voltage. although its primary purpose is to provide a reference for the analog comparators, it also may be used independently of them. a block diagram of the module is shown in figure 25-1. the resistor ladder is segmented to provide two ranges of voltage reference values and has a power-down func- tion to conserve power when the reference is not being used. the module?s supply reference can be provided from either device v dd /v ss or an external voltage refer- ence. the cv ref output is available for the comparators and typically available for pin output. please see the specific device data sheet for information. the comparator voltage reference has the following features: ? high and low range selection ? sixteen output levels available for each range ? internally connected to comparators to conserve device pins ? output can be connected to a pin figure 25-1: comparator voltage reference block diagram note: this data sheet summarizes the features of the pic32mx3xx/4xx family of devices. it is not intended to be a comprehensive refer- ence source. refer to the ?pic32mx family reference manual? (ds61132) for a detailed description of this peripheral. 16-to-1 mux cvr3:cvr0 8r r cvren cvrss = 0 av dd v ref + cvrss = 1 8r cvrss = 0 v ref - cvrss = 1 r r r r r r 16 steps cvrr cv ref av ss cvrcon pic32mx3xx/4xx ds61143e-page 550 preliminary ? 2008 microchip technology inc. 25.1 comparator voltage reference control registers the cv ref module consists of the following special function registers (sfrs): ? cvrcon: control register for the module ? cvrconclr, cvrconset, cvrconinv: atomic bit manipulation registers for cvrcon table 25-1 provides a brief summary of all cv ref module related registers. corresponding registers appear after the summary, followed by a detailed description of each register. table 25-1: comparator voltage reference sfr summary virtual address name bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 bf80_9800 cvrcon 31:24 ? ? ? ? ? ? ? ? 23:16 ? ? ? ? ? ? ? ? 15:8 on ? ? ? ? ? 7:0 ? cvroe cvrr cvrss cvr<3:0> bf80_9804 cvrconclr 31:0 write clears selected bits in cvrcon, read yields undefined value bf80_9808 cvrconset 31:0 write sets selected bits in cvrcon, read yields undefined value bf80_980c cvrconinv 31:0 write inverts selected bits in cvrcon, read yields undefined value
? 2008 microchip technology inc. preliminary ds61143e-page 551 pic32mx3xx/4xx register 25-1: cvrcon: comparator vo ltage reference control register r-x r-x r-x r-x r-x r-x r-x r-x ? ? ? ? ? ? ? ? bit 31 bit 24 r-x r-x r-x r-x r-x r-x r-x r-x ? ? ? ? ? ? ? ? bit 23 bit 16 r/w-0 r-x r-x r-x r-x r-x r-x r-x on ? ? ? ? ? ? ? bit 15 bit 8 r-x r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? cvroe cvrr cvrss cvr<3:0> bit 7 bit 0 legend: r = readable bit w = writable bit p = programmable bit r = reserved bit u = unimplemented bit -n = bit value at por: (?0?, ?1?, x = unknown) bit 31-16 reserved: write ? 0 ?; ignore read bit 15 on: cv ref peripheral on bit 1 = module is enabled; setting this bit does not affect the other bits in the register 0 = module is disabled and does not consume current; clearing this bit does not affect the other bits in the register bit 14-7 reserved: write ? 0 ?; ignore read bit 6 cvroe: cv ref output enable bit 1 = voltage level is output on cv ref pin 0 = voltage level is disconnected from cv ref pin note: cvroe overrides the tris bit setting; see section 12.0 ?i/o ports? for more information. bit 5 cvrr: cv ref range selection bit 1 = 0 to 0.67 cv rsrc , with cv rsrc /24 step size 0 =0.25 cv rsrc to 0.75 cv rsrc , with cv rsrc /32 step size bit 4 cvrss: cv ref source selection bit 1 = comparator voltage reference source, cv rsrc = (v ref +) ? (v ref -) 0 = comparator voltage reference source, cv rsrc = av dd ? av ss bit 3-0 cvr<3:0>: cv ref value selection 0 cvr3:cvr0 15 bits when cvrr = 1 : cv ref = (cvr<3:0>/24) ? (cv rsrc ) when cvrr = 0 : cv ref =1/4 ? (cv rsrc ) + (cvr<3:0>/32) ? (cv rsrc )
pic32mx3xx/4xx ds61143e-page 552 preliminary ? 2008 microchip technology inc. 25.2 operation the cv ref module is controlled through the cvrcon register (register 25-1). the cv ref provides two ranges of output voltage, each with 16 distinct levels. the range to be used is selected by the cvrr bit (cvrcon<5>). the primary difference between the ranges is the size of the steps selected by the cv ref value selection bits, cvr3:cvr0, with one range offering finer resolution and the other offering a wider range of output voltage. the typical output voltages are listed in table 25-2. the equations used to calculate the cv ref output are as follows: if cvrr = 1 : voltage reference = ((cvr3:cvr0)/24) x (cv rsrc ) if cvrr = 0 : voltage reference = (cv rsrc /4) + ((cvr3:cvr0)/32) x(cv rsrc ) the cv ref source voltage (cv rsrc ) can come from either v dd and v ss , or the external v ref + and v ref - pins that are multiplexed with i/o pins. the voltage source is selected by the cvrss bit (cvrcon<4>). the voltage reference is output to the cv ref pin by set- ting the cvroe (cvrcon<6>) bit; this will override the corresponding tris bit setting. the settling time of the cv ref must be considered when changing the cv ref output (refer to the data sheet for your device). table 25-2: typical voltage reference with cv rsrc =3.3 cvr<3:0> voltage reference cvrr = 0 (cvrcon <5>) cvrr = 1 (cvrcon <5> 0 0.83v 0.00v 1 0.93v 0.14v 2 1.03v 0.28v 3 1.13v 0.41v 4 1.24v 0.55v 5 1.34v 0.69v 6 1.44v 0.83v 7 1.55v 0.96v 8 1.65v 1.10v 9 1.75v 1.24v 10 1.86v 1.38v 11 1.96v 1.51v 12 2.06v 1.65v 13 2.17v 1.79v 14 2.27v 1.93v 15 2.37v 2.06v
? 2008 microchip technology inc. preliminary ds61143e-page 553 pic32mx3xx/4xx 25.2.1 cv ref output considerations the full range of voltage reference cannot be realized due to the construction of the module. the transistors on the top and bottom of the resistor ladder network (figure 25-1) keep the voltage reference from approaching the reference source rails. the voltage reference is derived from the reference source; there- fore, the voltage reference output changes with fluctuations in that source. refer to the product data sheet for the electrical specifications. table 25-3 contains the typical output impedances for the cv ref module. 25.2.2 initialization this initialization sequence, shown in example 25-1, configures the cv ref module for: module enabled, out- put enabled, high range, and set output for maximum (2.37v). example 25-1: voltage re ference configuration table 25-3: typical cv ref output impedance in ohms cvr<3:0> voltage reference cvrr = 0 (cvrcon <5>) cvrr = 1 (cvrcon <5> 0 12k 500 1 13k 1.9k 2 13.8k 3.7k 3 14.4k 5.3k 4 15k 6.7k 5 15.4k 7.9k 6 15.8k 9k 7 15.9k 9.9k 816k 10.7k 9 15.9k 11.3k 10 15.8k 11.7k 11 15.4k 11.9k 12 15k 12k 13 14.4k 11.9k 14 13.8k 11.7k 15 12.9k 11.3k cvrcon = 0x804f; //initialize voltage reference module //enable module, enable output, set // range to high, set output to maximum
pic32mx3xx/4xx ds61143e-page 554 preliminary ? 2008 microchip technology inc. 25.3 interrupts there are no interrupt configuration registers or bits for the cv ref module. the cv ref module does not generate interrupts. 25.4 i/o pin control the cv ref module has the ability to output to a pin. when the cv ref module is enabled and cvroe (cvrcon<6>) is ? 1 ?, the output driver for the cv ref pin is disabled and the cv ref voltage is available at the pin. for proper operation, the tris bit corresponding to the cv ref pin must be a ? 1 ? when cv ref is to be output to a pin. this disables the digital input mode for the pin and prevents undesired current draw resulting from applying an analog voltage to a digital input pin. the output buffer has very limited drive capability. an exter- nal buffer amplifier is recommended for any application that uses the cv ref voltage externally. an output capacitor may be used to reduce output noise. use of an output capacitor will increase settling time. table 25-4: pins associated with a comparator pin name module control controlling bit field required tris bit setting pin type buffer type description cv ref on cvroe input a, o ? cv ref output legend: st = schmitt trigger input with cmos levels, i = input, o = output, a = analog, d = digital
? 2008 microchip technology inc. preliminary ds61143e-page 555 pic32mx3xx/4xx 26.0 watchdog timer this section describes the operation of the watchdog timer (wdt) and power-up timer of the pic32mx3xx/4xx. the wdt, when enabled, operates from the internal low-power oscillator (lprc) clock source and can be used to detect system software malfunctions by reset- ting the device if the wdt is not cleared periodically in software. various wdt time-out periods can be selected using the wdt postscaler. the wdt can also be used to wake the device from sleep or idle mode. refer to figure 26-1. the following are some of the key features of the wdt module: ? configuration or software controlled ? user-configurable time-out period ? can wake the device from sleep or idle figure 26-1: watchdog and powe r-up timer block diagram note: this data sheet summarizes the features of the pic32mx3xx/4xx of devices. it is not intended to be a comprehensive reference source. refer to the ?pic32mx family reference manual? (ds61132) for a detailed description of this peripheral. table 26-1: results of a wdt time-o ut event for available modes of device operation device mode device reset generated non- maskable interrupt generated wdto (1) bit set sleep (1) bit set idle (1) bit set device registers reset awake yes no yes no no yes sleep no yes yes yes no n o idle no yes yes no yes no note 1: status bits are in the rcon register. wake wdtclr = 1 wdt enable lprc power save 25-bit counter pwrt enable wdt enable lprc wdt counter reset control oscillator 25 device reset nmi (wake-up) pwrt pwrt enable fwdtps<4:0>(devcfg1<20:16>) clock decoder 1 1:64 output 0 1
pic32mx3xx/4xx ds61143e-page 556 preliminary ? 2008 microchip technology inc. 26.1 watchdog timer registers table 26-2: wdt sfr summary virtual address name bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 bf80_0000 wdtcon 31:24 ? ? ? ? ? ? ? ? 23:16 ? ? ? ? ? ? ? ? 15:8 on ? ? ? ? ? ? ? 7:0 ?swdtps ? wdtclr bf80_0004 wdtconclr 31:0 write clears selected bits in wdtcon, read yields an undefined value bf80_0008 wdtconset 31:0 write sets selected bits in wdtcon, read yields an undefined value bf80_000c wdtconinv 31:0 write inverts selected bits in wdtcon, read yields an undefined value table 26-3: reset register summary (1) virtual address name bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 bf80_f600 rcon 31:24 ? ? ? ? ? ? ? ? 23:16 ? ? ? ? ? ? ? ? 15:8 ? ? ? ? ? ? cm vregs 7:0 extr swr ?wdto sleep idle bor por bf80_f604 rconclr 31:0 write clears selected bits in rcon, read yields an undefined value bf80_f608 rconset 31:0 write sets selected bits in rcon, read yields an undefined value bf80_f60c rconinv 31:0 write inverts selected bits in rcon, read yields an undefined value note 1: this summary table contains partial register definitions that only pertain to the watchdog timer peripheral. refer to the pic32mx family reference manual (ds61132) for a detailed description of these registers. table 26-4: device configuration summary (1) virtual address name bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 bfc0_2ff8 devcfg1 23:16 fwdten ? ? wdtps<4:0> note 1: this summary table contains partial register definitions that only pertain to the watchdog timer peripheral. refer to the pic32mx family reference manual (ds61132) for a detailed description of these registers.
? 2008 microchip technology inc. preliminary ds61143e-page 557 pic32mx3xx/4xx register 26-1: wdtcon: wat chdog timer control register r-x r-x r-x r-x r-x r-x r-x r-x ? ? ? ? ? ? ? ? bit 31 bit 24 r-x r-x r-x r-x r-x r-x r-x r-x ? ? ? ? ? ? ? ? bit 23 bit 16 r/w-0 r-x r-x r-x r-x r-x r-x r-x on ? ? ? ? ? ? ? bit 15 bit 8 r-x r-x r-x r-x r-x r-x r-0 r/w-0 ?swdtps ? wdtclr bit 7 bit 0 legend: r = readable bit w = writable bit p = programmable bit r = reserved bit u = unimplemented bit -n = bit value at por: (?0?, ?1?, x = unknown) bit 31-16 reserved: write ? 0 ?; ignore read bit 15 on: watchdog timer enable bit (1) 1 = enables the wdt if it is not enabled by the device configuration 0 = disable the wdt if is was enabled in software. bit 14-7 reserved: write ? 0 ?; ignore read bit 6-2 swdtps<4:0>: shadow copy of watchdog timer post-scaler value from device configuration bits bit 1 reserved: write ? 0 ? bit 0 wdtclr: watchdog timer reset bit 1 = writing a ? 1 ? will reset the wdt. 0 = software cannot force this bit to a ? 0 ? . note 1: a read of this bit will result in a ? 1 ? if the wdt is enabled by the device configuration or by software.
pic32mx3xx/4xx ds61143e-page 558 preliminary ? 2008 microchip technology inc. register 26-2: rcon: re sets control register r-x r-x r-x r-x r-x r-x r-x r-x ? ? ? ? ? ? ? ? bit 31 bit 24 r-x r-x r-x r-x r-x r-x r-x r-x ? ? ? ? ? ? ? ? bit 23 bit 16 r/w-0 r-x r-x r-x r-x r-0 r/w-0 r/w-0 ? ? ? ? ? ? cm vregs bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 extr swr ? wdto sleep idle bor por bit 7 bit 0 legend: r = readable bit w = writable bit p = programmable bit r = reserved bit u = unimplemented bit -n = bit value at por: (?0?, ?1?, x = unknown) bit 4 wdto: watchdog time-out bit 1 = a wdt time-out has occurred since the device was powered up 0 = a wdt time-out has not occurred since the wdto bit was cleared by software bit 3 sleep: sleep mode status bit 1 = the device has been in sleep mode since the device was powered up 0 = the device has not been in sleep mode since the sleep bit was cleared by software bit 2 idle: idle mode status bit 1 = the device has been in idle mode since the device was powered up 0 = the device has not been in idle mode since the idle bit was cleared by software
? 2008 microchip technology inc. preliminary ds61143e-page 559 pic32mx3xx/4xx register 26-3: devcfg1: de vice configuration word 1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 ? ? ? ? ? ? ? ? bit 31 bit 24 r/p-1 r-1 r-1 r/p-1 r/p-1 r/p-1 r/p-1 r/p-1 fwdten ? ? wdtps<4:0> bit 23 bit 16 r/p-1 r/p-1 r/p-1 r/p-1 r-1 r/p-1 r/p-1 r/p-1 fcksm<1:0> fpbdiv<1:0> ? osciofnc poscmd<1:0> bit 15 bit 8 r/p-1 r-1 r/p-1 r-1 r-1 r/p-1 r/p-1 r/p-1 ieso ? fsoscen ? ?fnosc<2:0> bit 7 bit 0 legend: r = readable bit w = writable bit p = programmable bit r = reserved bit u = unimplemented bit -n = bit value at por: (?0?, ?1?, x = unknown) bit 31-24 reserved: write ? 1 ? bit 23 fwdten: watchdog timer hardware enable bit 1 = the wdt is enabled and cannot be disabled by software 0 = the wdt is not enabled. it can be enabled in software bit 22 reserved: write ? 1 ? bit 20-16 wdtps<4:0>: watchdog timer postscaler selection bits (1) these bits are used to set the wdt time-out period. 10100 = 1:1,045,876 10011 = 1:524,288 10010 = 1:262,144 10001 = 1:131,072 10000 = 1:65,536 01111 = 1:32,768 01110 = 1:16,384 01101 = 1:8,192 01100 = 1:4,096 01011 = 1:2,048 01010 = 1:1,024 01001 = 1:512 01000 = 1:256 00111 = 1:128 00110 = 1:64 00101 = 1:32 00100 = 1:16 00011 = 1:8 00010 = 1:4 00001 = 1:2 00000 = 1:1 note 1: all combinations not listed result in operation as if the selection was 10100 . 2: do not disable posc (poscmd = 00 ) when using this oscillator source.
pic32mx3xx/4xx ds61143e-page 560 preliminary ? 2008 microchip technology inc. bit 15-14 fcksm<1:0>: clock switching and monitor selection configuration bits 1x = clock switching is disabled, fail-safe clock monitor is disabled 01 = clock switching is enabled, fail-safe clock monitor is disabled 00 = clock switching is enabled, fail-safe clock monitor is enabled bit 13-12 fpbdiv<1:0>: peripheral bus clock divisor default value bits 11 = pbclk is sysclk divided by 8 10 = pbclk is sysclk divided by 4 01 = pbclk is sysclk divided by 2 00 = pbclk is sysclk divided by 1 bit 11 reserved: write ? 1 ? bit 10 osciofnc: clko enable configuration bit 1 = clko output signal active on the osco pin; primary oscillator must be disabled or configured for the external clock (ec) mode for the clko to be active (poscmd<1:0> = 11 or 00 ) 0 = clko output disabled bit 9-8 poscmd<1:0>: primary oscillator configuration bits 11 = primary oscillator is disabled 10 = hs oscillator mode selected 01 = xt oscillator mode selected 00 = external clock mode selected bit 7 ieso: internal external switchover bit 1 = internal external switchover mode enabled (two-speed start-up enabled) 0 = internal external switchover mode disabled (two-speed start-up disabled) bit 6 reserved: write ? 1 ? bit 5 fsoscen: secondary oscillator enable bits 1 = enable secondary oscillator 0 = disable secondary oscillator bit 4-3 reserved: write ? 1 ? bit 2-0 fnosc<2:0>: oscillator selection bits 000 = fast rc oscillator (frc) 001 = fast rc oscillator with divide-by-n with pll module (frcdiv + pll) 010 = primary oscillator (xt, hs, ec) (2) 011 = primary oscillator with pll module (xt + pll, hs + pll, ec + pll) (2) 100 = secondary oscillator 101 = low-power rc oscillator (lprc) 110 = frcdivig fast rc oscillator with fixed divide-by-16 postscaler 111 = fast rc oscillator with divide-by-n (frcdiv) register 26-3: devcfg1: de vice configuration word 1 note 1: all combinations not listed result in operation as if the selection was 10100 . 2: do not disable posc (poscmd = 00 ) when using this oscillator source.
? 2008 microchip technology inc. preliminary ds61143e-page 561 pic32mx3xx/4xx 26.2 watchdog timer and power-up timer operation this describes the operation of the watchdog timer operation and the power-up timer 26.2.1 watchdog timer operation if enabled, the wdt will increment until it overflows or ?times out?. a wdt time-out will force a device reset, except during sleep or idle modes. to prevent a wdt time-out reset, the user must periodically clear the watchdog timer by setting the wdtclr (wdtcon<0>) bit. the wdt uses the lprc oscillator for reliability. 26.2.2 enabling and disabling the wdt the wdt is enabled or disabled by the device configu- ration or controlled via software by writing to the wdtcon register. 26.2.3 device configuration controlled wdt if the fwdten configuration bit is set, then the wdt is always enabled. the wdt on control bit (wdtcon<15>) will reflect this by reading a ? 1 ?. in this mode, the on bit cannot be cleared in software. this bit will not be cleared by any form of reset. to disable the wdt in this mode, the configuration must be rewritten to the device. 26.2.4 software controlled wdt if the fwdten configuration bit is a ? 0 ?, then the wdt can be enabled or disabled (the default condition) by software. in this mode, the on (wdtcon<15>) bit reflects the status of the wdt under software control. a ? 1 ? indicates the wdt is enabled and a ? 0 ? indicates it is disabled. the wdt is enabled in software by setting the wdt on control bit. the wdt on control bit is cleared on any device reset, the bit is not cleared upon a wake from sleep or exit from idle mode. the software wdt option allows the user to enable the wdt for critical code segments and disable the wdt during noncritical segments for maximum power savings. this bit can also be used to disable the wdt while the part is awake to eliminate the need for wdt servicing, and then re-enable it before the device is put into idle or sleep to wake the part at a later time. 26.2.5 wdt operation in power save modes the wdt, if enabled, will continue operation in sleep or idle modes. the wdt may be used to wake the device from sleep or idle. when the wdt times out in a power save mode, a non-maskable interrupt (nmi) is gener- ated and the wdto (rcon<4>) bit is set. the nmi vectors execution to the cpu start-up address but does not reset registers or peripherals. if the device was in sleep, the sleep (rcon<3>) status bit will also be set. if the device was in idle, the idle (rcon<2>) sta- tus bit will also be set. these bits allow the start-up code to determine the cause of the wake-up. 26.2.6 time delays on wake there will be a time delay between the wdt event in sleep and the beginning of code execution. the dura- tion of this delay consists of the start-up time for the oscillator in use and the power-up timer delay, if it is enabled. unlike a wake-up from sleep mode, there are no time delays associated with wake-up from idle mode. the system clock is running during idle mode; therefore, no start-up delays are required at wake-up. 26.2.7 resetting the wdt timer the wdt is reset by any of the following: ? on any device reset ?by a wdtconset = 0x01 or equivalent instruction during normal execution. ? execution of a debug command ? exiting from idle or sleep due to an interrupt 26.2.8 wdt timer period selection the wdt clock source is the internal lprc oscillator, which has a nominal frequency of 32 khz. this creates a nominal time-out period for the wdt (t wdt ) of 1 millisecond when no postscaler is used. note: the lprc is enabled whenever the wdt is enabled. note: the default state for the wdt on an unprogrammed device is wdt enabled. note: the wdt timer is not reset when the device enters a power save mode. the wdt should be serviced prior to entering a power save mode. note: the wdt time-out period is directly related to the frequency of the lprc oscillator. the frequency of the lprc oscillator will vary as a function of device operating voltage and temperature. please refer to the specific pic32mx3xx/4xx device data sheet for lprc clock frequency specifications.
pic32mx3xx/4xx ds61143e-page 562 preliminary ? 2008 microchip technology inc. 26.2.9 wdt postscalers the wdt has a 5-bit postscaler to create a wide variety of time-out periods. this postscaler provides 1:1 through 1: 1048576 divider ratios. time-out periods that range between 1 ms and 1048.576 seconds (nominal) can be achieved using the postscaler. the postscaler settings are selected using the wdtps bits in the devcfg1 configuration register. the time- out period of the wdt is calculated as follows: equation 26-1: wdt time-out period calculations table 26-5: wdt time-out period vs. postscaler settings wdt period = 1 ms ? 2 prescaler fwdtps<4:0> postscaler ratio time-out period 00000 1:1 1 ms 00001 1:2 2 ms 00010 1:4 4 ms 00011 1:8 8 ms 00100 1:16 16 ms 00101 1:32 32 ms 00110 1:64 64 ms 00111 1:128 128 ms 01000 1:256 256 ms 01001 1:512 512 ms 01010 1:1024 1.024 s 01011 1:2048 2.048 s 01100 1:4096 4.096 s 01101 1:8192 8.192 s 01110 1:16384 16.384 s 01111 1:32768 32.768 s 10000 1:65536 65.536 s 10001 1:131072 131.072 s 10010 1:262144 262.144 s 10011 1:524288 524.288 s 10100 1:1045876 1048.576 s note 1: all other combinations will result in an operation as if the prescaler was set to 10100 . 2: the periods listed are based on a 32 khz (nominal) input clock.
? 2008 microchip technology inc. preliminary ds61143e-page 563 pic32mx3xx/4xx 26.3 interrupts and resets the wdt will cause an nmi or a device reset when it expires. the power save mode of the device determines which event occurs. the pwrt does not generate interrupts or resets. 26.3.1 watchdog timer reset when the wdt expires and the device is not in sleep or idle, a device reset is generated. the cpu code execution jumps to the device reset vector and the registers and peripherals are forced to their reset values. to detect a wdt reset, the wdto (rcon<4>), sleep (rcon<3>) and idle (wdtcon<2>) bits must be tested. if the wdto bit is a ? 1 ?, the event was do to a wdt time-out. the sleep and idle bits can then be tested to determine if the wdt event occurred while the device was awake or if it was in sleep or idle. 26.3.2 watchdog timer nmi when the wdt expires in sleep or idle, a nmi is gen- erated. the nmi causes the cpu code execution to jump to the device reset vector. though the nmi share the same vector as a device reset, registers and peripherals are not reset. to detect a wake from a power save mode by wdt, the wdto (rcon<4>), sleep (rcon<3>) and idle (wdtcon<2>) bits must be tested. if the wdto bit is a ? 1 ? the event was caused by a wdt time-out. the sleep and idle bits can then be tested to determine if the wdt event occurred in sleep or idle. to cause a wdt time-out in sleep to act like an inter- rupt, a return from interrupt instruction may be used in the start-up code after the event was determined to be a wdt wake-up. this will cause code execution to con- tinue with the opcode following the wait instruction that put the device into power save mode. see example 26-2. example 26-1: sample wdt initialization and servicing //this code fragment assumes the wdt was not enabled by the device configuration // the postscaler value must be set with the device configuration wdtconset = 0x8000; // turn on the wdt main { wdtconset = 0x01; // service the wdt ... user code goes here ... }
pic32mx3xx/4xx ds61143e-page 564 preliminary ? 2008 microchip technology inc. example 26-2: sample code to determine the cause of a wdt event // sample code to determine the cause of a wdt event // unlock the osccon register syskey = 0x12345678; //write invalid key to force lock syskey = 0xaa996655; //write key1 to syskey syskey = 0x556699aa; //write key2 to syskey // osccon is now unlocked oscconset = 0x10; // set power save mode to sleep // alternate relock code in ?c? sysreg = 0x33333333; // osccon is relocked wdtconset = 0x8000; //enable wdt while (1) { ... user code ... wdtconset = 0x01;// service the wdt asm volatile ( ?wait? ); // put device is selected power save mode // code execution will resume here after wake ... user code ... } // the following code fragment is at the top of the device start-up code if ( rcon & 0x18 ) { // the wdt caused a wake from sleep asm volatile ( ?eret? ); // return from interrupt } if ( rcon & 0x14 ) { // the wdt caused a wake from idle asm volatile ( ?eret? ); // return from interrupt } if ( rcon & 0x10 ) { // wdt timed-out (device may have been awake or may have been in sleep/idle mode) }
? 2008 microchip technology inc. preliminary ds61143e-page 565 pic32mx3xx/4xx 27.0 special features pic32mx3xx/4xx devices include several features intended to maximize application flexibility and reliabil- ity, and minimize cost through elimination of external components. these are: ? flexible device configuration ? code protection ? internal voltage regulator note: this data sheet summarizes the features of the pic32mx3xx/4xx of devices. it is not intended to be a comprehensive reference source. refer to the ?pic32mx family reference manual? (ds61132) for a detailed description of this peripheral. table 27-1: devcfg: device configuration word summary virtual address name bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 bfc0_2ff0 devcfg3 31:24 ? ? ? ? ? ? ? ? 23:16 ? ? ? ? ? ? ? ? 15:8 userid15 userid14 userid13 userid12 userid11 userid10 userid9 userid8 7:0 userid7 userid6 userid5 userid4 userid3 userid2 userid1 userid0 bfc0_2ff4 devcfg2 31:24 ? ? ? ? ? ? ? ? 23:16 ? ? ? ? ? fpllodiv<2:0> 15:8 fupllen ? ? ? ? fupllidiv<2:0> 7:0 ? fpllmult<2:0> ? fpllidiv<2:0> bfc0_2ff8 devcfg1 31:24 ? ? ? ? ? ? ? ? 23:16 fwdten ? ? wdtps<4:0> 15:8 fcksm<1:0> fpbdiv<1:0> ? osciofnc poscmd<1:0> 7:0 ieso ? fsoscen ? ?fnosc<2:0> bfc0_2ffc devcfg0 31:24 ? ? ?cp ? ? ?bwp 23:16 ? ? ? ? pwp19 pwp18 pwp17 pwp16 15:8 pwp15 pwp14 pwp13 pwp12 ? ? ? ? 7:0 ? ? ? ? icesel ? debug<1:0> table 27-2: devid summary virtual address name bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 bf80_f220 devid 31:24 ver11 ver10 ver9 ver8 ver7 ver6 ver5 ver4 23:16 ver3 ver2 ver1 ver0 dev7 dev6 dev5 dev4 15:8 dev3 dev2 dev1 dev0 manid11 manid10 manid9 manid8 7:0 manid7 manid6 manid5 manid4 manid3 manid2 manid1 1
pic32mx3xx/4xx ds61143e-page 566 preliminary ? 2008 microchip technology inc. register 27-1: devcfg0: de vice configuration word 0 r-0 r-1 r-1 r/p-1 r-1 r-1 r-1 r/p-1 ? ? ?cp ? ? ?bwp bit 31 bit 24 r-1 r-1 r-1 r-1 r/p-1 r/p-1 r/p-1 r/p-1 ? ? ? ? pwp19 pwp18 pwp17 pwp16 bit 23 bit 16 r/p-1 r/p-1 r/p-1 r/p-1 r-1 r-1 r-1 r-1 pwp15 pwp14 pwp13 pwp12 ? ? ? ? bit 15 bit 8 r-1 r-1 r-1 r-1 r/p-1 r-1 r/p-1 r/p-1 ? ? ? ? icesel ? debug1 debug0 bit 7 bit 0 legend: r = readable bit w = writable bit p = programmable bit r = reserved bit u = unimplemented bit -n = bit value at por: (?0?, ?1?, x = unknown) bit 31 reserved: write ? 0 ? bit 30-29 reserved: write ? 1 ? bit 28 cp: code-protect bit prevents boot and program flash memory from being read or modified by an external programming device. 1 = protection disabled 0 = protection enabled bit 27-25 reserved: write ? 1 ? bit 24 bwp: boot flash write-protect bit prevents boot flash memory from being modified during code execution. 1 = boot flash is writable 0 = boot flash is not writable bit 23-20 reserved: write ? 1 ?
? 2008 microchip technology inc. preliminary ds61143e-page 567 pic32mx3xx/4xx bit 19-12 pwp<19:12>: program flash write-protect bits prevents selected program flash memory pages from being modified during code execution. the pwp bits represent the one?s compliment of the number of write protected program flash memory pages. 11111111 = disabled 11111110 = 0xbd00_0fff 11111101 = 0xbd00_1fff 11111100 = 0xbd00_2fff 11111011 = 0xbd00_3fff 11111010 = 0xbd00_4fff 11111001 = 0xbd00_5fff 11111000 = 0xbd00_6fff 11110111 = 0xbd00_7fff 11110110 = 0xbd00_8fff 11110101 = 0xbd00_9fff 11110100 = 0xbd00_afff 11110011 = 0xbd00_bfff 11110010 = 0xbd00_cfff 11110001 = 0xbd00_dfff 11110000 = 0xbd00_efff 11101111 = 0xbd00_ffff ... 01111111 = 0xbd07_ffff bit 11-4 reserved: write ? 1 ? bit 3 icesel: in-circuit emulator/debugger communication channel select bit 1 = in-circuit emulator uses emuc2/emud2 pins; in-circuit debugger uses pgc2/pgd2 pins 0 = in-circuit emulator uses emuc1/emud1 pins; in-circuit debugger uses pgc1/pgd1 pins bit 2 reserved: write ? 1 ? bit 1-0 debug<1:0>: background debugger enable bits (forced to ? 11 ? if code-protect is enabled) 11 = debugger disabled 10 = debugger enabled 01 = reserved (same as ? 11 ? setting) 00 = reserved (same as ? 11 ? setting) register 27-1: devcfg0: device configuration word 0 (continued)
pic32mx3xx/4xx ds61143e-page 568 preliminary ? 2008 microchip technology inc. register 27-2: devcfg1: de vice configuration word 1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 ? ? ? ? ? ? ? ? bit 31 bit 24 r/p-1 r-1 r-1 r/p-1 r/p-1 r/p-1 r/p-1 r/p-1 fwdten ? ? wdtps<4:0> bit 23 bit 16 r/p-1 r/p-1 r/p-1 r/p-1 r-1 r/p-1 r/p-1 r/p-1 fcksm<1:0> fpbdiv<1:0> ? osciofnc poscmd<1:0> bit 15 bit 8 r/p-1 r-1 r/p-1 r-1 r-1 r/p-1 r/p-1 r/p-1 ieso ? fsoscen ? ?fnosc<2:0> bit 7 bit 0 legend: r = readable bit w = writable bit p = programmable bit r = reserved bit u = unimplemented bit -n = bit value at por: (?0?, ?1?, x = unknown) bit 31-24 reserved: write ? 1 ? bit 23 fwdten: watchdog timer enable bit 1 = the wdt is enabled and cannot be disabled by software 0 = the wdt is not enabled; it can be enabled in software bit 22-21 reserved: write ? 1 ? bit 20-16 wdtps<4:0>: watchdog timer postscale select bits 10100 = 1:1048576 10011 = 1:524288 10010 = 1:262144 10001 = 1:131072 10000 = 1:65536 01111 = 1:32768 01110 = 1:16384 01101 = 1:8192 01100 = 1:4096 01011 = 1:2048 01010 = 1:1024 01001 = 1:512 01000 = 1:256 00111 = 1:128 00110 = 1:64 00101 = 1:32 00100 = 1:16 00011 = 1:8 00010 = 1:4 00001 = 1:2 00000 = 1:1 all other combinations not shown result in operation = ? 10100 ?
? 2008 microchip technology inc. preliminary ds61143e-page 569 pic32mx3xx/4xx bit 15-14 fcksm<1:0>: clock switching and monitor selection configuration bits 1x = clock switching is disabled, fail-safe clock monitor is disabled 01 = clock switching is enabled, fail-safe clock monitor is disabled 00 = clock switching is enabled, fail-safe clock monitor is enabled bit 13-12 fpbdiv<1:0>: peripheral bus clock divisor default value bits 11 = pbclk is sysclk divided by 8 10 = pbclk is sysclk divided by 4 01 = pbclk is sysclk divided by 2 00 = pbclk is sysclk divided by 1 bit 11 reserved: write ? 1 ? bit 10 osciofnc: clko enable configuration bit 1 = clko output signal active on the osco pin; primary oscillator must be disabled or configured for the external clock mode (ec) for the clko to be active (poscmd<1:0> = 11 or 00 ) 0 = clko output disabled bit 9-8 poscmd<1:0>: primary oscillator configuration bits 11 = primary oscillator disabled 10 = hs oscillator mode selected 01 = xt oscillator mode selected 00 = external clock mode selected bit 7 ieso: internal external switchover bit 1 = internal external switchover mode enabled (two-speed start-up enabled) 0 = internal external switchover mode disabled (two-speed start-up disabled) bit 6 reserved: write ? 1 ? bit 5 fsoscen: secondary oscillator enable bit 1 = enable secondary oscillator 0 = disable secondary oscillator bit 4-3 reserved: write ? 1 ? bit 2-0 fnosc<2:0>: oscillator selection bits 000 = fast rc oscillator (frc) 001 = fast rc oscillator with divide-by-n with pll module (frcdiv+pll) 010 = primary oscillator (xt, hs, ec) (1) 011 = primary oscillator with pll module (xt+pll, hs+pll, ec+pll) 100 = secondary oscillator (sosc) 101 = low-power rc oscillator (lprc) 110 = frcdiv16 fast rc oscillator with fixed divide-by-16 postscaler 111 = fast rc oscillator with divide-by-n (frcdiv) note 1: do not disable posc (poscmd = 00 ) when using this oscillator source. register 27-2: devcfg1: device configuration word 1 (continued)
pic32mx3xx/4xx ds61143e-page 570 preliminary ? 2008 microchip technology inc. register 27-3: devcfg2: de vice configuration word 2 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 ? ? ? ? ? ? ? ? bit 31 bit 24 r-1 r-1 r-1 r-1 r-1 r/p-1 r/p-1 r/p-1 ? ? ? ? ? fpllodiv<2:0> bit 23 bit 16 r/p-1 r-1 r-1 r-1 r-1 r/p-1 r/p-1 r/p-1 fupllen ? ? ? ? fupllidiv<2:0> bit 15 bit 8 r-1 r/p-1 r/p-1 r/p-1 r-1 r/p-1 r/p-1 r/p-1 ? fpllmult<2:0> ? fpllidiv<2:0> bit 7 bit 0 legend: r = readable bit w = writable bit p = programmable bit r = reserved bit u = unimplemented bit -n = bit value at por: (?0?, ?1?, x = unknown) bit 31-19 reserved: write ? 1 ? bit 18-16 fpllodiv[2:0]: default postscaler for pll bits 111 = pll output divided by 256 110 = pll output divided by 64 101 = pll output divided by 32 100 = pll output divided by 16 011 = pll output divided by 8 010 = pll output divided by 4 001 = pll output divided by 2 000 = pll output divided by 1 bit 15 fupllen: usb pll enable bit 1 = enable usb pll 0 = disable and bypass usb pll bit 14-11 reserved: write ? 1 ? bit 10-8 fupllidiv[2:0]: pll input divider bits 111 = 12x divider 110 = 10x divider 101 = 6x divider 100 = 5x divider 011 = 4x divider 010 = 3x divider 010 = 3x divider 001 = 2x divider 000 = 1x divider bit 7 reserved: write ? 1 ?
? 2008 microchip technology inc. preliminary ds61143e-page 571 pic32mx3xx/4xx bit 6-4 fpllmult[2:0]: pll multiplier bits 111 = 24x multiplier 110 = 21x multiplier 101 = 20x multiplier 100 = 19x multiplier 011 = 18x multiplier 010 = 17x multiplier 001 = 16x multiplier 000 = 15x multiplier bit 3 reserved: write ? 1 ? bit 2-0 fpllidiv[2:0]: pll input divider bits 111 = 12x divider 110 = 10x divider 101 = 6x divider 100 = 5x divider 011 = 4x divider 010 = 3x divider 001 = 2x divider 000 = 1x divider register 27-3: devcfg2: device configuration word 2 (continued)
pic32mx3xx/4xx ds61143e-page 572 preliminary ? 2008 microchip technology inc. register 27-4: devcfg3: de vice configuration word 3 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 ? ? ? ? ? ? ? ? bit 31 bit 24 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 ? ? ? ? ? ? ? ? bit 23 bit 16 r/p-x r/p-x r/p-x r/p-x r/p-x r/p-x r/p-x r/p-x userid15 userid14 userid13 userid12 userid11 userid10 userid9 userid8 bit 15 bit 8 r/p-x r/p-x r/p-x r/p-x r/p-x r/p-x r/p-x r/p-x userid7 userid6 userid5 userid4 userid3 userid2 userid1 userid0 bit 7 bit 0 legend: r = readable bit w = writable bit p = programmable bit r = reserved bit u = unimplemented bit -n = bit value at por: (?0?, ?1?, x = unknown) bit 31-16 reserved: write ? 1 ? bit 15-0 userid<15:0>: this is a 16-bit value that is user defined and is readable via icsp? and jtag
? 2008 microchip technology inc. preliminary ds61143e-page 573 pic32mx3xx/4xx register 27-5: devid: device id register r r r r r-0 r-0 r-0 r-0 ver11 ver10 ver9 ver8 ver7 ver6 ver5 ver4 bit 31 bit 24 r-1 r-0 r-0 r-1 r r r r ver3 ver2 ver1 ver0 dev7 dev6 dev5 dev4 bit 23 bit 16 r r r r r-0 r-0 r-0 r-0 dev3 dev2 dev1 dev0 manid11 manid10 manid9 manid8 bit 15 bit 8 r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-1 manid7 manid6 manid5 mani d4 manid3 manid2 manid1 1 bit 7 bit 0 legend: r = readable bit w = writable bit p = programmable bit r = reserved bit u = unimplemented bit -n = bit value at por: (?0?, ?1?, x = unknown) bit 31-20 ver<11:0>: revision identifier bits bit 19-12 devid<7:0>: device id 78h = pic32mx460f512l 74h = pic32mx460f256l 6dh = pic32mx440f128l 56h = pic32mx440f512h 52h = pic32mx440f256h 4dh = pic32mx440f128h 42h = pic32mx420f032h 38h = pic32mx360f512l 34h = pic32mx360f256l 2dh = pic32mx340f128l 2ah = pic32mx320f128l 16h = pic32mx340f512h 12h = pic32mx340f256h 0dh = pic32mx340f128h 0ah = pic32mx320f128h 06h = pic32mx320f064h 02h = pic32mx320f032h bit 11-1 manid<11:0>: jedec manufacturer?s identification code for microchip technology inc. bit 0 fixed value: read as ? 1 ?
pic32mx3xx/4xx ds61143e-page 574 preliminary ? 2008 microchip technology inc. 27.1 device configuration in pic32mx3xx/4xx devices, the configuration words select various device configurations. these configuration words are implemented as volatile mem- ory registers and must be loaded from the nonvolatile programmed configuration data mapped in the last four words (32-bit x 4 words) of boot flash memory, devcfg0-devcfg3. these are the four locations an external programming device programs with the appro- priate configuration data (see table 27-3). on power-on reset (por) or any reset, the configu- ration words are copied from boot flash memory to their corresponding configuration registers. a configu- ration bit can only be programmed = 0 (unprogrammed state = 1 ). during programming, a configuration word can be programmed a maximum of two times before a page erase must be performed. after programming the configuration words, the user should reset the device to ensure the configuration registers are reloaded with the new programmed data. 27.1.1 configuration register protection to prevent inadvertent configuration bit changes dur- ing code execution, all programmable configuration bits are write-once. after a bit is initially programmed during a power cycle, it cannot be written to again. changing a device configuration requires changes to the configuration data in the boot flash memory and power to the device be cycled. to ensure the 128-bit data integrity, a comparison is continuously made between each configuration bit and its stored complement. if a mismatch is detected, a configuration mismatch reset is generated, causing a device reset. 27.2 device code protection the pic32mx features a single device code protection bit, cp that when programmed = 0 , protects boot flash and program flash from being read or modified by an external programming device. when code protection is enabled, only the device id registers is available to be read by an external programmer. boot flash and pro- gram flash memory are not protected from self-pro- gramming during program execution when code protection is enabled. see section 27.3 ?program write protection (pwp)? . 27.3 program write protection (pwp) in addition to a device code protection bit, the pic32mx also features write protection bits to prevent boot flash and program flash memory regions from being written during code execution. boot flash memory is write protected with a single configuration bit, bwp (devcfg0<24>), when programmed = 0 . program flash memory can be write-protected entirely or in selectable page sizes using configuration bits pwp<7:0> (devcfg0<19:12>). a page of program flash memory is 4096 bytes (1024 words). the pwp bits represent the one?s complement of the number of protected pages. for example, programming pwp bits = 0xff selects 0 pages to be write-protected, effec- tively disabling the program flash write protection. pro- gramming pwp bits = 0xfe selects the first page to be write protected. when enabled, the write-protected memory range is inclusive from the beginning of pro- gram flash memory (0xbd00_0000) up through the selected page. refer to table 27-4. table 27-3: devcfg locations configuration word address devcfg0 0xbfc0_2ffc devcfg1 0xbfc0_2ff8 devcfg2 0xbfc0_2ff4 devcfg3 0xbfc0_2ff0 note: the pwp bits represent the one?s complement of the number of protected pages.
? 2008 microchip technology inc. preliminary ds61143e-page 575 pic32mx3xx/4xx the amount of program flash memory available for write protection depends on the family device variant. table 27-4: flash program memory write-protect ranges pwp bit value range size (kbytes) write protected memory ranges (1) 0xff 0 disabled 0xfe 4 0xbd00_0fff 0xfd 8 0xbd00_1fff 0xfc 12 0xbd00_2fff 0xfb 16 0xbd00_3fff 0xfa 20 0xbd00_4fff 0xf9 24 0xbd00_5fff 0xf8 28 0xbd00_6fff 0xf7 32 0xbd00_7fff 0xf6 36 0xbd00_8fff 0xf5 40 0xbd00_9fff 0xf4 44 0xbd00_afff 0xf3 48 0xbd00_bfff 0xf2 52 0xbd00_cfff 0xf1 56 0xbd00_dfff 0xf0 60 0xbd00_efff 0xef 64 0xbd00_ffff ... 0x7f 512 0xbd07_ffff note 1: write-protected memory range is inclusive from 0xbd00_0000.
pic32mx3xx/4xx ds61143e-page 576 preliminary ? 2008 microchip technology inc. 27.4 on-chip voltage regulator all pic32mx3xx/4xx device?s core and digital logic are designed to operate at a nominal 1.8v. to simplify system designs, most devices in the pic32mx3xx/4xx incorporate an on-chip regulator providing the required core logic voltage from v dd . the internal 1.8v regulator is controlled by the envreg pin. tying this pin to v dd enables the regu- lator, which in turn provides power to the core. a low esr capacitor (such as tantalum) must be connected to the v ddcore /v cap pin (figure 27-1). this helps to maintain the stability of the regulator. the recom- mended value for the filer capacitor is provided in section 30.1 ?dc characteristics? . tying the envreg pin to v ss disables the regulator. in this case, separate power for the core logic at a nomi- nal 1.8v must be supplied to the device on the v ddcore /v cap pin. alternatively, the v ddcore /v cap and v dd pins can be tied together to operate at a lower nominal voltage. refer to figure 27-1 for possible configurations. 27.4.1 on-chip regulator and por when the voltage regulator is enabled, it takes approxi- mately 10 s for it to generate output. during this time, designated as t startup , code execution is disabled. t startup is applied every time the device resumes operation after any power-down, including sleep mode. if the regulator is disabled, a separate power-up timer (pwrt) is automatically enabled. the pwrt adds a fixed delay of 64 ms nominal delay at device start-up. 27.4.2 on-chip regulator and bor when the on-chip regulator is enabled, pic32mx3xx/4xx devices also have a simple brown- out capability. if the voltage supplied to the regulator is inadequate to maintain a regulated level, the regulator reset circuitry will generate a brown-out reset. this event is captured by the bor flag bit (rcon<1>). the brown-out voltage levels are specific in section 30.1 ?dc characteristics? . 27.4.3 power-up requirements the on-chip regulator is designed to meet the power-up requirements for the device. if the application does not use the regulator, then strict power-up conditions must be adhered to. while powering up, v ddcore must never exceed v dd by 0.3 volts. figure 27-1: conne ctions for the on-chip regulator v dd envreg v ddcore /v cap v ss pic32mx 3.3v (1) 1.8v (1) v dd envreg v ddcore /v cap v ss pic32mx c efc 3.3v regulator enabled (envreg tied to v dd ): regulator disabled (envreg tied to ground): note 1: these are typical operating voltages. refer to section 30.1 ?dc characteristics? for the full operating ranges of v dd and v ddcore . (10 f typ)
? 2008 microchip technology inc. preliminary ds61143e-page 577 pic32mx3xx/4xx 28.0 programming and diagnostics pic32mx3xx/4xx devices provide a complete range of programming and diagnostic features that can increase the flexibility of any application using them. these features allow system designers to include: ? simplified field programmability using two-wire in- circuit serial programming? (icsp?) interfaces ? debugging using icsp ? programming and debugging capabilities using the ejtag extension of jtag ? jtag boundary scan testing for device and board diagnostics pic32mx devices incorporate two programming and diagnostic modules, and a trace controller, that provide a range of functions to the application developer. they are summarized in table 28-1. figure 28-1: block diagram of programming, debugging, and trace ports note: this data sheet summarizes the features of the pic32mx3xx/4xx of devices. it is not intended to be a comprehensive reference source. refer to the ?pic32mx family reference manual? (ds61132) for a detailed description of this peripheral. tdi tdo tck tms jtag controller icsp? controller core jtagen debug<1:0> instruction trace controller debug<1:0> icesel pgc1 pgd1 pgc2 pgd2 trclk trd0 trd1 trd2 trd3 table 28-1: comparison of pic32mx3xx /4xx programming and diagnostic features functions pins used interface boundary scan tdi, tdo, tms and tck pins jtag programming and debugging tdi, tdo, tms and tck pins ejtag programming and debugging pgcx and pgdx pins icsp?
pic32mx3xx/4xx ds61143e-page 578 preliminary ? 2008 microchip technology inc. 28.1 control registers the programming and diagnostics module consists of the following special function registers (sfrs): ? ddpcon: control register for the diagnostic module ? devcfg0: device configuration register the following table summarizes all programming and diagnostics related registers. corresponding registers appear after the summary, followed by a detailed description of each register. table 28-3: device config uration register summary table 28-2: programming a nd diagnostics sfr summary virtual address name bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 bf80_f200 ddpcon 31:24 ? ? ? ? ? ? ? ? 23:16 ? ? ? ? ? ? ? ? 15:8 ? ? ? ? ? ? ? ? 7:0 ddpusb ddpu1 ddpu2 ddpspi1 jtagen troen ? ? virtual address name bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 bfc0_2ffc devcfg0 7:0 ? ? ? ? icesel ? debug1 debug0
? 2008 microchip technology inc. preliminary ds61143e-page 579 pic32mx3xx/4xx register 28-1: ddpcon: debug data port control register r-x r-x r-x r-x r-x r-x r-x r-x ? ? ? ? ? ? ? ? bit 31 bit 24 r-x r-x r-x r-x r-x r-x r-x r-x ? ? ? ? ? ? ? ? bit 23 bit 16 r-x r-x r-x r-x r-x r-x r-x r-x ? ? ? ? ? ? ? ? bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-1 r/w-0 r-x r-x ddpusb ddpu1 ddpu2 ddpspi1 jtagen troen ? ? bit 7 bit 0 legend: r = readable bit w = writable bit p = programmable bit r = reserved bit u = unimplemented bit -n = bit value at por: (?0?, ?1?, x = unknown) bit 31-8 reserved: write ? 0 ?; ignore read bit 7 ddpusb: debug data port enable for usb 1 = usb peripheral ignores usbfrz (u1cnfg1<5>) setting 0 = usb peripheral follows usbfrz setting. bit 6 ddpu1: debug data port enable for uart1 bit 1 = uart1 peripheral ignores frz (u1mode<14>) setting 0 = uart1 peripheral follows frz setting bit 5 ddpu2: debug data port enable for uart2 bit 1 = uart2 peripheral ignores frz (u2mode<14) setting 0 = uart2 peripheral follows frz setting bit 4 ddpspi1: debug data port enable for spi1 bit 1 = spi1 peripheral ignores frz (spi1con<14>) setting 0 = spi1 peripheral follows frz setting bit 3 jtagen: jtag port enable bit 1 = enable jtag port 0 = disable jtag port bit 2 troen: trace output enable bit 1 = enable trace port 0 = disable trace port bit 1-0 reserved: write ? 1 ?; ignore read
pic32mx3xx/4xx ds61143e-page 580 preliminary ? 2008 microchip technology inc. register 28-2: devcfg0: devi ce configuration register (1) r-1 r-1 r-1 r/p-1 r-1 r-1 r-1 r/p-1 ? ? ? cp ? ? ? bwp bit 31 bit 24 r-1 r-1 r-1 r-1 r/p-1 r/p-1 r/p-1 r/p-1 ? ? ? ? pwp19 pwp18 pwp17 pwp16 bit 23 bit 16 r/p-1 r/p-1 r/p-1 r/p-1 r-1 r-1 r-1 r-1 pwp15 pwp14 pwp13 pwp12 ? ? ? ? bit 15 bit 8 r-1 r-1 r-1 r-1 r/p-1 r-1 r/p-1 r/p-1 ? ? ? ? icesel ? debug1 debug0 bit 7 bit 0 legend: r = readable bit w = writable bit p = programmable bit r = reserved bit u = unimplemented bit -n = bit value at por: (?0?, ?1?, x = unknown) bit 3 icesel: in-circuit emulator/debugger communication channel select bit 1 = in-circuit emulator uses emuc2/emud2 pins; in-circuit debugger uses pgc2/pgd2 0 = in-circuit emulator uses emuc1/emud1 pins; in-circuit debugger uses pgc1/pgd1 bit 1-0 debug<1:0>: background debugger enable bits (forced to ? 11 ? if code-protect is enabled) 11 = in-circuit emulator/debugger disabled 10 = in-circuit emulator/debugger enabled 01 = reserved (same as ? 11 ? setting) 00 = reserved (same as ? 11 ? setting) note 1: this summary table contains partial register definitions that only pertain to the debug peripheral. refer to the pic32mx family reference manual (ds61132) for a detailed description of these registers.
? 2008 microchip technology inc. preliminary ds61143e-page 581 pic32mx3xx/4xx 28.2 operation the pic32mx3xx/4xx of devices has multiple programming and debugging options including: ? in-circuit serial programming via icsp ? in-circuit programming ejtag ? debugging via icsp ? debugging via ejtag ? special debug modes for select communication peripherals ? boundary scan 28.2.1 device programming options 28.2.1.1 in-circuit serial programming icsp is microchip?s proprietary solution to providing microcontroller programming in the target application. icsp is also the most direct method to program the device, whether the controller is embedded in a system or loaded into a device programmer. 28.2.1.2 icsp interface icsp uses two pins as the core of its interface. the programming data (pgd) line functions as both an input and an output, allowing programming data to be read in and device information to be read out on com- mand. the programming clock (pgc) line is used to clock in data and control the overall process. pic32mx3xx/4xx devices have more than one pair of pgc and pgd pins; these are multiplexed with other i/o or peripheral functions. individual icsp pin pairs are indicated by number (e.g., pgc1/pgd1, etc.), and are generically referred to as ?pgcx? and ?pgdx?. the multiple pgcx/pgdx pairs provide additional flexibility in system design by allowing users to incorporate icsp on the pair of pins that is least constrained by the circuit design. all pgcx and pgdx pins are functionally tied together and behave identically, and any one pair can be used for successful device programming. the only limitation is that both pins from the same pair must be used. in addition to the pgcx and pgdx pins, icsp requires that all voltage supply (including voltage regulator pin envreg) and ground pins on the device must be con- nected. the mclr pin, which is used with pgcx to enter and control the programming process, must also be connected to the programmer. a typical in-circuit serial programming connection is shown in figure 28-2. figure 28-2: typical in-circuit serial programming? connection 28.2.1.3 icsp operation icsp uses a combination of internal hardware and external control to program the target device. program- ming data and instructions are provided on pgd. icsp uses a special set of commands to control the overall process, combined with standard pic32mx3xx/4xx instructions to execute the actual writing of the program memory. pgd also returns data to the external programmer when responding to queries. users who are interested in a more detailed description, or who are considering designing their own programming interface for pic32mx3xx/4xx devices, should consult the appropriate pic32mx3xx/4xx device programming specification. 28.2.1.4 enhanced in-circuit serial programming the enhanced in-circuit serial programming (icsp) protocol is an extension of the original icsp. it uses the same physical interface as the original, but changes the location and execution of programming control to a software application written to the pic32mx3xx/4xx device. use of enhanced icsp results in significant decrease in overall programming time. for additional information on enhanced icsp and the program executive, refer to the appropriate pic32mx3xx/4xx device programming specification. note: the following sections provide a brief overview of each programming option. for more detailed information, refer to ? pic32mx flash programming specifica- tion ? (ds61145). note: for all device programming options, a minimum v dd requirement for flash erase and programming operations is required. refer to section 30.1 ?dc characteris- tics? for details. icsp? pic32mx v ss v dd mclr /v pp pgcx pgdx v ss v dd v pp clk data i/o
pic32mx3xx/4xx ds61143e-page 582 preliminary ? 2008 microchip technology inc. 28.2.1.5 ejtag device programming using the jtag interface the jtag interface can also be used to program pic32mx3xx/4xx devices in their target applications. using ejtag with the jtag interface allows application designers to include a dedicated test and programming port into their applications, with a single 4-pin interface, without imposing the circuit constraints that the icsp interface may require. 28.2.1.6 enhanced ejtag programming using the jtag interface enhanced ejtag programming uses the standard jtag interface but uses a programming executive writ- ten to ram. use of the programming executive with the jtag interface provides a significant improvement in programming speed. 28.2.2 debugging 28.2.2.1 icsp and in-circuit debugging icsp also provides a hardware channel for the in-cir- cuit debugger (icd) which allows externally controlled debugging of software. using the appropriate hardware interface and software environment, users can force the device to single step through its code, track the actual content of multiple registers and set software breakpoints. the active icsp debugger port is selected by the icesel configuration bit. 28.2.2.2 ejtag debugging the industry standard ejtag interface allows third party ejtag tools to be used for debugging. using the ejtag interface, memory and registers can be viewed and modified. breakpoints can be set and the program execution may be stopped, started or single stepped. 28.2.3 special debug modes for select communications peripherals to aid in debugging applications certain i/o peripherals have a user-controllable bit to override the freeze func- tion in the peripheral. this allows the module to continue to send any data, buffered within the periph- eral, even when a debugger attempts to halt the periph- eral. the debug mode control bits for these peripherals are contained in the ddpcon register. 28.2.4 jtag boundary scan the jtag boundary scan method is the process of adding a shift register stage adjacent to each of the component?s i/o pins. this permits signals at the com- ponent boundaries to be controlled and observed, using a defined set of scan test principles. an external tester or controller provides instructions and reads the results in a serial fashion. the external device also provides common clock and control signals. depending on the implementation, access to all test signals is provided through a standardized, 4-pin interface. a typical application incorporating the jtag boundary scan interface is shown in figure 28-3. in this example, a pic32mx3xx/4xx microcontroller is daisy-chained to a second jtag compliant device. note that the tdi line from the external tester supplies data to the tdi pin of the first device in the chain (in this case, the micro- controller). the resulting test data for this two-device chain is provided from the tdo pin of the second device to the tdo line of the tester. this section describes the jtag module and its gen- eral use. users interested in using the jtag interface for device programming should refer to the appropriate pic32mx3xx/4xx device programming specification for more information.
? 2008 microchip technology inc. preliminary ds61143e-page 583 pic32mx3xx/4xx figure 28-3: overview of pic32mx3xx/4xx-based jtag compliant application showing daisy-chaining of components in pic32mx3xx/4xx devices, the hardware for the jtag boundary scan is implemented as a peripheral module (i.e., outside of the cpu core) with additional integrated logic in all i/o ports. a logical block diagram of the jtag module is shown in figure 28-1. it consists of the following key elements: ? tap interface pins (tdi, tms, tck and tdo) ? tap controller ? instruction shift register and instruction register (ir) ? data registers (dr) 28.2.4.1 test access port (tap) and tap controller the test access port (tap) on the pic32mx3xx/4xx device is a general purpose port that provides test access to many built-in support functions and test logic defined in ieee 1149.1. the tap is enabled by the jtagen bit in the ddpcon register. the tap is enabled, jtagen = 1 , by default when the device exits power-on-reset (por) or any device reset. once enabled, the designated i/o pins become dedicated tap pins. the pic32mx3xx/4xx implements a 4-pin jtag interface with these pins: ? tck (test clock input): provides the clock for test logic. ? tms (test mode select input): used by the tap to control test operations. ? tdi (test data input): serial input for test instructions and data. ? tdo (test data output): serial output for test instructions and data. 28.2.4.2 jtag registers the jtag module uses a number of registers of vari- ous sizes as part of its operation. in terms of bit count, most of the jtag registers are single bit register cells, integrated into the i/o ports. regardless of their loca- tion within the module, none of the jtag registers are located within the device data memory space, and cannot be directly accessed by the user in normal operating modes. tdi tdo tck tms tdi tdo tck tms tdi tdo tck tms jtag controller pic32mx (or other jtag compliant device) pic32mx device-based application jtag connector pic32mx note: power and ground connections not shown.
pic32mx3xx/4xx ds61143e-page 584 preliminary ? 2008 microchip technology inc. 28.2.4.3 instruction shift register and instruction register the instruction shift register is a 5-bit shift register used for selecting the actions to be performed and/or what data registers to be accessed. instructions are shifted in, least significant bit first, and then decoded. a list and description of implemented instructions is given in section 28.2.4.6 ?jtag instructions? . 28.2.4.4 data registers once an instruction is shifted in and updated into the instruction register, the tap controller places certain data registers between the tdi and tdo pins. addi- tional data values can then be shifted into these data registers as needed. the pic32mx3xx/4xx device supports three data registers: ? bypass register: a single bit register which allows the boundary scan test data to pass through the selected device to adjacent devices. the bypass register is placed between the tdi and tdo pins when the bypass instruction is active. ? devid register: a 32-bit part identifier. it consists of an 11-bit manufacturer id assigned by the ieee (29h for microchip technology), device part num- ber and device revision identifier. when the idcode instruction is active, the device id regis- ter is placed between the tdi and tdo pins. the device data id is then shifted out on to the tdo pin, on the next 32 falling edges of tck, after the tap controller is in the shift_dr. ? mchp command shift register: an 8-bit shift register that is placed between the tdi and tdo pins when the mchp_cmd instruction is active. this shift register is used to shift in microchip commands. 28.2.4.5 boundary scan register (bsr) the bsr is a large shift register that is comprised of all the i/o boundary scan cells (bscs), daisy-chained together. each i/o pin has one bsc, each containing 3 bsc registers, an input cell, an output cell and a control cell. when the sample/preload or extest instruc- tions are active, the bsr is placed between the tdi and tdo pins, with the tdi pin as the input and the tdo pin as the output. the size of the bsr depends on the number of i/o pins on the device. for example, the 100-pin pic32mx gen- eral purpose parts have 82 i/o pins. with 3 bsc regis- ters for each of the 82 i/os, this yields a boundary scan register length of 244 bits. this is due to the mclr pin being an input only bsr cell. information on the i/o port pin count of other pic32mx3xx/4xx devices can be found in their specific device data sheets. 28.2.4.6 jtag instructions pic32mx3xx/4xx devices support the mandatory instruction set specified by ieee 1149.1, as well as sev- eral optional public instructions defined in the specifica- tion. these devices also implement instructions that are specific to microchip devices. the mandatory jtag instructions are: ? bypass (0x1f): used for bypassing a device in a test chain; this allows the testing of off-chip circuitry and board level interconnections. ? sample/preload (0x02): captures the i/o states of the component, providing a snapshot of its operation. ? extest (0x06): allows the external circuitry and interconnections to be tested, by either forcing various test patterns on the output pins, or capturing test results from the input pins. microchip has implemented optional jtag instructions and manufacturer-specific jtag commands in pic32mx3xx/4xx devices. please refer to table 28-4, table 28-5, table 28-6 and table 28-7. table 28-4: jtag commands opcode name device integration 0x1f bypass bypasses device in test chain 0x00 highz places device in a high-impedance state, all pins are forced to inputs 0x01 id code shifts out the device?s id code 0x02 sample/preload samples all pins or loads a specific value into output latch 0x06 extest boundary scan
? 2008 microchip technology inc. preliminary ds61143e-page 585 pic32mx3xx/4xx table 28-5: microchip tap ir commands table 28-6: microchip tap 8-bit dr commands table 28-7: ejtag commands opcode name device integration 0x01 mtap_idcode shifts out the device?s id code 0x07 mtap_command configures microchip tap controller for dr commands 0x04 mtap_sw_mtap selects microchip tap controller 0x05 mtap_sw_etap selects ejtag tap controller opcode name device integration 0x00 mchp_status performs nop and returns status 0xd1 mchp_asert_rst requests assert device reset 0xd0 mchp_de_assert_rst requests deassert device reset 0xfc mchp_erase performs a chip erase 0xfe mchp_flash_enable enables fetches and loads to the flash from the cpu 0xfd mchp_flash_disable disables fetches and loads to the flash from the cpu 0xff mchp_read_config forces device to reread the configuration settings and initialize accordingly opcode name device integration data length for the following dr 0x00 not used 0x01 idcode selects the device?s id code register 32 bits 0x02 not used 0x03 impcode selects implementation register 0x04 (2) mtap_sw_mtap selects microchip tap controller 0x05 (2) mtap_sw_etap selects ejtag tap controller (1) 0x06-0x07 not used 0x08 address selects the address register 32 bits 0x09 data selects the data register 32 bits 0x0a control selects the ejtag control register (1) 32 bits 0x0b all selects the address, data, ejtag control register (1) 96 bits 0x0c ejtagboot forces the cpu to take a debug exception after boot 1 bit 0x0d normalboot makes the cpu execute the reset handler after a boot 1 bit 0x0e fastdata selects the data and fast data registers 1 bit 0x0f-0x1b reserved 0x1c-0xfe not used 0xff selects the bypass register note 1: for complete information about ejtag commands and protocol, refer to the ejtag specification available on mips technologies web site, www.mips.com. 2: not ejtag commands but are recognized by the microchip implementation.
pic32mx3xx/4xx ds61143e-page 586 preliminary ? 2008 microchip technology inc. 28.2.5 boundary scan testing (bst) boundary scan testing (bst) is the method of control- ling and observing the boundary pins of the jtag com- pliant device, like those of the pic32mx3xx/4xx, utilizing software control. bst can be used to test con- nectivity between devices by daisy-chaining jtag compliant devices to form a single scan chain. several scan chains can exist on a pcb to form multiple scan chains. these multiple scan chains can then be driven simultaneously to test many components in parallel. scan chains can contain both jtag compliant devices and non-jtag compliant devices. a key advantage of bst is that it can be implemented without physical test probes; all that is needed is a 4- wire interface and an appropriate test platform. since jtag boundary scan has been available for many years, many software tools exist for testing scan chains without the need for extensive physical probing. the main drawback to bst is that it can only evaluate digital signals and circuit continuity; it cannot measure input or output voltage levels or currents. 28.2.5.1 related jtag files to implement bst, all jtag test tools will require a boundary scan description language (bsdl) file. bsdl is a subset of vhdl (vhsic hardware descrip- tion language), and is described as part of ieee. 1149.1. the device-specific bsdl file describes how the standard is implemented on a particular device and how it operates. the bsdl file for a particular device includes the following: ? the pinout and package configuration for the particular device ? the physical location of the tap pins ? the device id register and the device id ? the length of the instruction register ? the supported bst instructions and their binary codes ? the length and structure of the boundary scan register ? the boundary scan cell definition device-specific bsdl files are available at microchip?s web site, www.microchip.com. the name for each bsdl file is the device name and silicon revision?for example, pic32mx3xx/4xx 320f128l_a2.bsd is the bsdl file for pic32mx3xx/4xx 320f128l, silicon revision a2. 28.3 interrupts programming and debugging operations are not performed during code execution and are therefore not affected by interrupts. trace operations will report the change in code execution when a interrupt occurs but the trace controller is not affected by interrupts. 28.4 i/o pins in order to interface the numerous programming and debugging option available and still provide peripheral access to the pins, the pins are multiplexed with periph- erals. table describes the function of the programming and debug related pins. table 28-8: programming a nd debugging pin functions pin name function description comments boundary scan mode program mode debug mode trace mode mclr mclr master clear used to enter icsp? mode and to override jtagen (ddpcon<3>) pgc1/emuc1 general purpose i/o or peripheral pgc1 ? icsp? clock selected by icesel (devcfg0<3>) and debug configuration bits (devcfg0<1:0>) ? emuc1 pgd1/emud1 pgd1 ? icsp? data emud1 pgc2/emuc2 general purpose i/o or peripheral pgc2 ? alternate icsp? clock emuc1 pgd2/emud2 pgd2 ? alternate icsp? data emud1
? 2008 microchip technology inc. preliminary ds61143e-page 587 pic32mx3xx/4xx trclk general purpose i/o or peripheral trclk trace clock controlled by troen bit (ddpcon<2>) trd0 trd0 trace data trd1 trd1 trd2 trd2 trd3 trd3 tms tms tms tms tms jtag test mode select tck tck tck tck tck jtag clock controlled by jtagen bit (ddpcon<3>) tdo tdo tdo tdo tdo jtag data out tdi tdi tdi tdi tdi jtag data in table 28-8: programming a nd debugging pin functions pin name function description comments boundary scan mode program mode debug mode trace mode
pic32mx3xx/4xx ds61143e-page 588 preliminary ? 2008 microchip technology inc. notes:
? 2008 microchip technology inc. preliminary ds61143e-page 589 pic32mx3xx/4xx 29.0 development support the pic ? microcontrollers are supported with a full range of hardware and software development tools: ? integrated development environment - mplab ? ide software ? assemblers/compilers/linkers - mpasm tm assembler - mplab c18 and mplab c30 c compilers -mplink tm object linker/ mplib tm object librarian - mplab asm30 assembler/linker/library ? simulators - mplab sim software simulator ?emulators - mplab ice 2000 in-circuit emulator - mplab real ice? in-circuit emulator ? in-circuit debugger - mplab icd 2 ? device programmers - picstart ? plus development programmer - mplab pm3 device programmer - pickit? 2 development programmer ? low-cost demonstration and development boards and evaluation kits 29.1 mplab integrated development environment software the mplab ide software brings an ease of software development previously unseen in the 8/16-bit micro- controller market. the mplab ide is a windows ? operating system-based application that contains: ? a single graphical interface to all debugging tools - simulator - programmer (sold separately) - emulator (sold separately) - in-circuit debugger (sold separately) ? a full-featured editor with color-coded context ? a multiple project manager ? customizable data windows with direct edit of contents ? high-level source code debugging ? visual device initializer for easy register initialization ? mouse over variable inspection ? drag and drop variables from source to watch windows ? extensive on-line help ? integration of select third party tools, such as hi-tech software c compilers and iar c compilers the mplab ide allows you to: ? edit your source files (either assembly or c) ? one touch assemble (or compile) and download to pic mcu emulator and simulator tools (automatically updates all project information) ? debug using: - source files (assembly or c) - mixed assembly and c - machine code mplab ide supports multiple debugging tools in a single development paradigm, from the cost-effective simulators, through low-cost in-circuit debuggers, to full-featured emulators. this eliminates the learning curve when upgrading to tools with increased flexibility and power.
pic32mx3xx/4xx ds61143e-page 590 preliminarypreliminary ? 2008 microchip technology inc. 29.2 mpasm assembler the mpasm assembler is a full-featured, universal macro assembler for all pic mcus. the mpasm assembler generates relocatable object files for the mplink object linker, intel ? standard hex files, map files to detail memory usage and symbol reference, absolute lst files that contain source lines and generated machine code and coff files for debugging. the mpasm assembler features include: ? integration into mplab ide projects ? user-defined macros to streamline assembly code ? conditional assembly for multi-purpose source files ? directives that allow complete control over the assembly process 29.3 mplab c18 and mplab c30 c compilers the mplab c18 and mplab c30 code development systems are complete ansi c compilers for microchip?s pic18 and pic24 families of microcon- trollers and the dspic30 and dspic33 family of digital signal controllers. these compilers provide powerful integration capabilities, superior code optimization and ease of use not found with other compilers. for easy source level debugging, the compilers provide symbol information that is optimized to the mplab ide debugger. 29.4 mplink object linker/ mplib object librarian the mplink object linker combines relocatable objects created by the mpasm assembler and the mplab c18 c compiler. it can link relocatable objects from precompiled libraries, using directives from a linker script. the mplib object librarian manages the creation and modification of library files of precompiled code. when a routine from a library is called from a source file, only the modules that contain that routine will be linked in with the application. this allows large libraries to be used efficiently in many different applications. the object linker/library features include: ? efficient linking of single libraries instead of many smaller files ? enhanced code maintainability by grouping related modules together ? flexible creation of libraries with easy module listing, replacement, deletion and extraction 29.5 mplab asm30 assembler, linker and librarian mplab asm30 assembler produces relocatable machine code from symbolic assembly language for dspic30f devices. mplab c30 c compiler uses the assembler to produce its object file. the assembler generates relocatable object files that can then be archived or linked with other relocatable object files and archives to create an executable file. notable features of the assembler include: ? support for the entire dspic30f instruction set ? support for fixed-point and floating-point data ? command line interface ? rich directive set ? flexible macro language ? mplab ide compatibility 29.6 mplab sim software simulator the mplab sim software simulator allows code development in a pc-hosted environment by simulat- ing the pic mcus and dspic ? dscs on an instruction level. on any given instruction, the data areas can be examined or modified and stimuli can be applied from a comprehensive stimulus controller. registers can be logged to files for further run-time analysis. the trace buffer and logic analyzer display extend the power of the simulator to record and track program execution, actions on i/o, most peripherals and internal registers. the mplab sim software simulator fully supports symbolic debugging using the mplab c18 and mplab c30 c compilers, and the mpasm and mplab asm30 assemblers. the software simulator offers the flexibility to develop and debug code outside of the hardware laboratory environment, making it an excellent, economical software development tool.
? 2008 microchip technology inc. preliminary ds61143e-page 591 pic32mx3xx/4xx 29.7 mplab ice 2000 high-performance in-circuit emulator the mplab ice 2000 in-circuit emulator is intended to provide the product development engineer with a complete microcontroller design tool set for pic microcontrollers. software control of the mplab ice 2000 in-circuit emulator is advanced by the mplab integrated development environment, which allows editing, building, downloading and source debugging from a single environment. the mplab ice 2000 is a full-featured emulator system with enhanced trace, trigger and data monitor- ing features. interchangeable processor modules allow the system to be easily reconfigured for emulation of different processors. the architecture of the mplab ice 2000 in-circuit emulator allows expansion to support new pic microcontrollers. the mplab ice 2000 in-circuit emulator system has been designed as a real-time emulation system with advanced features that are typically found on more expensive development tools. the pc platform and microsoft ? windows ? 32-bit operating system were chosen to best make these features available in a simple, unified application. 29.8 mplab real ice in-circuit emulator system mplab real ice in-circuit emulator system is microchip?s next generation high-speed emulator for microchip flash dsc and mcu devices. it debugs and programs pic ? flash mcus and dspic ? flash dscs with the easy-to-use, powerful graphical user interface of the mplab integrated development environment (ide), included with each kit. the mplab real ice probe is connected to the design engineer?s pc using a high-speed usb 2.0 interface and is connected to the target with either a connector compatible with the popular mplab icd 2 system (rj11) or with the new high-speed, noise tolerant, low- voltage differential signal (lvds) interconnection (cat5). mplab real ice is field upgradeable through future firmware downloads in mplab ide. in upcoming releases of mplab ide, new devices will be supported, and new features will be added, such as software break- points and assembly code trace. mplab real ice offers significant advantages over competitive emulators including low-cost, full-speed emulation, real-time variable watches, trace analysis, complex breakpoints, a ruggedized probe interface and long (up to three meters) interconnection cables. 29.9 mplab icd 2 in-circuit debugger microchip?s in-circuit debugger, mplab icd 2, is a powerful, low-cost, run-time development tool, connecting to the host pc via an rs-232 or high-speed usb interface. this tool is based on the flash pic mcus and can be used to develop for these and other pic mcus and dspic dscs. the mplab icd 2 utilizes the in-circuit debugging capability built into the flash devices. this feature, along with microchip?s in-circuit serial programming tm (icsp tm ) protocol, offers cost- effective, in-circuit flash debugging from the graphical user interface of the mplab integrated development environment. this enables a designer to develop and debug source code by setting breakpoints, single step- ping and watching variables, and cpu status and peripheral registers. running at full speed enables testing hardware and applications in real time. mplab icd 2 also serves as a development programmer for selected pic devices. 29.10 mplab pm3 device programmer the mplab pm3 device programmer is a universal, ce compliant device programmer with programmable voltage verification at v ddmin and v ddmax for maximum reliability. it features a large lcd display (128 x 64) for menus and error messages and a modu- lar, detachable socket assembly to support various package types. the icsp? cable assembly is included as a standard item. in stand-alone mode, the mplab pm3 device programmer can read, verify and program pic devices without a pc connection. it can also set code protection in this mode. the mplab pm3 connects to the host pc via an rs-232 or usb cable. the mplab pm3 has high-speed communications and optimized algorithms for quick programming of large memory devices and incorporates an sd/mmc card for file storage and secure data applications.
pic32mx3xx/4xx ds61143e-page 592 preliminarypreliminary ? 2008 microchip technology inc. 29.11 picstart plus development programmer the picstart plus development programmer is an easy-to-use, low-cost, prototype programmer. it connects to the pc via a com (rs-232) port. mplab integrated development environment software makes using the programmer simple and efficient. the picstart plus development programmer supports most pic devices in dip packages up to 40 pins. larger pin count devices, such as the pic16c92x and pic17c76x, may be supported with an adapter socket. the picstart plus development programmer is ce compliant. 29.12 pickit 2 development programmer the pickit? 2 development programmer is a low-cost programmer and selected flash device debugger with an easy-to-use interface for programming many of microchip?s baseline, mid-range and pic18f families of flash memory microcontrollers. the pickit 2 starter kit includes a prototyping development board, twelve sequential lessons, software and hi-tech?s picc? lite c compiler, and is designed to help get up to speed quickly using pic ? microcontrollers. the kit provides everything needed to program, evaluate and develop applications using microchip?s powerful, mid-range flash memory family of microcontrollers. 29.13 demonstration, development, and evaluation boards a wide variety of demonstration, development, and evaluation boards for various pic mcus and dspic dscs allows quick application development on fully func- tional systems. most boards include prototyping areas for adding custom circuitry and provide application firmware and source code for examination and modification. the boards support a variety of features, including leds, temperature sensors, switches, speakers, rs-232 interfaces, lcd displays, potentiometers, and additional eeprom memory. the demonstration and development boards can be used in teaching environments, for prototyping custom circuits, and for learning about various microcontroller applications. in addition to the picdem? and dspicdem? demon- stration/development board series of circuits, microchip has a line of evaluation kits and demonstration software for analog filter design, k ee l oq ? security ics, can, irda ? , powersmart battery management, seeval ? evaluation system, sigma-delta adc, flow rate sensing, plus many more. check the microchip web page (www.microchip.com) for the complete list of demonstration, development and evaluation kits.
? 2008 microchip technology inc. preliminary ds61143e-page 593 pic32mx3xx/4xx 30.0 electrical characteristics this section provides an overview of pic32mx3xx/4xx electrical characteristics. additional information will be provided in future revisions of this document as it becomes available. absolute maximum ratings for the pic32mx3xx/4xx are listed below. exposure to these maximum rating conditions for extended periods may affect device reliability. functional operation of the device at these or any other conditions above the parameters indicated in the operation listings of this specification is not implied. absolute maximum ratings (1) ambient temperature under bias................................................................................................. ............. .-40c to +85c storage temperature ............................................................................................................ .................. -65c to +150c voltage on v dd with respect to v ss ......................................................................................................... -0.3v to +4.0v voltage on any combined analog and digital pin and mclr , with respect to v ss ......................... -0.3v to (v dd + 0.3v) voltage on any digital only pin with respect to v ss .................................................................................. -0.3v to +5.5v voltage on v ddcore with respect to v ss ................................................................................................... -0.3v to 2.0v maximum current out of v ss pin(s) .......................................................................................................................3 00 ma maximum current into v dd pin(s) (note 1) ............................................................................................................300 ma maximum output current sunk by any i/o pin..................................................................................... .....................25 ma maximum output current sourced by any i/o pin .................................................................................. ..................25 ma maximum current sunk by all ports .............................................................................................. .........................200 ma maximum current sourced by all ports (note 1) ....................................................................................................200 ma note 1: maximum allowable current is a function of device maximum power dissipation (see table 30-2). note: stresses above those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. exposure to maximum rating conditions for extended periods may affect device reliability.
pic32mx3xx/4xx ds61143e-page 594 preliminary ? 2008 microchip technology inc. 30.1 dc characteristics table 30-1: operating mips vs. voltage characteristic v dd range (in volts) temp. range (in c) max. frequency pic32mx3xx/4xx dc5 2.3-3.6v -40c to +85c 80 mhz (1) note 1: 40 mhz maximum for pic32mx 40mhz family variants. table 30-2: thermal operating conditions rating symbol min. typical max. unit pic32mx3xx/4xx operating junction temperature range t j -40 ? +125 c operating ambient temperature range t a -40 ? +85 c power dissipation: internal chip power dissipation: p int = v dd x (i dd ? s i oh ) p d p int + p i / o w i/o pin power dissipation: i/o = s ({v dd ? v oh } x i oh ) + s (v ol x i ol ) ) maximum allowed power dissipation p dmax (t j ? t a )/ ja w table 30-3: thermal packaging characteristics characteristics symbol typical max. unit notes package thermal resistance, 100-pin tqfp (12x12x1 mm) ja 52.3 ? c/w 1 package thermal resistance, 64-pin tqfp (10x10x1 mm) ja 38.3 ? c/w 1 note 1: junction to ambient thermal resistance, theta- ja ( ja ) numbers are achieved by package simulations. table 30-4: dc temperature and voltage specifications dc characteristics standard operating conditions: 2.3v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial param. no. symbol characteristics min. typical (1) max. units conditions operating voltage dc10 supply voltage v dd 2.3 ? 3.6 v dc12 v dr ram data retention voltage (2) ?1.75?v dc16 v por v dd start voltage to ensure internal power-on reset signal 1.75 ? 1.95 v dc17 s vdd v dd rise rate to ensure internal power-on reset signal 0.05 ? ? v/ms note 1: data in ?typical? column is at 3.3v, 25c unless otherwise stated. parameters are for design guidance only and are not tested. 2: this is the limit to which v dd can be lowered without losing ram data.
? 2008 microchip technology inc. preliminary ds61143e-page 595 pic32mx3xx/4xx table 30-5: dc characteristics: operating current (i dd ) (1) dc characteristics standard operating conditions: 2.3v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial parameter no. typical (3) max. units conditions operating current (i dd ) (2) dc20 ? 13 ma 2.3v 4 mhz dc20a 8.5 ? ma ? dc20b ? 13 ma 3.6v dc20c 4.0 ? ma code executing from sram ? dc21 ? 32 ma 2.3v 20 mhz dc21a 23.5 ? ma ? dc21b ? 32 ma 3.6v dc21c 16.4 ? ma code executing from sram ? dc22 ? 61 ma 2.3v 60 mhz dc22a 48 ? ma ? dc22b ? 61 ma 3.6v dc22c 45 ? ma code executing from sram ? dc23 ? 75 ma 2.3v 80 mhz dc23a 55 ? ma ? dc23b ? 75 ma 3.6v dc23c 55 ? ma code executing from sram ? dc24 ? 97 a -40c 2.3v lprc (31 khz) dc24a ? 129 a +25c dc24b ? 670 a +85c dc25 94 ? a -40c 3.3v dc25a 125 ? a +25c dc25b 302 ? a +85c dc25c 71 ? a code executing from sram dc26 ? 107 a -40c 3.6v dc26a ? 180 a +25c dc26b ? 697 a +85c note 1: a device?s i dd supply current is mainly a function of the operating voltage and frequency. other factors, such as pbclk (peripheral bus clock) frequency, number of peripheral modules enabled, internal code execution pattern, execution from program flash memory vs. sram, i/o pin loading and switching rate, oscillator type as well as temperature can have an impact on the current consumption. 2: the test conditions for i dd measurements are as follows: oscillator mode = ec+pll with osc1 driven by external square wave from rail to rail and pbclk divisor = 1:8. cpu, program flash and sram data mem- ory are operational, program flash memory wait stat es = 7, program cache and prefetch are disabled and sram data memory wait states = 1 . all peripheral modules are disabled (on bit = 0 ). wdt and fscm are disabled. all i/o pins are configured as inputs and pulled to v ss . m clr = v dd . 3: data in ?typical? column is at 3.3v, 25c at specified operating frequency unless otherwise stated. parameters are for design guidance only and are not tested.
pic32mx3xx/4xx ds61143e-page 596 preliminary ? 2008 microchip technology inc. table 30-6: dc characteristics: idle current (i idle ) dc characteristics standard operating conditions: 2.3v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial parameter no. typical (2) max. units conditions idle current (i idle ): core off, clock on base current (1) dc30 ? 5 ma 2.3v 4 mhz dc30a 1.4 ? ma ? dc30b ? 5 ma 3.6v dc31 ? 15 ma 2.3v 20 mhz dc31a 13 ? ma ? dc31b ? 17 ma 3.6v dc32 ? 22 ma 2.3v 60 mhz dc32a 20 ? ma ? dc32b ? 25 ma 3.6v dc33 ? 29 ma 2.3v 80 mhz dc33a 24 ? ma ? dc33b ? 32 ma 3.6v dc34 ? 36 a -40c 2.3v lprc (31 khz) dc34a ? 62 a +25c dc34b ? 392 a +85c dc35 35 ? a -40c 3.3v dc35a 65 ? a +25c dc35b 242 ? a +85c dc36 ? 43 a -40c 3.6v dc36a ? 106 a +25c dc36b ? 414 a +85c note 1: the test conditions for base i dle current measurements are as follows: system clock is enabled and pbclk divisor = 1:8. cpu in idle mode (cpu core halted). only digital peripheral modules are enabled (on bit = 1 ) and being clocked. wdt and fscm are disabled. all i/o pins are configured as inputs and pulled to v ss . m clr = v dd . 2: data in ?typical? column is at 3.3v, 25c unless otherwise stated. parameters are for design guidance only and are not tested.
? 2008 microchip technology inc. preliminary ds61143e-page 597 pic32mx3xx/4xx table 30-7: dc characteristics: power-down current (i pd ) dc characteristics standard operating conditions: 2.3v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial parameter no. typical (2) max. units conditions power-down current (i pd ) (1) dc40 ? 28 a-40c 2.3v base power-down current dc40a ? 28 a+25c dc40b ? 300 a+85c dc40c 39 ? a dc40d ? 70 a-40c 3.6v dc40e ? 70 a+25c dc40g ? 300 (5) a+70c dc40f ? 600 a+85c module differential current dc41 ? 10 a-40c 2.3v watchdog timer current: i wdt (3) dc41a ? 10 a+25c dc41b ? 10 a+85c dc41c 5 ? a dc41d ? 10 a-40c 3.6v dc41e ? 10 a+25c dc41f ? 12 a+85c dc42 ? 10 a-40c 2.3v rtcc + timer1 w/32khz crystal: i rtcc (3) dc42a ? 17 a+25c dc42b ? 37 a+85c dc42c 23 ? a dc42e ? 10 a-40c 3.6v dc42f ? 30 a+25c dc42g ? 44 a+85c dc42 ? 1100 a-40c 2.5v adc: i adc (3,4) dc42a ? 1100 a+25c dc42b ? 1000 a+85c dc42c 880 ? a dc42e ? 1100 a-40c 3.6v dc42f ? 1100 a+25c dc42g ? 1000 a+85c note 1: base i pd is measured with all digital peripheral modules enabled (on bit = 1 ) and being clocked, cpu clock is disabled. all i/os are configured as outputs and pulled low. wdt and fscm are disabled. 2: data in the ?typical? column is at 3.3v, 25c unless otherwise stated. parameters are for design guidance only and are not tested. 3: the current is the additional current consumed when the module is enabled. this current should be added to the base i pd current. 4: test conditions for adc module differential current are as follows: internal adc rc oscillator enabled. 5: data is characterized at +70c and not tested. parameter is for design guidance only.
pic32mx3xx/4xx ds61143e-page 598 preliminary ? 2008 microchip technology inc. table 30-8: dc characteristics: i/o pin input specifications dc characteristics standard operating conditions: 2.3v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial param. no. symbol characteristics min. typical (1) max. units conditions v il input low voltage di10 i/o pins: with ttl buffer v ss ?0.15v dd v ss with schmitt trigger buffer v ss ?0.2v dd v ss di15 mclr v ss ?0.2v dd v di16 osc1 (xt mode) v ss ?0.2v dd v di17 osc1 (hs mode) v ss ?0.2v dd v di18 sdax, sclx v ss ?0.3v dd v smbus disabled di19 sdax, sclx v ss ? 0.8 v smbus enabled v ih input high voltage di20 i/o pins: with analog functions 0.8 v dd ?v dd v digital only 0.8 v dd ?v with ttl buffer 0.25v dd + 0.8 v ?5.5v ss with schmitt trigger buffer 0.8 v dd ?5.5v ss di25 mclr 0.8 v dd ?v dd v di26 osc1 (xt mode) 0.7 v dd ?v dd v di27 osc1 (hs mode) 0.7 v dd ?v dd v di28 sdax, sclx 0.7 v dd ?v dd v smbus disabled di29 sdax, sclx 2.1 ? v dd v smbus enabled, 2.3v v pin v dd di30 i cnpu cnxx pull up current 50 250 400 av dd = 3.3v, v pin = v ss i il input leakage current (2,3) di50 i/o ports ? ? + 1 av ss v pin v dd , pin at high-impedance di51 analog input pins ? ? + 1 av ss v pin v dd , pin at high-impedance di55 mclr ??+ 1 av ss v pin v dd di56 osc1 ? ? + 1 av ss v pin v dd , xt and hs modes note 1: data in ?typical? column is at 3.3v, 25c unless otherwise stated. parameters are for design guidance only and are not tested. 2: the leakage current on the mclr pin is strongly dependent on the applied voltage level. the specified levels represent normal operating conditions. higher leakage current may be measured at different input voltages. 3: negative current is defined as current sourced by the pin.
? 2008 microchip technology inc. preliminary ds61143e-page 599 pic32mx3xx/4xx table 30-9: dc characteristics: i/o pin output specifications dc characteristics standard operating conditions: 2.3v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial param. no. symbol characteristics min. typical (1) max. units conditions v ol output low voltage do10 i/o ports ? ? 0.4 v i ol = 7 ma, v dd = 3.6v ??0.4vi ol = 6 ma, v dd = 2.3v do16 osc2/clko ? ? 0.4 v i ol = 3.5 ma, v dd = 3.6v ??0.4vi ol = 2.5 ma, v dd = 2.3v v oh output high voltage do20 i/o ports 2.4 ? ? v i oh = -12 ma, v dd = 3.6v 1.4 ? ? v i oh = -12 ma, v dd = 2.3v do26 osc2/clko 2.4 ? ? v i oh = -12 ma, v dd = 3.6v 1.4 ? ? v i oh = -12 ma, v dd = 2.3v note 1: data in ?typical? column is at 3.3v, 25c unless otherwise stated. parameters are for design guidance only and are not tested. table 30-10: dc characteristics: program memory dc characteristics standard operating conditions: 2.3v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial param. no. symbol characteristics min. typical (1) max. units conditions program flash memory d130 e p cell endurance 1000 ? ? e/w -40 c to +85 c d131 v pr v dd for read v min ?3.6vv min = minimum operating voltage d132 v pew v dd for erase or write 3.0 ? 3.6 v d134 t retd characteristic retention 20 ? ? year provided no other specifications are violated d135 i ddp supply current during programming ?10 ?ma t ww word write cycle time 20 ? 40 s d136 t rw row write cycle time (2) (128 words per row) 34.5?ms d137 t pe page erase cycle time 20 ? 40 ms t ce chip erase cycle time 20 ? 40 ms note 1: data in ?typical? column is at 3.3v, 25c unless otherwise stated. 2: the minimum sysclk for row programming is 4 mhz. care should be taken to minimize bus activities during row programming, such as suspending any memory-to-memory dma operations. if heavy bus loads are expected, selecting bus matrix arbitration mode 2 (rotating priority) may be necessary. the default arbitration mode is mode 1 (cpu has lowest priority).
pic32mx3xx/4xx ds61143e-page 600 preliminary ? 2008 microchip technology inc. table 30-11: program flash memo ry wait state characteristics dc characteristics standard operating conditions: 2.3v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial required flash wait states sysclk units comments 0 wait state 0 to 30 mhz 1 wait state 31 to 60 2 wait states 61 to 80 note 1: 40 mhz maximum for pic32mx 40mhz family variants. table 30-12: comparator specifications dc characteristics standard operating conditions: 2.3v to 3.6v (unless otherwise stated) operating temperature-40c t a +85c for industrial param. no. symbol characteristics min. typical max. units comments d300 v ioff input offset voltage ? 7.5 25 mv d301 v icm input common mode voltage* 0 ? v dd v d302 cmrr common mode rejection ratio* 55 ? ? db d303 t resp response time* (1) ? 150 400 nsec d304 t mc 2 ov comparator mode change to output valid* ?? 10 s * these parameters are characterized but not tested. note 1: response time measured with one comparator input at (v dd ? 1.5)/2, while the other input transitions from v ss to v dd . table 30-13: voltage reference specifications dc characteristics standard operating conditions: 2.3v to 3.6v (unless otherwise stated) operating temperature-40c t a +85c for industrial param. no. symbol characteristics min. typical max. units comments d310 v res resolution v dd /24 ? v dd /32 lsb d311 vr aa absolute accuracy ? ? 1/2 lsb d312 t set settling time (1) ? ? 10 s note 1: settling time measured while cvrr = 1 and cvr3:cvr0 transitions from ? 0000 ? to ? 1111 ?. table 30-14: internal voltag e regulator specifications dc characteristics standard operating conditions: 2.3v to 3.6v (unless otherwise stated) operating temperature-40c t a +85c for industrial param. no. symbol characteristics min. typical max. units comments d320 v ddcore regulator output voltage 1.62 1.80 1.98 v d321 c efc external filter capacitor value 4.7 10 ? f capacitor must be low series resistance (< 3 ohms) d322 t pwrt ? 64 ? ms envreg = 0
? 2008 microchip technology inc. preliminary ds61143e-page 601 pic32mx3xx/4xx 30.2 ac characteristics and timing parameters the information contained in this section defines pic32mx3xx/4xx ac characteristics and timing parameters. figure 30-1: load conditions fo r device timing specifications table 30-15: ac characteristics ac characteristics standard operating conditions: 2.3v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial operating voltage v dd range. table 30-16: capacitiv e loading requirements on output pins ac characteristics standard operating conditions: 2.3v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial param. no. symbol characteristics min. typical (1) max. units conditions do56 c io all i/o pins and osc2 ? ? 50 pf ec mode do58 c b sclx, sdax ? ? 400 pf in i 2 c? mode note 1: data in ?typical? column is at 3.3v, 25c unless otherwise stated. parameters are for design guidance only and are not tested. v dd /2 c l r l pin pin v ss v ss c l r l =464 c l = 50 pf for all pins 50 pf for osc2 pin (ec mode) load condition 1 ? for all pins except osc2 load condition 2 ? for osc2
pic32mx3xx/4xx ds61143e-page 602 preliminary ? 2008 microchip technology inc. figure 30-2: extern al clock timing table 30-17: external cl ock timing requirements ac characteristics standard operating conditions: 2.3v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial param. no. symbol characteristics min. typical (1) max. units conditions os10 f osc external clki frequency (external clocks allowed only in ec and ecpll modes) dc 4 ? ? 50 (3) 50 (3) mhz mhz ec ecpll (4) os11 oscillator crystal frequency 3 ? 10 mhz xt os12 4 ? 10 mhz xtpll (4) os13 10 ? 25 mhz hs os14 10 ? 25 mhz hspll (4) os15 32 32.768 100 khz sosc os20 t osc t osc = 1/f osc = t cy (2) ? ? ? ? see parameter os10 for f osc value os30 t os l, t os h external clock in (osc1) high or low time 0.45 x t osc ? ? nsec ec os31 t os r, t os f external clock in (osc1) rise or fall time ??0.05 x t osc nsec ec os40 t ost oscillator start-up timer period (only applies to hs, hspll, xt, xtpll and sosc clock oscillator modes) ? 1024 ? t osc -40c to +85c os41 t fscm primary clock fail safe time-out period ? 2 ? ms -40c to +85c note 1: data in ?typical? column is at 3.3v, 25c unless otherwise stated. parameters are for design guidance only and are not tested. 2: instruction cycle period (t cy ) equals the input oscillator time base period. all specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. all devices are tested to operate at ?min.? values with an exter- nal clock applied to the osc1/clki pin. 3: 40 mhz maximum for pic32mx 40 mhz family variants. 4: pll input requirements: 4 mh z f pllin 5 mh z (use pll prescaler to reduce f osc ). osc1 os20 os30 os30 os31 os31
? 2008 microchip technology inc. preliminary ds61143e-page 603 pic32mx3xx/4xx table 30-18: pll clock ti ming specifications (v dd = 2.3v to 3.6v) ac characteristics standard operating conditions: 2.3v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial param. no. symbol characteristics (1) min. typical (2) max. units conditions os50 f plli pll voltage controlled oscillator (vco) input frequency range 4 ? 5 mhz ecpll, hspll, mspll, frcpll modes os51 f sys on-chip vco system frequency 60 ? 230 mhz os52 t lock pll start-up time (lock time) ? ? 2 ms os53 d clk clko stability (jitter) -2 1 2 % measured over 100 ms period note 1: these parameters are characterized but not tested in manufacturing. 2: data in ?typical? column is at 3.3v, 25c unless otherwise stated. parameters are for design guidance only and are not tested. table 30-19: internal frc accuracy ac characteristics standard operating conditions: 2.3v to 3.6v (unless otherwise stated) operating temperature -40c ta +85c for industrial param. no. characteristics min. typical max. units conditions internal frc accuracy @ 8.00 mhz (1) f20 frc -2 ? +2 % -40c t a +85c v dd = 2.3 to 3.6v note 1: frequency calibrated at 25c and 3.3v. tun bits can be used to compensate for temperature drift. table 30-20: internal rc accuracy ac characteristics standard operating conditions: 2.3v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial param. no. characteristics min. typical max. units conditions lprc @ 31.25 khz (1) f21 -15 ? +15 % -40c t a +85c v dd = 2.3 to 3.6v note 1: change of lprc frequency as v dd changes.
pic32mx3xx/4xx ds61143e-page 604 preliminary ? 2008 microchip technology inc. figure 30-3: i/o ti ming characteristics note: refer to figure 30-1 for load conditions. i/o pin (input) i/o pin (output) di35 di40 do31 do32 table 30-21: i/o timing requirements ac characteristics standard operating conditions: 2.3v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial param. no. symbol characteristics min. typical (1) max. units conditions do31 t io r port output rise time ? 5 10 nsec do32 t io f port output fall time ? 5 10 nsec di35 t inp intx pin high or low time 10 ? ? nsec di40 t rbp cnx high or low time (input) 2 ? ? t sysclk note 1: data in ?typical? column is at 3.3v, 25c unless otherwise stated.
? 2008 microchip technology inc. preliminary ds61143e-page 605 pic32mx3xx/4xx figure 30-4: power-on rese t timing characteristics v dd v por note 1: the power up period will be extended if the power up sequence completes before the device exits from bor (v dd < v ddmin ). 2: includes interval voltage regulator stabilization delay. 3: power-up timer (pwrt); only active when the internal voltage regulator is disabled sy00 power up sequence (see note 2) v dd v por v ddcore external v ddcore provided internal voltage regulator enabled (t pu ) sy10 sy01 power up sequence (see note 3) cpu starts fetching code cpu starts fetching code (t pwrt ) clock sources = (hs, hspl l, xt, xtpll and sosc) v dd v por sy00 power up sequence (see note 2) internal voltage regulator enabled (t pu ) (t sysdly ) cpu starts fetching code (see note 1) (see note 1) (see note 1) clock sources = (frc, frcdiv, frcdiv16, frcpll, ec, ecpll and lprc) clock sources = (frc, frcdiv, frcdiv16, frcpll, ec, ecpll and lprc) (t ost ) sy02 (t sysdly ) sy02 (t sysdly ) sy02
pic32mx3xx/4xx ds61143e-page 606 preliminary ? 2008 microchip technology inc. figure 30-5: external re set timing characteristics table 30-22: resets timing ac characteristics standard operating conditions: 2.3v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial param. no. symbol characteristics (1) min. typical (2) max. units conditions sy00 t pu power-up period internal voltage regulator enabled ? 400 600 s -40c to +85c sy01 t pwrt power-up period external v ddcore applied (power-up-timer active) 48 64 80 ms -40c to +85c sy02 t sysdly system delay period: time required to reload device configuration fuses plus sysclk delay before first instruction is fetched. ? 1 s + 8 sysclk cycles ?? -40c to +85c sy20 t mclr mclr pulse width (low) ? 2 ? s -40c to +85c sy30 t bor bor pulse width (low) ?1 ? s -40c to +85c note 1: these parameters are characterized but not tested in manufacturing. 2: data in ?typ? column is at 3.3v, 25c unless otherwise stated. characterized by design but not tested. mclr (sy20) reset sequence (sy10) cpu starts fetching code bor (sy30) t ost t mclr t bor reset sequence cpu starts fetching code clock sources = (frc, frcdiv, frcdiv16, frcpll, ec, ecpll and lprc) clock sources = (hs, hspll, xt, xtpll and sosc) (t sysdly ) sy02 (t sysdly ) sy02
? 2008 microchip technology inc. preliminary ds61143e-page 607 pic32mx3xx/4xx figure 30-6: timer1, 2, 3, 4, 5 exte rnal clock timing characteristics note: refer to figure 30-1 for load conditions. tx11 tx15 tx10 tx20 tmrx os60 txck table 30-23: timer1 external clock timing requirements (1) ac characteristics standard operating conditions: 2.3v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial param. no. symbol characteristics min. typical max. units conditions ta10 t tx h txck high time synchronous, with prescaler 10 ? ? nsec must also meet parameter ta15 asynchronous, with prescaler 10 ? ? nsec asynchronous 10 ? ? nsec ta11 t tx l txck low time synchronous, with prescaler 10 ? ? nsec must also meet parameter ta15 asynchronous, with prescaler 10 ? ? nsec asynchronous 10 ? ? nsec ta15 t tx p txck input period synchronous, with prescaler greater of: 10 nsec or (2 * t pb + 10) ? ? nsec asynchronous, with prescaler greater of: 10 nsec or (2 * t pb + 10)/n ???n = prescale value (1, 8, 64, 256) asynchronous 10 ? ? nsec os60 f t 1 sosc1/t1ck oscillator input frequency range (oscillator enabled by setting tcs bit (t1con<1>)) 32 ? 100 khz ta20 t ckextmrl delay from external txck clock edge to timer increment ?10nsec note 1: timer1 is a type a.
pic32mx3xx/4xx ds61143e-page 608 preliminary ? 2008 microchip technology inc. table 30-24: timer2, 3, 4, 5 exte rnal clock timing requirements ac characteristics standard operating conditions: 2.3v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial param. no. symbol characteristics min. max. units conditions tb10 t tx h txck high time synchronous, no prescaler greater of: 10 nsec or (t pb + 5) ? nsec must also meet parameter tb15 synchronous, with prescaler 20 ? nsec tb11 t tx l txck low time synchronous, no prescaler greater of: 10 nsec or (t pb + 5) ? nsec must also meet parameter tb15 synchronous, with prescaler 10 ? nsec tb15 t tx p txck input period synchronous, no prescaler greater of: 10 nsec or (2 * t pb + 10) ? nsec n = prescale value (1, 2, 4, 8, 16, 32, 64, 256) synchronous, with prescaler greater of: 10 nsec or (2*t pb + 10)/n tb20 t ckextmrl delay from external txck clock edge to timer increment ? 5 nsec
? 2008 microchip technology inc. preliminary ds61143e-page 609 pic32mx3xx/4xx figure 30-7: input capture (capx) timing characteristics figure 30-8: output compare module (o cx) timing characteristics table 30-25: input capture module timing requirements ac characteristics standard operating conditions: 2.3v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial param. no. symbol characteristics (1) min. max. units conditions ic10 t cc l icx input low time no prescaler greater of: 10 nsec or (t pb + 5) ?nsec with prescaler 10 ? nsec ic11 t cc h icx input high time no prescaler greater of: 20 nsec or (t pb + 5) ?nsec with prescaler 10 ? nsec ic15 t cc p icx input period greater of: 10 nsec or (2*t pb + 10)/n ? nsec n = prescale value (1, 4, 16) note 1: these parameters are characterized but not tested in manufacturing. icx ic10 ic11 ic15 note: refer to figure 30-1 for load conditions. ocx oc11 oc10 (output compare note: refer to figure 30-1 for load conditions. or pwm mode)
pic32mx3xx/4xx ds61143e-page 610 preliminary ? 2008 microchip technology inc. table 30-26: output compare modul e timing requirements figure 30-9: oc/pwm module ti ming characteristics ac characteristics standard operating conditions: 2.3v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial param. no. symbol characteristics (1) min. typical (2) max. units conditions oc10 t cc f ocx output fall time ? ? ? nsec see parameter do32 oc11 t cc r ocx output rise time ? ? ? nsec see parameter do31 note 1: these parameters are characterized but not tested in manufacturing. 2: data in ?typical? column is at 3.3v, 25c unless otherwise stated. parameters are for design guidance only and are not tested. ocfa/ocfb ocx oc20 oc15 note: refer to figure 30-1 for load conditions. table 30-27: simple oc/pwm mode timing requirements ac characteristics standard operating conditions: 2.3v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial param no. symbol characteristics (1) min typical (2) max units conditions oc15 t fd fault input to pwm i/o change ? ? 25 nsec oc20 t flt fault input pulse width 50 ? ? nsec note 1: these parameters are characterized but not tested in manufacturing. 2: data in ?typical? column is at 3.3v, 25c unless otherwise stated. parameters are for design guidance only and are not tested.
? 2008 microchip technology inc. preliminary ds61143e-page 611 pic32mx3xx/4xx figure 30-10: spix module master mode (cke = 0 ) timing characteristics table 30-28: spix master mode (cke = 0 ) timing requirements ac characteristics standard operating conditions: 2.3v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial param. no. symbol characteristics (1) min. typical (2) max. units conditions sp10 t sc l sckx output low time (3) t sck /2 ? ? nsec sp11 t sc h sckx output high time (3) t sck /2 ? ? nsec sp20 t sc f sckx output fall time (4) ???nsec see parameter do32 sp21 t sc r sckx output rise time (4) ? ?? nsec see parameter do31 sp30 t do f sdox data output fall time (4) ? ?? nsec see parameter do32 sp31 t do r sdox data output rise time (4) ? ?? nsec see parameter do31 sp35 t sc h2 do v, t sc l2 do v sdox data output valid after sckx edge ?? 15 nsec sp40 t di v2 sc h, t di v2 sc l setup time of sdix data input to sckx edge 10 ? ? nsec sp41 t sc h2 di l, t sc l2 di l hold time of sdix data input to sckx edge 10 ? ? nsec note 1: these parameters are characterized but not tested in manufacturing. 2: data in ?typical? column is at 3.3v, 25c unless otherwise stated. parameters are for design guidance only and are not tested. 3: the minimum clock period for sckx is 40 nsec. therefore, the clock generated in master mode must not violate this specification. 4: assumes 50 pf load on all spix pins. sckx (ckp = 0 ) sckx (ckp = 1 ) sdox sdix sp11 sp10 sp40 sp41 sp21 sp20 sp35 sp20 sp21 msb lsb bit 14 - - - - - -1 msb in lsb in bit 14 - - - -1 sp30 sp31 note: refer to figure 30-1 for load conditions.
pic32mx3xx/4xx ds61143e-page 612 preliminary ? 2008 microchip technology inc. figure 30-11: spix module master mode (cke = 1 ) timing characteristics table 30-29: spix module master mode (cke = 1 ) timing requirements ac characteristics standard operating conditions: 2.3v to 3.6v (unless otherwise stated) operating temperature -40c t a +85cfor industrial param. no. symbol characteristics (1) min. typical (2) max. units conditions sp10 t sc l sckx output low time (3) t sck /2 ? ? nsec sp11 t sc h sckx output high time (3) t sck /2 ? ? nsec sp20 t sc f sckx output fall time (4) ???nsec see parameter do32 sp21 t sc r sckx output rise time (4) ? ?? nsec see parameter do31 sp30 t do f sdox data output fall time (4) ? ?? nsec see parameter do32 sp31 t do r sdox data output rise time (4) ? ?? nsec see parameter do31 sp35 t sc h2 do v, t sc l2 do v sdox data output valid after sckx edge ?? 15 nsec sp36 t do v2 sc , t do v2 sc l sdox data output setup to first sckx edge 15 ? ? nsec sp40 t di v2 sc h, t di v2 sc l setup time of sdix data input to sckx edge 10 ? ? nsec sp41 t sc h2 di l, t sc l2 di l hold time of sdix data input to sckx edge 10 ? ? nsec note 1: these parameters are characterized but not tested in manufacturing. 2: data in ?typical? column is at 3.3v, 25c unless otherwise stated. parameters are for design guidance only and are not tested. 3: the minimum clock period for sckx is 40 nsec. therefore, the clock generated in master mode must not violate this specification. 4: assumes 50 pf load on all spix pins. sck x (ckp = 0 ) sck x (ckp = 1 ) sdo x sdi x sp36 sp30,sp31 sp35 msb msb in bit 14 - - - - - -1 lsb in bit 14 - - - -1 lsb note: refer to figure 30-1 for load conditions . sp11 sp10 sp20 sp21 sp21 sp20 sp40 sp41
? 2008 microchip technology inc. preliminary ds61143e-page 613 pic32mx3xx/4xx figure 30-12: spix modul e slave mode (cke = 0 ) timing characteristics ss x sck x (ckp = 0 ) sck x (ckp = 1 ) sdo x sp50 sp40 sp41 sp30,sp31 sp51 sp35 msb lsb bit 14 - - - - - -1 msb in bit 14 - - - -1 lsb in sp52 sp73 sp72 sp72 sp73 sp71 sp70 note: refer to figure 30-1 for load conditions . sdi x
pic32mx3xx/4xx ds61143e-page 614 preliminary ? 2008 microchip technology inc. table 30-30: spix modul e slave mode (cke = 0 ) timing requirements ac characteristics standard operating conditions: 2.3v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial param. no. symbol characteristics (1) min. typical (2) max. units conditions sp70 t sc l sckx input low time (3) t sck /2 ? ? nsec sp71 t sc h sckx input high time (3) t sck /2 ? ? nsec sp72 t sc f sckx input fall time ? 5 10 nsec sp73 t sc r sckx input rise time ? 510 nsec sp30 t do f sdox data output fall time (4) ? ? ? nsec see parameter do32 sp31 t do r sdox data output rise time (4) ???nsec see parameter do31 sp35 t sc h2 do v, t sc l2 do v sdox data output valid after sckx edge ?? 15 nsec sp40 t di v2 sc h, t di v2 sc l setup time of sdix data input to sckx edge 10 ? ? nsec sp41 t sc h2 di l, t sc l2 di l hold time of sdix data input to sckx edge 10 ? ? nsec sp50 t ss l2 sc h, t ss l2 sc l ssx to sckx or sckx input 60 ? ? nsec sp51 t ss h2 do z ssx to sdox output high-impedance (3) 5 ? 25 nsec sp52 t sc h2 ss h t sc l2 ss h ssx after sckx edge t sck + 20 ? ? nsec ? note 1: these parameters are characterized but not tested in manufacturing. 2: data in ?typical? column is at 3.3v, 25c unless otherwise stated. parameters are for design guidance only and are not tested. 3: the minimum clock period for sckx is 40 nsec. 4: assumes 50 pf load on all spix pins.
? 2008 microchip technology inc. preliminary ds61143e-page 615 pic32mx3xx/4xx figure 30-13: spix modul e slave mode (cke = 1 ) timing characteristics ssx sckx (ckp = 0 ) sckx (ckp = 1 ) sdox sdi sp50 sp60 sdix sp30,sp31 msb bit 14 - - - - - -1 lsb sp51 msb in bit 14 - - - -1 lsb in sp35 sp52 sp52 sp73 sp72 sp72 sp73 sp71 sp70 sp40 sp41 note: refer to figure 30-1 for load conditions.
pic32mx3xx/4xx ds61143e-page 616 preliminary ? 2008 microchip technology inc. table 30-31: spix modul e slave mode (cke = 1 ) timing requirements ac characteristics standard operating conditions: 2.3v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial param .no. symbol characteristics (1) min. typical (2) max. units conditions sp70 t sc l sckx input low time (3) t sck /2 ? ? nsec sp71 t sc h sckx input high time (3) t sck /2 ? ? nsec sp72 t sc f sckx input fall time ? 5 10 nsec sp73 t sc r sckx input rise time ? 510 nsec sp30 t do f sdox data output fall time (4) ???nsec see parameter do32 sp31 t do r sdox data output rise time (4) ???nsec see parameter do31 sp35 t sc h2 do v, t sc l2 do v sdox data output valid after sckx edge ?? 15 nsec sp40 t di v2 sc h, t di v2 sc l setup time of sdix data input to sckx edge 10 ? ? nsec sp41 t sc h2 di l, t sc l2 di l hold time of sdix data input to sckx edge 10 ? ? nsec sp50 t ss l2 sc h, t ss l2 sc l ssx to sckx or sckx input 60 ? ? nsec sp51 t ss h2 do z ssx to sdo x output high-impedance (4) 5 ? 25 nsec sp52 t sc h2 ss h t sc l2 ss h ssx after sckx edge t sck + 20 ? ? nsec sp60 t ss l2 do v sdox data output valid after ssx edge ?? 25 nsec note 1: these parameters are characterized but not tested in manufacturing. 2: data in ?typical? column is at 3.3v, 25c unless otherwise stated. parameters are for design guidance only and are not tested. 3: the minimum clock period for sckx is 40 nsec. 4: assumes 50 pf load on all spix pins.
? 2008 microchip technology inc. preliminary ds61143e-page 617 pic32mx3xx/4xx figure 30-14: i2cx bus start/stop bits ti ming characteristics (master mode) figure 30-15: i2cx bus data timing characteristics (master mode) im31 im34 sclx sdax start condition stop condition im30 im33 note: refer to figure 30-1 for load conditions. im11 im10 im33 im11 im10 im20 im26 im25 im40 im40 im45 im21 sclx sdax in sdax out note: refer to figure 30-1 for load conditions.
pic32mx3xx/4xx ds61143e-page 618 preliminary ? 2008 microchip technology inc. table 30-32: i2cx bus data timing requirements (master mode) ac characteristics standard operating conditions: 2.3v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial param. no. symbol characteristics min. (1) max. units conditions im10 t lo : scl clock low time 100 khz mode t pb * (brg + 2) ? s? 400 khz mode t pb * (brg + 2) ? s? 1 mhz mode (2) t pb * (brg + 2) ? s? im11 t hi : scl clock high time 100 khz mode t pb * (brg + 2) ? s? 400 khz mode t pb * (brg + 2) ? s? 1 mhz mode (2) t pb * (brg + 2) ? s? im20 t f : scl sdax and sclx fall time 100 khz mode ? 300 nsec c b is specified to be from 10 to 400 pf 400 khz mode 20 + 0.1 c b 300 nsec 1 mhz mode (2) ? 100 nsec im21 t r : scl sdax and sclx rise time 100 khz mode ? 1000 nsec c b is specified to be from 10 to 400 pf 400 khz mode 20 + 0.1 c b 300 nsec 1 mhz mode (2) ? 300 nsec im25 t su : dat data input setup time 100 khz mode 250 ? nsec ? 400 khz mode 100 ? nsec 1 mhz mode (2) 100 ? nsec im26 t hd : dat data input hold time 100 khz mode 0 ? s? 400 khz mode 0 0.9 s 1 mhz mode (2) 0 0.3 s im30 t su : sta start condition setup time 100 khz mode t pb * (brg + 2) ? s only relevant for repeated start condition 400 khz mode t pb * (brg + 2) ? s 1 mhz mode (2) t pb * (brg + 2) ? s im31 t hd : sta start condition hold time 100 khz mode t pb * (brg + 2) ? s after this period, the first clock pulse is generated 400 khz mode t pb * (brg + 2) ? s 1 mhz mode (2) t pb * (brg + 2) ? s im33 t su : sto stop condition setup time 100 khz mode t pb * (brg + 2) ? s? 400 khz mode t pb * (brg + 2) ? s 1 mhz mode (2) t pb * (brg + 2) ? s im34 t hd : sto stop condition 100 khz mode t pb * (brg + 2) ?nsec ? hold time 400 khz mode t pb * (brg + 2) ?nsec 1 mhz mode (2) t pb * (brg + 2) ?nsec im40 t aa : scl output valid from clock 100 khz mode ? 3500 nsec ? 400 khz mode ? 1000 nsec ? 1 mhz mode (2) ? 350 nsec ? im45 t bf : sda bus free time 100 khz mode 4.7 ? s time the bus must be free before a new transmission can start 400 khz mode 1.3 ? s 1 mhz mode (2) 0.5 ? s im50 c b bus capacitive loading ? 400 pf note 1: brg is the value of the i 2 c? baud rate generator. 2: maximum pin capacitance = 10 pf for all i2cx pins (for 1 mhz mode only).
? 2008 microchip technology inc. preliminary ds61143e-page 619 pic32mx3xx/4xx figure 30-16: i2cx bus start/stop bits timing characteristics (slave mode) figure 30-17: i2cx bus data timing characteristics (slave mode) is31 is34 sclx sdax start condition stop condition is30 is33 note: refer to figure 30-1 for load conditions. is30 is31 is33 is11 is10 is20 is26 is25 is40 is40 is45 is21 sclx sdax in sdax out note: refer to figure 30-1 for load conditions.
pic32mx3xx/4xx ds61143e-page 620 preliminary ? 2008 microchip technology inc. table 30-33: i2cx bus data timing requirements (slave mode) ac characteristics standard operating conditions: 2.3v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial param. no. symbol characteristics min. max. units conditions is10 t lo : scl clock low time 100 khz mode 4.7 ? s pbclk must operate at a minimum of 800 khz 400 khz mode 1.3 ? s pbclk must operate at a minimum of 3.2 mhz 1 mhz mode (1) 0.5 ? s is11 t hi : scl clock high time 100 khz mode 4.0 ? s pbclk must operate at a minimum of 800 khz. 400 khz mode 0.6 ? s pbclk must operate at a minimum of 3.2 mhz 1 mhz mode (1) 0.5 ? s is20 t f : scl sdax and sclx fall time 100 khz mode ? 300 nsec c b is specified to be from 10 to 400 pf 400 khz mode 20 + 0.1 c b 300 nsec 1 mhz mode (1) ? 100 nsec is21 t r : scl sdax and sclx rise time 100 khz mode ? 1000 nsec c b is specified to be from 10 to 400 pf 400 khz mode 20 + 0.1 c b 300 nsec 1 mhz mode (1) ? 300 nsec is25 t su : dat data input setup time 100 khz mode 250 ? nsec 400 khz mode 100 ? nsec 1 mhz mode (1) 100 ? nsec is26 t hd : dat data input hold time 100 khz mode 0 ? nsec 400 khz mode 0 0.9 s 1 mhz mode (1) 00.3 s is30 t su : sta start condition setup time 100 khz mode 4700 ? s only relevant for repeated start condition 400 khz mode 600 ? s 1 mhz mode (1) 250 ? s is31 t hd : sta start condition hold time 100 khz mode 4000 ? s after this period, the first clock pulse is generated 400 khz mode 600 ? s 1 mhz mode (1) 250 ? s is33 t su : sto stop condition setup time 100 khz mode 4000 ? s 400 khz mode 600 ? s 1 mhz mode (1) 600 ? s is34 t hd : sto stop condition hold time 100 khz mode 4000 ? nsec 400 khz mode 600 ? nsec 1 mhz mode (1) 250 nsec is40 t aa : scl output valid from clock 100 khz mode 0 3500 nsec 400 khz mode 0 1000 nsec 1 mhz mode (1) 0 350 nsec is45 t bf : sda bus free time 100 khz mode 4.7 ? s time the bus must be free before a new transmission can start 400 khz mode 1.3 ? s 1 mhz mode (1) 0.5 ? s is50 c b bus capacitive loading ? 400 pf note 1: maximum pin capacitance = 10 pf for all i2cx pins (for 1 mhz mode only).
? 2008 microchip technology inc. preliminary ds61143e-page 621 pic32mx3xx/4xx table 30-34: adc mo dule specifications ac characteristics standard operating conditions: 2.5v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial param. no. symbol characteristics min. typical max. units conditions device supply ad01 av dd module v dd supply greater of v dd ? 0.3 or 2.5 ? lesser of v dd + 0.3 or 3.6 v ad02 av ss module v ss supply v ss ?v ss + 0.3 v reference inputs ad05 v refh reference voltage high av ss + 2.0 ? av dd vsee note 1 ad05a 2.5 ? 3.6 v v refh = av dd ad06 v refl reference voltage low av ss ?v refh ? 2.0 vsee note 1 ad07 v ref absolute reference voltage (v refh ? v refl ) 2.0 ? av dd v ad08 i ref current drain ? 250 ? 400 3 a a adc operating adc off analog input ad12 v inh -v inl full-scale input span v refl ?v refh v v inl absolute v inl input voltage av ss ? 0.3 av dd /2 v v in absolute input voltage av ss ? 0.3 av dd + 0.3 v leakage current ? +/- 0.001 +/-0.610 av inl = av ss = v refl = 0v, av dd = v refh = 3.3v source impedance = 10k ad17 r in recommended impedance of analog voltage source ??10k adc accuracy ? measurements with external v ref +/v ref - ad20c nr resolution 10 data bits bits ad21c inl integral nonlinearity ? ? <+/-1 lsb v inl = av ss = v refl = 0v, av dd = v refh = 3.3v ad22c dnl differential nonlinearity ? ? <+/-1 lsb v inl = av ss = v refl = 0v, av dd = v refh = 3.3v (2) ad23c g err gain error ? ? <+/-1 lsb v inl = av ss = v refl = 0v, av dd = v refh = 3.3v ad24n e off offset error ? ? <+/-1 lsb v inl = av ss = 0v, av dd = 3.3v ad25c ? monotonicity ? ? ? ? guaranteed adc accuracy ? measurements with internal v ref +/v ref - ad20d nr resolution 10 data bits bits ad21d inl integral nonlinearity ? ? <+/-1 lsb v inl = av ss = 0v, av dd = 2.5v to 3.6v note 1: these parameters are not characterized or tested in manufacturing. 2: with no missing codes.
pic32mx3xx/4xx ds61143e-page 622 preliminary ? 2008 microchip technology inc. ad22d dnl differential nonlinearity ? ? <+/-1 lsb v inl = av ss = 0v, av dd = 2.5v to 3.6v (2) ad23d g err gain error ? ? <+/-4 lsb v inl = av ss = 0v, av dd = 2.5v to 3.6v ad24d e off offset error ? ? <+/-2 lsb v inl = av ss = 0v, av dd = 2.5v to 3.6v ad25d ? monotonicity ? ? ? ? guaranteed table 30-34: adc module specifications (continued) ac characteristics standard operating conditions: 2.5v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial param. no. symbol characteristics min. typical max. units conditions note 1: these parameters are not characterized or tested in manufacturing. 2: with no missing codes.
? 2008 microchip technology inc. preliminary ds61143e-page 623 pic32mx3xx/4xx table 30-35: a/d conversion timing requirements ac characteristics standard operating conditions: 2.5v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial param. no. symbol characteristics min. typical (1) max. units conditions clock parameters ad50 t ad a/d clock period (2) 75 ? ? nsec t pb = 75 nsec, av dd = 3.0v ad51 trc a/d internal rc oscillator period ? 250 ? nsec see note 3 conversion rate ad55 tconv conversion time ? 12 t ad ?? ? ad56 f cnv throughput rate (sampling speed) ? ? 500 ksps av dd = 3.0v to 3.6v ? ? 400 ksps av dd = 2.5v to 3.6v ad57 t samp sample time 1 ? 31 t ad t samp must be 140 nsec timing parameters ad60 tpcs conversion start from sample trigger (3) ?1.0 t ad ? ? auto-convert trigger (ssrc<2:0> = 111 ) not selected ad61 tpss sample start from setting sample (samp) bit 0.5 t ad ? 1.5 t ad ?? ad62 tcss conversion completion to sample start (asam = 1 ) (3) ?0.5 t ad ?? ? ad63 tdpu time to stabilize analog stage from a/d off to a/d on (3) ?? 2 s? note 1: these parameters are characterized but not tested in manufacturing. 2: because the sample caps will eventually lose charge, clock rates below 10 khz can affect linearity performance, especially at elevated temperatures. 3: characterized by design but not tested.
pic32mx3xx/4xx ds61143e-page 624 preliminary ? 2008 microchip technology inc. figure 30-18: a/d conversion (1 0-bit mode) timing characteristics (chps<1:0> = 01 , simsam = 0 , asam = 0 , ssrc<2:0> = 000 ) ad55 t samp clear samp set samp ad61 adclk instruction samp ch0_dischrg ch1_samp ad60 conv adxif buffer( 0 ) buffer( 1 ) 1 2 3 4 5 6 8 5 6 7 1 ? software sets adxcon. samp to start sampling. 2 ? sampling starts after discharge period. t samp is described in the ?pic32mx family reference manual? (ds61132). 3 ? software clears adxcon. samp to start conversion. 4 ? sampling ends, conversion sequence starts. 5 ? convert bit 9. 8 ? one t ad for end of conversion. ad50 ch0_samp ch1_dischrg eoc 7 ad55 8 6 ? convert bit 8. 7 ? convert bit 0. execution
? 2008 microchip technology inc. preliminary ds61143e-page 625 pic32mx3xx/4xx figure 30-19: a/d conversion (10-bit mode) timing characteristics (chps<1:0> = 01 , simsam = 0 , asam = 1 , ssrc<2:0> = 111 , samc<4:0> = 00001 ad55 t samp set adon adclk instruction samp ch0_dischrg ch1_samp conv adxif buffer( 0 ) buffer( 1 ) 1 2 3 4 5 6 4 5 6 8 1 ? software sets adxcon. adon to start ad operation. 2 ? sampling starts after discharge period. 3 ? convert bit 9. 4 ? convert bit 8. 5 ? convert bit 0. ad50 ch0_samp ch1_dischrg eoc 7 3 ad55 6 ? one t ad for end of conversion. 7 ? begin conversion of next channel. 8 ? sample for time specified by samc<4:0>. t samp t conv 3 4 execution t samp is described in the ?pic32mx family reference manual? (ds61132).
pic32mx3xx/4xx ds61143e-page 626 preliminary ? 2008 microchip technology inc. figure 30-20: parallel slave port timing cs r d w r pmd<7:0> ps1 ps2 ps3 ps4 ps5 ps6 ps7 table 30-36: parallel slave port requirements ac characteristics standard operating conditions: 2.3v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial param. no. symbol characteristics min. typical max. units conditions ps1 tdtv2wrh data in valid before wr or cs inactive (setup time) 20 ? ? nsec ps2 twrh2dti wr or cs inactive to data? in invalid (hold time) 20 ? ? nsec ps3 trdl2dtv rd and cs active to data? out valid ? ? 60 nsec ps4 trdh2dti rd active or cs inactive to data? out invalid 0 ? 10 nsec ps5 tcs cs active time 25 ? ? nsec ps6 t wr wr active time 25 ? ? nsec ps7 t rd rd active time 25 ? ? nsec
? 2008 microchip technology inc. preliminary ds61143e-page 627 pic32mx3xx/4xx figure 30-21: parallel master port read timing diagram t pb t pb t pb t pb t pb t pb t pb t pb pb clock pmall/pmalh pmd<7:0> pma<13:18> pmrd pmcs<2:1> pmwr pm5 data address<7:0> pm1 pm3 pm6 data pm7 address<7:0> address pm4 pm2 table 30-37: parallel master po rt read timing requirements ac characteristics standard operating conditions: 2.3v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial param. no. symbol characteristics min. typical max. units conditions pm1 t lat pmall/pmalh pulse width ? 1 t pb ?? pm2 t adsu address out valid to pmall/pmalh invalid (address setup time) ?2 t pb ?? pm3 t adhold pmall/pmalh invalid to address out invalid (address hold time) ?1 t pb ?? pm4 t ahold pmrd inactive to address out invalid (address hold time) 1??nsec pm5 t rd pmrd pulse width ? 1 t pb ?? pm6 t dsu pmrd or pmenb active to data in valid (data setup time) 5??nsec pm7 t dhold pmrd or pmenb inactive to data in invalid (data hold time) ?0?nsec
pic32mx3xx/4xx ds61143e-page 628 preliminary ? 2008 microchip technology inc. figure 30-22: parallel master port write timing diagram t pb t pb t pb t pb t pb t pb t pb t pb pb clock pmall/pmalh pmd<7:0> pma<13:18> pmwr pmcs<2:1> pmrd pm12 pm13 pm11 address address<7:0> data pm2 + pm3 pm1 table 30-38: parallel master port write timing requirements ac characteristics standard operating conditions: 2.3v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial param. no. symbol characteristics min. typical max. units conditions pm11 t wr pmwr pulse width ? 1 t pb ?? pm12 t dvsu data out valid before pmwr or pmenb goes inactive (data setup time) ?2 t pb ?? pm13 t dvhold pmwr or pmemb invalid to data out invalid (data hold time) ?1 t pb ??
? 2008 microchip technology inc. preliminary ds61143e-page 629 pic32mx3xx/4xx table 30-39: otg timing requirements ac characteristics standard operating conditions: 2.3v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial param. no. symbol characteristics min. typ max. units conditions usb313 v usb usb voltage 3.0 ? 3.6 v voltage on bus must be in this range for proper usb operation usb315 v ilusb input low voltage for usb buffer ? ? 0.8 v usb316 v ihusb input high voltage for usb buffer 2.0 ? ? v usb318 v difs differential input sensitivity ? ? 0.2 v usb319 vcm differential common mode range 0.8 ? 2.5 v the difference between d+ and d- must exceed this value while vcm is met usb320 z out driver output impedance 28.0 ? 44.0 usb321 v ol voltage output low 0.0 ? 0.3 v 1.5 k load connected to 3.6v usb322 v oh voltage output high 2.8 ? 3.6 v 1.5 k load connected to ground
pic32mx3xx/4xx ds61143e-page 630 preliminary ? 2008 microchip technology inc. figure 30-23: ejtag timing characteristics table 30-40: ejtag timing requirements ac characteristics standard operating conditions: 2.3v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial param. no. symbol description min. max. units conditions ej1 t tckcyc tck cycle time 25 ? nsec ej2 t tckhigh tck high time 10 ? nsec ej3 t tcklow tck low time 10 ? nsec ej4 t tsetup tap signals setup time before rising tck 5 ? nsec ej5 t thold tap signals hold time after rising tck 3 ? nsec ej6 t tdoout tdo output delay time from falling tck ? 5 nsec ej7 t tdozstate tdo 3-state delay time from falling tck ? 5 nsec ej8 t trstlow trst low time 25 ? nsec ej9 t rf tap signals rise/fall time, all input and output ? ? nsec t tckeye t tckhigh t tcklow t rf t rf t rf t rf t tse t up t thold t tdoout t tdozstate defined undefined t trst*low t rf tck tdo trst* tdi tms
? 2008 microchip technology inc. preliminary ds61143e-page 631 pic32mx3xx/4xx 31.0 packaging information 31.1 package marking information legend: xx...x customer-specific information y year code (last digit of calendar year) yy year code (last 2 digits of calendar year) ww week code (week of january 1 is week ?01?) nnn alphanumeric traceability code pb-free jedec designator for matte tin (sn) * this package is pb-free. the pb-free jedec designator ( ) can be found on the outer packaging for this package. note : in the event the full microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. 3 e 64-lead tqfp (10x10x1 mm) xxxxxxxxxx xxxxxxxxxx xxxxxxxxxx yywwnnn example pic32mx360f 512l-80i/pt 0510017 100-lead tqfp (12x12x1 mm) xxxxxxxxxxxx xxxxxxxxxxxx yywwnnn 3 e example pic32mx360f 256l-80i/pt 0510017 3 e
pic32mx3xx/4xx ds61143e-page 632 preliminary ? 2008 microchip technology inc. 31.2 package details the following sections give the technical details of the packages.

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pic32mx3xx/4xx ds61143e-page 636 preliminary ? 2008 microchip technology inc. notes:
? 2008 microchip technology inc. preliminary ds61143e-page 637 pic32mx3xx/4xx appendix a: revision history revision e (july 2008) ? updated the pic32mx340f128h features in table 2 to include 4 programmable dma channels.
pic32mx3xx/4xx ds61143e-page 638 preliminary ? 2008 microchip technology inc. notes:
? 2008 microchip technology inc. preliminary ds61143e-page 639 pic32mx3xx/4xx product identification system to order or obtain information, e. g., on pricing or delivery, refer to the factory or the listed sales office . architecture mx = 32-bit risc mcu core product groups 3xx = general purpose microcontroller family 4xx = usb flash memory family f = flash program memory program memory size 32 = 32k 64 = 64k 128 = 128k 256 = 256k 512 = 512k pin count h = 64-pin l = 100-pin temperature range i = -40 c to +85 c (industrial) package pt = 64-lead, 100-lead (10x10x1 mm) tqfp (thin quad flatpack) pt = 100-lead (12x12x1 mm) tqfp (thin quad flatpack) pattern three-digit qtp, sqtp, code or special requirements (blank otherwise) es = engineering sample examples: pic32mx320f032h-40i/pt: general purpose pic32mx, 32 kb program memory, 64-pin, industrial temp., tqfp package. pic32mx360f256l-80i/pt: general purpose pic32mx, 256 kb program memory, 100-pin, industrial temp., tqfp package. microchip brand architecture flash memory family pin count product groups program memory size (kb) pic32 mx 3xx f 512 h t - 80 i / pt - xxx flash memory family speed pattern package temperature range tape and reel flag (if applicable)
pic32mx3xx/4xx ds61143e-page 640 preliminary ? 2008 microchip technology inc. notes:
? 2008 microchip technology inc. preliminary ds61143e-page 641 pic32mx3xx/4xx index numerics 12-bit a/d adpcfg ................................................................... 491 a a/d enabling the module ................................................. 507 how to start sampling .............................................. 505 sampling requirements............................................ 519 a/d conversion speeds.................................................... 518 a/d converter voltage reference schematic................... 517 a/d module configuration ................................................. 503 a/d terminology and conversion sequence .................... 502 ac characteristics ............................................................ 601 internal rc accuracy ................................................ 603 ac electrical specifications parallel master port read requirements ................. 627 parallel master port write requirements.................. 628 parallel slave port requirements ............................. 626 adc converting 1 channel at 400 ksps............................ 509 assembler mpasm assembler................................................... 590 automatic clock stretch.................................................... 411 receive mode ........................................................... 411 transmit mode .......................................................... 411 b baud rate error calculation (brgh = 0) ......................... 434 block diagrams 10-bit high-speed a/d converter ............................. 490 comparator analog input model ............................... 546 comparator i/o operating modes............................. 537 comparator voltage reference ................................ 549 connections for on-chip voltage regulator............. 576 crystal or cermaic resonator operation (xt or hs)........................................................... 71 external clock input (osciofcn = 0) ....................... 72 external clock input (osciofcn = 1) ....................... 72 input capture ............................................................ 355 jtag compliant application showing daisy-chaining of components ................ 577, 583 output compare module........................................... 365 overview of usb implementation as a device ......... 287 overview of usb implementation as a host............. 288 overview of usb implementation for otg (dual role) ............................................... 289 reset system.............................................................. 83 rtcc ........................................................................ 467 shared port structure ....................................... 305, 306 single comparator .................................................... 545 type b timer .............................................. 34, 177, 340 typical i 2 c interconnection....................................... 412 uart ........................................................................ 425 wdt.......................................................................... 555 boundary scan register (bsr) ........................................ 584 boundary scan testing (bst) .......................................... 586 brown-out reset (bor) and on-chip voltage regulator................................ 576 c c compilers mplab c18 .............................................................. 590 mplab c30 .............................................................. 590 clearing usb otg interrupts ........................................... 244 clock switching operation.................................................. 79 enabling...................................................................... 79 entering sleep mode .................................................. 81 sequence ................................................................... 79 code examples aborting a clock switch........................................ 76, 81 erasing a program memory block............................ 120 initialization code for 16-bit asynchronous counter mode using an external clock input ....................................................... 334 initialization code for 16-bit synchronous counter mode using an external clock input ....... 193, 349, 351, 456, 460, 461, 463 initialization code for 16-bit timer using system clock..... 88, 169, 170, 175, 193, 325, 336, 350, 353, 393, 396, 437 initialization code for 32-bit gated time accumulation mode ......................... 239, 326, 336, 354, 364, 406, 407, 437, 464, 485 initiating a programming sequence ......................... 122 pwm mode pulse setup and interrupt servicing .................................... 377, 380 setting the rtcwren bit........................ 231, 233, 479 voltage reference configuration ............................. 553 comparator analog input connection considerations ................. 546 configuration ............................................................ 545 external reference signal........................................ 545 internal reference signal ......................................... 545 interrupts .................................................................. 547 operation.................................................................. 545 outputs ..................................................................... 546 reference ................................................................. 545 comparator voltage reference accuracy and error................................................... 553 configuring ............................................................... 552 initialization............................................................... 553 control registers ...................................................... 243, 491 conversion sequence examples...................................... 510 core features....................................................................... 9 16-bit architecture ........................................................ 9 easy migration .............................................................. 9 oscillator options, features ....................................... 10 power-saving technology............................................ 9 cpu module ....................................................................... 33 d dc characteristics............................................................ 594 i/o pin input specifications ...................................... 598 i/o pin output specifications.................................... 599 idle current (i idle ) .................................................... 596 operating current (i dd ) ............................................ 595 power-down current (i pd )........................................ 597 program memory...................................................... 599 temperature and voltage specifications.................. 594 development support ....................................................... 589 device reset times............................................................ 91
pic32mx3xx/4xx ds61143e-page 642 preliminary ? 2008 microchip technology inc. e electrical characteristics................................................... 593 ac ............................................................................. 601 enhanced in-circuit serial programming (eicsp)............ 581 equations calculating the pwm period ..................................... 379 calculation for maximum pwm resolution............... 379 serial clock rate ...................................................... 409 uart baud rate with brgh = 0 ............................. 434 uart baud rate with brgh = 1 ............................. 434 wdt time-out period ............................................... 562 errata .................................................................................... 8 f fail-safe clock monitor (fscm) and wdt ..................................................................... 79 delay........................................................................... 79 slow oscillator start-up ............ .................................. 79 flash program memory..................................................... 115 control registers ...................................................... 119 operations ................................................................ 119 programming algorithm ............................................ 120 rtsp operation........................................................ 119 i i/o pin control............................ 92, 238, 240, 382, 408, 438, 486, 487, 516, 547, 548, 554 i/o pins ............................................................................. 301 i/o ports .................................................................... 305, 425 parallel i/o (pio)............................................... 322, 434 i 2 c addresses ................................................................. 411 baud rate generator ................................................ 409 general call address support .................................. 411 interrupts................................................................... 409 ipmi support ............................................................. 411 master mode operation clock arbitration................................................ 412 multi-master communication, bus collision and bus arbitration..................... 412 operating modes ...................................................... 409 registers................................................................... 409 slave address masking ............................................ 411 slope control ............................................................ 412 software controlled clock stretching (stren = 1) ..................................................... 411 idle mode wake-up from on interrupt ........................................ 534 in-circuit serial programming (icsp) ............................... 581 in-circuit debugging ................................................. 582 interface .................................................................... 581 operation .................................................................. 581 initialization ....................................................................... 514 input change notification.................................................. 324 internal fast rc oscillator (frc) ....................................... 76 postscaler mode (frcdiv) ........................................ 76 with pll mode (frcpll) ........................................... 76 internal low-power rc oscillator (lprc) .......................... 76 enabling ...................................................................... 77 interrupts coincident with power save instructions.......... 535 j jtag device programming ................................................ 582 instructions ............................................................... 584 registers .................................................................. 583 jtag boundary scan ....................................................... 582 l low-power secondary oscillator (sosc) .......................... 75 continuous operation................................................. 75 enabling...................................................................... 75 m mplab asm30 assembler, linker, librarian ................... 590 mplab icd 2 in-circuit debugger ................................... 591 mplab ice 2000 high-performance universal in-circuit emulator .................................................... 591 mplab integrated development environment software .............................................. 589 mplab pm3 device programmer .................................... 591 mplab real ice in-circuit emulator system ................ 591 mplink object linker/mplib object librarian ................ 590 n non-maskable traps ........................................................ 126 o open-drain configuration................................................. 323 oscillator osc1, osc2 pin functions in non-crystal modes............................................. 81 output compare ............................................................... 374 registers .................................................................. 382 output compare registers ....................................... 538, 550 p packaging ......................................................................... 631 details....................................................................... 632 marking ..................................................................... 631 phase locked loop (pll) ............................................ 73, 77 lock status........................................................... 75, 77 pic32 family usb interface diagram .............................. 242 picstart plus development programmer..................... 592 pinout descriptions pic32 family ........................................................ 16, 24 power-on reset (por) and on-chip voltage regulator................................ 576 power-saving modes control registers........................... 522 primary oscillator (posc)............................................ 71, 72 operating modes ............................................ 71, 74, 81 selecting ..................................................................... 71 pulse width modulation mode .......................................... 380 pulse-width modulation mode.......................................... 378 duty cycle ................................................................ 379 period ....................................................................... 379
? 2008 microchip technology inc. preliminary ds61143e-page 643 pic32mx3xx/4xx r rcon register bit status during initialization ..................................... 90 using the rcon status bits ....................................... 90 refer ................................................................................. 236 registers 10-bit a/d converter special function...................... 492 ad1con1 (a/d control 1) ........ 494, 498, 499, 500, 501 ad1con2 (a/d control 1) ........................................ 496 adchs a/d input select .......................................... 499 adpcfg a/d port configuration .............................. 500 cmcon (comparator control) ......................... 540, 542 osccon (oscillator control) ............................. 57, 523 rcon (reset control) ................................................ 86 reset brown-out reset (bor) .............................................. 89 configuration mismatch .............................................. 89 mclr reset ............................................................... 88 power-on reset (por) ............................................... 88 software reset instruction (swr) ........................... 88 watchdog time-out reset (wdtr) ............................ 89 rtcc alarm configuring ....................................................... 480 mask settings ................................................... 480 operation calibration......................................................... 483 write lock ......................................................... 478 s selecting a/d conversion clock ....................................... 506 selecting the voltage reference source .......................... 505 serial peripheral interface (spi) ........................ 83, 197, 383, 439, 467, 555 setup for continuous output pulse generation................ 378 setup for single output pulse generation ........................ 376 sleep mode and fscm delay....................................................... 530 clock selection on wake-up from............................. 529 delay on wake-up from ............................................ 529 delay times for exit.................................................. 529 slow oscillator start-up .............. ...................................... 530 software simulator (mplab sim)..................................... 590 special features ............................................................... 565 spi error handling........................................................... 405 t test access port (tap), controller................................... 583 timer1 module .......................................... 125, 177, 327, 339 timing diagrams 10-bit a/d conversion (chps = 01, simsam = 0, asam = 0, ssrc = 000) ............ 624 i2cx bus data (master mode) .................................. 617 i2cx bus data (slave mode) .................................... 619 i2cx bus start/stop bits (master mode) ................... 617 i2cx bus start/stop bits (slave mode) ..................... 619 input capture (capx)................................................ 609 oc/pwm................................................................... 610 output compare (ocx)............................................. 609 parallel master port write ................................. 627, 628 parallel slave port .................................................... 626 spix master mode (cke = 0) ................................... 611 spix master mode (cke = 1) ................................... 612 spix slave mode (cke = 0) ..................................... 613 spix slave mode (cke = 1) ..................................... 615 timer1, 2, 3, 4, 5, 6, 7, 8, 9 external clock .............. 607 timing requirements clko and i/o ........................................................... 604 timing specifications i2cx bus data requirements (master mode)........... 618 i2cx bus data requirements (slave mode)............. 619 output compare requirements................................ 610 simple oc/pwm mode requirements ..................... 610 spix master mode (cke = 0) requirements............ 611 spix master mode (cke = 1) requirements............ 612 spix slave mode (cke = 1) requirements.............. 616 u uart infrared support........................................................ 436 irda built-in encoder and decoder........................... 436 external support, clock output ........................ 436 operation of uxcts and uxrts control pins ......... 436 receiving 8-bit or 9-bit data mode.................................... 436 transmitting break and sync sequence ............................... 436 usb interrupts .................................................................. 298 operation.................................................................. 278 v v ddcore /v cap pin ........................................................... 576 voltage reference specifications..................................... 600 voltage regulator (on-chip) ............................................ 576 w watchdog timer ............................................................... 561 enabling and disabling............................................. 561 operation.................................................................. 561 period selection ....................................................... 561 prescalers................................................................. 562 resetting .................................................................. 561 software controlled .................................................. 561 www, on-line support ..................... .................................. 8
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